TW201520797A - Device and method for checking printed circuitry - Google Patents

Abstract

A method and device for checking printed circuitry is provided. First a circuit layout is obtained, the layout recording a first layer and a second layer. The first layer in turn records multiple nets, each of which has a name and corresponds to a first set of coordinates on a coordinate system. The second layer also corresponds to a second set of coordinates on the coordinate system. Then a keyword string is obtained, and, for each net, when its name includes the keyword string, its corresponding first set is compared with the second set. The present invention is capable of checking automatically for voids within the nets.

Description

Printed circuit inspection method and device

The present invention relates to printed circuit boards, and more particularly to methods and apparatus for inspecting whether a line has entered a void area during the design phase.

Electronic design automation (EDA) is currently focused on checking production problems and erroneous circuit designs, while also assisting in detecting signal and voltage between the conductor layer and the plane layer. The interference is actually done by making a copper-breaking inspection of all the lines (net) in the copper foil area on the board layer and then hand-by-hand visual comparison. When these methods are used in the past, they are easy to flow in a hundred meters. In particular, the disadvantage is that they are not targeted. All lines must be inspected, and there is no way to break the copper phenomenon across the copper foil.

In view of the above problems, the present invention is directed to a printed circuit inspection method and a printed circuit inspection device capable of automatically checking a copper break condition of a line.

The invention provides a printed circuit inspection method, the steps comprising: Obtaining a circuit layout (recording) having a first layer and a second layer, the first layer recording a plurality of lines, each line having a code, and each line corresponding to the first set of the plurality of coordinates on the coordinate system The second layer also corresponds to the second set of the plurality of coordinates on the coordinate system; receiving a key string; and for each line, when the code of the line includes the foregoing keyword string, comparing the second set to the line corresponding to the line The first collection of.

The invention also provides a printed circuit inspection device, including a layout Modules, input modules and inspection modules. The layout module is used to provide a circuit layout, which records the first layer and the second layer. The first layer records a plurality of lines, the lines have codes, and each line corresponds to a plurality of coordinates on the coordinate system. A set, the second layer also corresponding to the second set of coordinates on the coordinate system. The input module is configured to receive a keyword string. The inspection module is coupled to the layout module and the input module for comparing the first set corresponding to one of the second set and the line; the code of the line includes the keyword string.

In summary, the printed circuit inspection method and device operation of the present invention For a circuit layout, the first layer of the circuit layout records the netlist, and the second layer is associated with certain rules that the line must follow. Comparing the selected line and the second layer of coordinates (or an image composed of pixels), the difference is the copper break. Since the line is selected according to a certain keyword string, the inspection of the present invention is targeted and meets the needs of the circuit designer.

The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the spirit and principles of the invention The scope of the patent application of the present invention is further explained.

10‧‧‧Layout module

12‧‧‧Image Processing Module

14‧‧‧Input module

16‧‧‧Check module

3‧‧‧ coordinate system

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a high level block diagram of a printed circuit inspection apparatus in accordance with an embodiment of the present invention.

Fig. 2 is a flow chart showing a method of inspecting a printed circuit in accordance with an embodiment of the present invention.

Figure 3 is a schematic illustration of a first set of coordinates corresponding to a line.

Figure 4A is a schematic illustration of a second set of a plurality of coordinates corresponding to a ply.

Figure 4B is a schematic diagram of a third set of a plurality of coordinates corresponding to a ply.

Figure 4C is a schematic diagram of the relative complement of the third set corresponding to a layer in the first set corresponding to a line.

Figure 5A is a schematic illustration of a second set of coordinates of a forbidden via region.

Figure 5B is a schematic diagram of the relative complement of the second set corresponding to a forbidden through-hole region in the first set corresponding to a line.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the invention. The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

See Figure 1. Figure 1 is printed in accordance with an embodiment of the present invention A high-order block diagram of the brush circuit inspection device. As shown in FIG. 1, the printed circuit inspection apparatus includes a layout module 10, an image processing module 12, an input module 14, and an inspection module 16. The layout module 10, the image processing module 12, and the inspection module 16 are coupled to each other, and the inspection module 16 is coupled to the input module 14.

Please refer to Figure 2 in conjunction with Figure 1. Figure 2 is in accordance with the present invention A flow chart of an embodiment of a printed circuit inspection method. As shown in FIG. 2, in step S201, the layout module 10 provides a circuit layout, which may be one or more files in the electronic design automation. The circuit layout records the first layer and the second layer, wherein the first layer may be a trace layer, and the trace layer includes a line list composed of a plurality of lines. In this embodiment, the second layer represents a slab layer, which may be a ground plane or a power plane. Generally speaking, the position of the line on the trace layer needs to be protected by the corresponding conductive copper foil in the layer, but the trace layer and the layer are independent individuals, and the circuit design process may be different, that is, A situation called copper breaking.

As mentioned earlier, there is a set of implicit finite coordinates in the circuit layout. The first layer and the second layer correspond to each other. Specifically, each line on the trace layer corresponds to a narrow area (the line has a width) in the image of the trace layer, and the pixels of the area correspond to the first set of coordinates on the coordinate system, as shown in FIG. . In Fig. 3, a line corresponds to a slashed area on the coordinate system 3 which can be marked as (2, c), (2, d), (3, c) with coordinates up to (6, d). Similarly, the layer (image) also corresponds to the second set of coordinates on the coordinate system. The layer image referred to here refers to the positive (positive), that is, when the layer is observed with the naked eye. The appearance of the situation. In step S203, the image processing module 12 obtains a third set of coordinates in the coordinate system that is complementary to the second set, that is, a plurality of coordinates corresponding to the area of the layer that does not have any copper foil or components. In other words, step S203 corresponds to the negative processing of the slice layer image by the image processing module 12. For example, the ply image positive film shown in the shaded area in FIG. 4A and the ply image negative film shown in the oblique line area in FIG. 4B are in an absolute complement relationship in the limited coordinate system 3.

In step S205, the input module receives a keyword string. Each line in the line table has its code or name; when the naming conforms to a specific rule, for example, the clock signal line starts with "CLK_", and the user inputs "CLK" as a keyword string to search for all the lines. Clock signal line. In an embodiment, the keyword string is entered by the user. In another embodiment, the printed circuit inspection apparatus of the present invention presets one or more key strings.

In step S207, the checking module 16 compares the matching keyword string. The first set corresponding to one line and the second set corresponding to the board layer. Specifically, the checking module 16 obtains a relative complement of the third set in the first set, that is, calculates a difference between the first set minus the third set. In terms of image processing, the inspection module 16 performs a logical non-NO operation on the image of the line (such as FIG. 3) as a negative of the layer image (eg, FIG. 4B) to obtain a slash as shown in FIG. 4C. region. In step S209, the checking module 16 determines whether there is a change in the image of the line, such as whether the area of the line is reduced, that is, comparing the first set and the aforementioned relative complement. When judging that the first set is not equal to the aforementioned phase For the complement, if the diagonal line area of FIG. 4C is less than the two pieces of copper broken with coordinates (4, c) and (4, d), the inspection module 16 records the line in step S211. At least one error point on the above, such as the missing coordinates in the foregoing relative set, and returning to step S207 to continue checking other lines that match the keyword string. The recording of the error points is for subsequent processing. For example, in an embodiment, the layout module 10 can display the circuit layout of the portion adjacent to the error point, or in another embodiment, the inspection module 16 can automatically modify the error point. The part of the circuit layout. In step S209, when it is determined that the first set is equal to the aforementioned relative complement, the checking module 16 returns to step S207 to continue checking other lines that match the key string.

In another embodiment, the second layer is at least one prohibited through hole region (via keepout), which specifies the area where copper is exposed on the trace layer (so there is no line, and the line is broken for copper), but the area of the via cannot be placed, as shown by the shaded area in Figure 5A. Since the definition of the forbidden through-hole area is already empty, the image processing module 12 does not need to obtain its negative film to compare with the first set corresponding to the line of the keyword string. The checking module 16 obtains the relative complement of the second set corresponding to the forbidden through-hole area in the first set, or performs the image of the second layer (such as FIG. 3) with the image of the second layer (as shown in FIG. 5A). The NOT operation can obtain a slashed area as shown in Fig. 5B, which is the place where the copper break occurs when the two coordinates of the coordinates (3, c) and (4, c) which are missing from the third figure.

In summary, the printed circuit inspection method and device of the present invention can be Automatically check the copper-breaking condition of a particular line in the circuit layout, especially when the line crosses the copper foil of the board or touches the forbidden through-hole area, avoiding the artificial carpet type Inefficiency in search and correction.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

Claims (10)

A printed circuit inspection method includes: obtaining a circuit layout, the circuit layout recording a first layer and a second layer, the first layer recording a plurality of lines, each of the lines having a code and corresponding to a label a first set of a plurality of coordinates, the second layer corresponding to a second set of coordinates on the coordinate system; receiving a key string; and for each of the lines, when the code of the line includes the keyword In the case of a string, the second set and the first set corresponding to the line are compared. The printed circuit inspection method of claim 1, wherein the comparing the second set with the first set corresponding to the line comprises: obtaining a third set complementary to the second set on the coordinate system; and obtaining a relative complement of the third set in the first set; wherein when the relative complement is not equal to the first set, at least one error point on the line is recorded. The printed circuit inspection method of claim 2, wherein the second layer is a layer, the layer corresponds to a layer image, the second set corresponds to a positive image of the layer image, and the third set corresponds to the board The negative of the layer image. The printed circuit inspection method of claim 1, wherein the second layer is at least one forbidden through-hole area, and the step of comparing the second set and the first set corresponding to the line comprises: Obtaining a relative complement of the second set in the first set; wherein when the relative complement is not equal to the first set, recording at least one error point on the line. The printed circuit inspection method of claim 2 or 4, further comprising: displaying the portion of the circuit layout adjacent to the error point. A printed circuit inspection device includes: a layout module for providing a circuit layout, the circuit layout recording a first layer and a second layer, the first layer recording a plurality of lines, each of the lines having a a code corresponding to a first set of a plurality of coordinates on a label, the second layer corresponding to a second set of coordinates on the coordinate system; an input module for receiving a keyword string; and an inspection The module is coupled to the layout module and the input module for comparing the second set and the first set corresponding to one of the lines, and the code of the line includes the keyword string. The printed circuit inspection device of claim 6, further comprising: an image processing module coupled to the layout module for obtaining a third set complementary to the second set on the coordinate system; When the checking module compares the second set with the first set corresponding to the line, the checking module obtains a relative complement of the third set in the first set, and when the relative complement is not equal to the first When collecting, the inspection module is further used to record at least one error point on the line. The printed circuit inspection device of claim 7, wherein the second layer is a board layer, the board layer corresponds to a layer image, the second set corresponds to a positive film of the layer image, and the third set corresponds to the board The negative of the layer image. The printed circuit inspection apparatus of claim 6, wherein the second layer is at least one forbidden through hole area, and when the inspection module compares the second set and the first set corresponding to the line, the checking The module obtains a relative complement of the second set in the first set, and when the relative complement is not equal to the first set, the check module is further configured to record at least one error point on the line. The printed circuit inspection device of claim 7 or 9, wherein the layout module is further configured to display a portion of the circuit layout adjacent to the error point.