JPH1145822A - Thin-film capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film capacitor having a low inductance structure which can be readily mounted and readily laminated. SOLUTION: A first capacitance element A having a positive electrode layer 2 on the upper surface of a dielectric layer 1 and a negative electrode layer 3 on the lower surface thereof, and a second capacitance element B having the negative electrode layer 3 on the upper surface of the dielectric layer 1 and the positive electrode layer 2 on the lower surface thereof, are placed in parallel. The positive electrode layers 2 and the negative electrode layers 3 of the first capacitance element A and the second capacitance element B are connected via a connecting terminal electrode 5 to constitute a capacitor element C. A plurality of the capacitor elements C are arranged being kept away from each other. The uppermost positive electrode layer 2, and the uppermost negative electrode layers 3 of the plural capacitor elements C are respectively electrically connected by means of terminal members through respective capacitance take-out members 10, 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film capacitor, for example, a large-capacity, low-inductance thin-film capacitor provided in an electric circuit operating at high speed and used for bypassing high-frequency noise or preventing fluctuations in power supply voltage. It relates to a thin film capacitor.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in the electronic devices to be smaller, thinner, and compatible with high frequencies.

In particular, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is from 100 MHz to several hundred MHz, and the clock frequency of the bus between chips is also from 30 MHz, even at the personal computer level. The high-speed operation is remarkable at 75 MHz.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

In order to reduce the size and the capacity of a capacitor, it is most effective to make the dielectric sandwiched between the pair of electrodes thinner and thinner. The thinning also conforms to the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these functions, the function of the capacitor, which is particularly important in the function of removing high-frequency noise, is that the instantaneous drop of the power supply voltage that occurs when simultaneous switching of logic circuits occurs at the same time is a measure of the energy stored in the capacitor. This function is reduced by supplying the This is a so-called decoupling capacitor.

[0007] The performance required of the decoupling capacitor lies in how quickly the current can be supplied in response to the current fluctuation in the load section faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, an actual capacitor has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases with increasing frequency, and the inductance component increases with increasing frequency. For this reason, as the operating frequency increases, the transient current to be supplied by the inductance of the element is limited, and the power supply voltage on the logic circuit side instantaneously drops or new voltage noise is generated. As a result, an error occurs in the logic circuit.

Particularly, in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements.
The allowable fluctuation range of the power supply voltage is also small. Therefore, it is very important to reduce the inductance of the decoupling capacitor element itself in order to minimize the voltage fluctuation width during high-speed operation.

There are three ways to reduce inductance. The first is a method for minimizing the length of the current path, the second is a method for minimizing the loop cross-sectional area by forming the current path into a loop structure, and the third is a method of distributing the current path into n pieces to reduce the effective inductance by one. / N.

The first method may be achieved by increasing the capacity per unit area to achieve miniaturization, and can be achieved by reducing the thickness of the capacitor element. For the purpose of obtaining a capacitor having a large capacity and good high-frequency characteristics, Japanese Patent Application Laid-Open No. 60-94716 discloses a capacitor in which the thickness of a dielectric material is reduced to 1 μm or less.

The second method has an effect of reducing the magnetic field formed by one current path by the magnetic field formed by another adjacent current path. Therefore, a pair of electrode plates or electrodes forming a capacitor is used. The directions of the currents flowing through the layers should not be in the same direction as much as possible.

In the third method, low inductance can be achieved by connecting the divided capacitors in parallel.
As such a capacitor, Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-Open Publication No. H11-163,887 discloses a device using a thin film dielectric layer.

[0014]

However, when considering a decoupling capacitor that can be mounted at a desired place, the size that can be handled is 0.5 mm × 0.5 mm.
mm or more is required, and there is a limit to reducing the inductance by only the first thin film and the method of miniaturization.

Further, in the second method, the positive and negative terminal electrodes need to be at the same end face or orthogonal to each other, which is disadvantageous in mounting.

In the third split parallel connection method, for example,
Normal multilayer capacitors are also connected in parallel, but since the directions of the currents are the same, the magnetic fields formed by the respective electrode currents are superimposed. That is, since the mutual inductance becomes large, the effective total inductance cannot be sufficiently reduced. Therefore, it was necessary to employ the second means together, but as described above, there was a mounting problem due to the problem of the terminal electrode.

An object of the present invention is to provide a split-parallel connection type thin film capacitor having a low inductance structure that is easy to mount and easy to stack.

[0018]

According to the present invention, there is provided a thin film capacitor comprising: a first capacitor having a first electrode layer formed on an upper surface of a dielectric layer and a second electrode layer formed on a lower surface; A two-electrode layer and a second capacitor having a first electrode layer formed on a lower surface are juxtaposed, and the first electrode layers of the first capacitor element and the second capacitor element and the second electrode layers of the second capacitor element are connected to each other. A plurality of capacitor elements connected via connection terminal electrodes are arranged in a spaced state, and the first electrode layers and the second electrode layers of the plurality of capacitor elements are
Each is electrically connected by a capacity take-out member.

Also, a plurality of electrode layers and a plurality of dielectric layers are alternately laminated, and the first and second electrode layers are alternately stacked from the bottom.
A first capacitive element serving as an electrode layer or a second electrode layer, and a plurality of electrode layers and a plurality of dielectric layers are alternately laminated, and the electrode layers are alternately arranged from below on the second electrode layer or the second electrode layer. Along with juxtaposing the second capacitance element formed as one electrode layer,
A capacitor element and the second electrode layer of the second capacitor element and the second electrode layer are arranged with a plurality of capacitor elements connected via connection terminal electrodes spaced apart from each other;
Further, the first electrode layers and the second electrode layers of the plurality of capacitor elements are electrically connected to each other by a capacitance extracting member.

[0020]

In the thin film capacitor of the present invention, first, since a pair of capacitance elements are juxtaposed at a predetermined interval, the pair of capacitance elements are provided on the same plane with the first electrode layer (for example, the positive electrode layer). ) And a second electrode layer (for example, a negative electrode layer) are formed, and the positive electrode layer and the negative electrode layer can be formed close to each other, so that the current path is shortened and the inductance is reduced. Can be smaller.

Second, the directions of the currents flowing through the positive electrode layer and the negative electrode layer of each of the capacitive elements are opposite to each other, and the generated inductances are canceled out and can be reduced.

Third, by connecting a plurality of capacitor elements composed of a pair of capacitance elements in parallel, the current path becomes n
And the effective inductance can be reduced to 1 / n times.

Fourth, since the respective electrode layers of the pair of capacitive elements can be connected by the connection terminal electrodes formed on the opposing surfaces thereof, the lamination is facilitated. Further, since the capacitance extracting member used for the contact with the outside can be formed, for example, on the uppermost electrode layer, the mounting is facilitated.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a single-plate type thin film capacitor according to the present invention, a pair of capacitive elements having a positive electrode layer and a negative electrode layer formed on the upper and lower surfaces of a dielectric layer are opposed to each other at a predetermined interval. At the same time, the electrode layer formed at a position facing the pair of capacitors is an electrode layer having a different polarity, and further, the positive electrode layer and the negative electrode layer of the pair of capacitors are directed toward the facing capacitor. A protruding connection terminal electrode is formed, the connection terminal electrodes of the electrode layers having the same polarity in a pair of capacitance elements are connected to each other to produce a capacitor element, and a plurality of such capacitor elements are arranged in a separated state. The uppermost first electrode layers of the plurality of capacitor elements and the uppermost second electrode layers are electrically connected to each other by a capacitance extracting member, and the capacitor elements are connected in parallel.

Further, in the laminated thin film capacitor of the present invention, a pair of capacitive elements formed by alternately laminating a plurality of electrode layers and a plurality of dielectric layers are arranged opposite to each other at a predetermined interval, and Are alternately positive electrode layers or negative electrode layers in the laminating direction, and the electrode layers formed at positions opposed to the pair of capacitive elements are electrode layers having different polarities. In the layer and the negative electrode layer, connection terminal electrodes protruding toward the opposing capacitance elements are formed, and in the pair of capacitance elements, the connection terminal electrodes of the same electrode layer having the same polarity are connected to each other to form a capacitor element.
Such a plurality of capacitor elements are arranged in a separated state, and the uppermost first electrode layers and the uppermost second electrode layers of the plurality of capacitor elements are electrically connected by a capacitance extracting member, It is formed by connecting capacitor elements in parallel.

FIG. 1 shows a single-plate type thin film capacitor according to the present invention, FIG. 2 is a view for explaining a manufacturing method thereof, and FIG. 3 is an exploded perspective view showing a capacitor element. As shown in FIG. 1, the thin-film capacitor of the present invention is formed by arranging four capacitor elements C each composed of a pair of capacitance elements A and B in a state of being spaced apart in a line.

As shown in FIGS. 3 to 5, a capacitor element C composed of a pair of capacitance elements A and B has a positive electrode layer 2 (first electrode layer) and a negative electrode layer 3 on the upper and lower surfaces of a dielectric layer 1. A pair of capacitance elements A and B formed by forming the (second electrode layer) are juxtaposed to face each other. The electrode layers formed at positions facing the pair of capacitive elements A and B have different polarities. The capacitors A and B are formed on the upper surface of the substrate 4.

That is, the capacitive element A has a positive electrode layer 2 formed on the lower surface of the dielectric layer 1 and a negative electrode layer 3 formed on the upper surface, and the capacitive element B has a negative electrode layer formed on the lower surface of the dielectric layer 1. 3, the positive electrode layer 2 is formed on the upper surface. And the capacitive elements A and B
Are arranged at predetermined intervals, and the negative electrode layer 3 of the capacitive element B is on the same plane as the positive electrode layer 2 of the capacitive element A, and the capacitive element B is on the same plane as the negative electrode layer 3 of the capacitive element A. Of the positive electrode layer 2 is formed.

The positive electrode layer 2 and the negative electrode layer 3 are shown in FIG.
As shown in FIG. 1A, the dielectric layer 1 has a rectangular shape.
As shown in FIG. 6B, the rectangular shape is such that the positive electrode layer 2 or the negative electrode layer 3 formed on the lower surface of the dielectric layer 1 is covered. The dielectric layers 1 are spaced apart from each other at a predetermined interval. The positive electrode layer 2 or the negative electrode layer 3 formed on the upper surface of the dielectric layer 1 is, as shown in FIG. 6C, the positive electrode layer 2 or the negative electrode layer 3 formed on the lower surface of the dielectric layer 1. It has the same shape and the same dimensions.

The thickness of the dielectric layer 1 is 0.1 to 1 μm, and the size is 1.2 mm in length and 1.2 mm in width.
The thickness of the electrode layers 2 and 3 is 0.1 to 1 μm, and the size is 1.0 mm in length and 0.3 mm in width.

A connection terminal electrode 5 is formed on the positive electrode layer 2 and the negative electrode layer 3 of the pair of capacitance elements A and B so as to project toward the opposing capacitance elements A and B, respectively. The connection terminal electrodes 5 of the layers 2 and 3 are connected to each other.

As shown in FIG. 4, the positive electrode connecting portion 7 where the positive electrode layers 2 are connected to each other and the negative electrode connecting portion 8 where the negative electrode layers 3 are connected are spaced apart from each other at a predetermined interval as shown in FIG. And
This is insulated. The space between the positive electrode connection portion 7 and the negative electrode connection portion 8 may be filled with the same material as the dielectric layer 1. In this case, the dielectric layers 1 of the pair of capacitive elements A and B are connected to form an H shape in plan view. A portion between the positive electrode layer 2 and the negative electrode layer 3 and between the positive electrode connection portion 7 and the negative electrode connection portion 8, that is, FIG.
May be filled with the same material as the dielectric layer 1. In FIG. 5, the negative electrode connecting portion 8 is omitted for the sake of explanation.

In the thin film capacitor of the present invention, a capacitor element C comprising a pair of capacitance elements A and B
As shown in (a), the four capacitors are arranged in a line at a predetermined interval, thereby insulating the capacitor elements C from each other. The same material as the dielectric layer 1 may be filled in the space N between the four capacitor elements C. In this case, the dielectric layers 1 of the capacitor elements C are connected.

The uppermost positive electrode layers 2 and the uppermost negative electrode layers 3 of the four capacitor elements C are connected to each other as shown in FIG.
As shown in the figure, the capacitors are electrically connected by the capacity take-out members 10 and 11. The capacitance extracting members 10 and 11 are formed in a thin plate made of a conductive material.
Reference numeral 11 is connected via a joint 13. In FIG. 1, for easy understanding, the dielectric layer 1 is drawn by broken lines, and the electrode layers 2 and 3 on the lower surface of the dielectric layer 1 are omitted.

The shape of the bonding portion 13 is, for example, a bump shape, a foil shape, a plate shape, a line shape, or a paste shape, and is not particularly limited. A plurality of shapes may be combined. The material is solder, Au, Cu, Pt, Pd, Ag, A
There are l, Ni, conductive resin and the like, as long as they are conductive, and a plurality of materials may be combined. The material of the capacity take-out members 10 and 11 is the same as that of the joint 13. Although the capacitance extracting members 10 and 11 are formed in a thin plate shape, for example, the uppermost positive electrode layers 2 and the uppermost negative electrode layers 3 may be connected by a wire such as a lead wire.

The thin film capacitor of the present invention is
The positive electrode layer 2 and the negative electrode layer 3 are formed as shown in FIG. 2A, and the dielectric layer 1 is formed on the upper surfaces of the positive electrode layer 2 and the negative electrode layer 3 as shown in FIG. The positive electrode layer 2 and the negative electrode layer 3 are formed on the upper surface of the dielectric layer 1 as shown in FIG.
(C), and further, as described above,
For example, a pump-shaped joint portion 13 is formed, and on this upper surface,
As shown in FIG. 2D, it is manufactured by forming the capacity takeout members 10 and 11.

As the substrate 4 used in the present invention, alumina, sapphire, MgO single crystal, SrTiO ₃ single crystal, titanium-coated silicon, or copper (Cu), nickel (Ni), titanium (Ti), tin (Sn) A stainless steel (SUS) thin film or thin plate is desirable. In particular, alumina and sapphire are desirable in terms of low reactivity with the thin film, low cost and high strength, and crystallinity of the dielectric film or the electrode film, and copper (Cu) thin plate or A copper (Cu) thin film is desirable.

The electrode layer of the present invention comprises platinum (Pt), gold (A
u), palladium (Pd), copper (Cu) thin film, etc.
Among these, platinum (Pt) and gold (Au) thin films and low-resistance copper (Cu) thin films are optimal. This is because Pt and Au have low reactivity with the dielectric and are hardly oxidized, so that a low dielectric constant phase is hardly formed at the interface with the dielectric.

Further, the dielectric layer may have a high dielectric constant in a high-frequency region, and its thickness is 1 μm.
m or less is desirable. The dielectric layer is, for example, a dielectric thin film made of a perovskite-type composite oxide crystal containing Pb, Mg, and Nb as metal elements.
A dielectric thin film having a relative dielectric constant of 1000 or more at 00 MHz (room temperature) is desirable. In the present invention, Pb, Mg,
Other than a dielectric thin film composed of a perovskite-type composite oxide crystal containing Nb, for example, a perovskite-type composite oxide crystal containing Ba and Ti, PZT, PLZT, SrTiO
₃ , Ta ₂ O ₅ or the like may be used without any particular limitation. Such a dielectric layer is manufactured by a known method such as a PVD method, a CVD method, and a sol-gel method.

In the thin film capacitor configured as described above, first, the pair of capacitance elements A and B are formed to face each other. The electrode layer 2 and the negative electrode layer 3 are formed at predetermined intervals, and the positive electrode layer 2 and the negative electrode layer 3 are formed.
Can be formed close to each other, so that the current path can be shortened and the inductance can be reduced.

Second, since the directions of the currents flowing through the positive electrode layer 2 and the negative electrode layer 3 in the individual capacitance elements are opposite to each other, the inductances of the respective positive electrode layers 2 and the negative electrode layer 3 cancel each other out, and the generated currents are different. Inductance can be reduced.

Third, by connecting four capacitor elements C composed of a pair of capacitive elements in parallel, a current path of 4
And the effective inductance can be reduced to 1/4 times.

Fourthly, since the capacitance take-out members 10 and 11 used for the contacts between the capacitor elements C and the contacts with the outside can be formed on the uppermost electrode layers 2 and 3, the mounting becomes easy. .

The laminated type thin film capacitor of the present invention will be described with reference to FIG. According to FIG. 7, a dielectric layer and an electrode layer are further laminated on the structure of the pair of single-plate type capacitors shown in FIG.

That is, a pair of capacitive elements A and B, in which the electrode layers 2 and 3 and the dielectric layer 1 are alternately laminated, are juxtaposed. In these capacitive elements A and B, the electrode layers 2 and 3 are stacked in the laminating direction. The positive electrode layer 2 and the negative electrode layer 3 are alternately formed. The electrode layers 2 and 3 formed at opposing positions of the pair of capacitance elements A and B are electrode layers 2 and 3 having different polarities, and the positive electrode layer 2 and the negative electrode layer of the pair of capacitance elements A and B are formed. 3, a connection terminal electrode 5 protruding toward the opposing capacitance elements A and B is formed. The connection terminal electrodes 5 of the electrode layers 2 and 3 having the same polarity are electrically connected to each other, thereby forming the capacitor element C.

The laminated capacitor elements C are arranged in an arrangement as shown in FIG.
A capacitance extraction member 10 formed on the uppermost electrode layers 2 and 3;
The electrode layers having the same polarity are electrically connected to each other through the connection line 11.

The thin film capacitor of the present invention is generally formed on the surface of the substrate 4 for use as described above, but may be used by being built in the substrate. When incorporated in the substrate, the capacitance extracting member is, for example, a through-hole conductor formed in the substrate, thereby extracting the capacitance.

Further, although an example in which the shape of the electrode layers 2 and 3 is rectangular has been described, any shape such as a square or a circle may be used.

Although an example in which four capacitor elements C are arranged in one column has been described, two or more elements may be arranged, and the arrangement method, that is, the number of rows and the number of columns is particularly questioned. is not.

[0050]

【Example】

Example 1 An electrode layer and a dielectric layer were all formed by using a high-frequency magnetron sputtering method. Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation.

A substrate holder and three target holders are provided in the process chamber, and sputtering from three types of target materials is possible. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.

A high-frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high-frequency power supply, and a high-density plasma is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. Then, the target surface was sputtered.

High-frequency voltage can be applied to three targets independently. In this embodiment, plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant.

Also, three types of metal masks having a thickness of 0.05 mm are provided on the target side of the substrate placed on the substrate holder, and necessary masks can be set on the substrate deposition surface according to the deposition pattern. Structured.

First, a 4 × 1 connection terminal electrode as shown in FIG. 2A was formed on a 0.25 mm thick alumina sintered body substrate by sputtering a platinum target with a first mask pattern. forming a pair of electrode layers, followed with _{Pb (Mg 1/3 Nb 2/3} ) O 3 sintered body target, the second mask pattern is set, a substrate temperature of 535 ° C., the conditions of RF power 200W Thus, a pair of dielectric layers as shown in FIG. 2B was formed. Next, a third mask pattern is set, and sputtering of a platinum target is performed as shown in FIG.
A pair of electrode layers having the connection terminal electrodes of 4 rows × 1 column as shown in FIG. The total area of the electrode layers was 2.4 mm ² .

Two Au wires having a line width of 0.3 mm were connected to the four thin film capacitors thus prepared through solder bumps by 0.6 m.
It was connected to conductor patterns arranged at m intervals, and the electrical characteristics were evaluated. The used solder pumps had a diameter of 0.2 mm and were formed two on each electrode layer. The capacity take-out member in this case is A
It becomes u line.

1 MHz of the manufactured laminated thin film capacitor
The impedance characteristics at 1.8 GHz can be measured using an impedance analyzer (HP by Hewlett-Packard Company).
4291A), the capacitance component was 51.
A value of 2 nF and an inductance component of 50 pH was obtained. After the above measurement, when the cross section of the thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.3 μm.

As a comparative example, except for the structure of a conventional general thin film capacitor as shown in FIG. 8, conditions such as the total area of the electrode layers (2 mm × 1.2 mm) were set in the same manner as described above. When the capacitance component and the inductance component were measured, the capacitance component obtained a value of 51.0 nF and an inductance component of 420 pH. In FIG. 8, the conventional thin-film capacitor includes a positive electrode layer 2
1, a dielectric layer 22 and a negative electrode layer 23 are sequentially laminated, and a capacity take-out portion 24 is formed on the positive electrode layer 21 and the negative electrode layer 23 on the opposite side.

Embodiment 2 Using the same method as in Embodiment 1, two capacitor elements C
Were prepared in an array of 2 rows × 1 column, and evaluated in the same manner as in Example 1. As a result, a value of 25.4 nF for the capacitance component and a value of 95 pH for the inductance component were obtained.

Embodiment 3 Using the same method as in Embodiment 1, four capacitor elements C
Were prepared in an array of 2 rows × 2 columns, and evaluated in the same manner as in Example 1. As a result, a capacitance component of 51.2 nF and an inductance component of 50 pH were obtained. Capacitor elements in a 2 row × 2 column array have a line width of 0.3 mm via solder bumps.
These two Au wires were connected to a rape-shaped conductor pattern arranged at intervals of 0.6 mm and evaluated.

Example 4 The measuring jig and the thin film capacitor were connected via the conductive adhesive and the Au bump by using the same method as in Examples 1 to 3. No difference was found in the capacitance component and the inductance component.

Embodiment 5 The measuring jig and the thin film capacitor were connected via Au wire bonding having a diameter of 0.1 mm using the same method as in Embodiments 1 to 3. No difference was found in the obtained capacitance component and inductance component.

Example 6 A laminated thin-film capacitor having 10 dielectric layers was manufactured in exactly the same manner as in Example 1, and evaluated by the same method as in Example 1. The capacitance component was 508.2 nF, and the inductance component was 5
A value of 0 pH was obtained. After the above measurement, when the cross section of the multilayer thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.3 μm.

Example 7 A substrate material, an electrode material, an electrode forming method, a shape and dimensions were exactly the same as in Example 1, and only a dielectric film was formed by a sol-gel method. The procedure for producing a film by the sol-gel method was as follows.

Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 2-methoxyethanol (1).
24 hours at 24 ° C.), and a MgNb composite alkoxide solution (Mg = 4.95 mmol, Nb10.05 mmol)
1, 2-methoxyethanol 150 mmol) was synthesized. Next, 15 mmol of lead acetate (anhydride) and 150 mmol
l of 2-methoxyethanol was mixed, and a Pb precursor solution was synthesized by a distillation operation at 120 ° C.

The MgNb precursor solution and the Pb precursor solution are mixed at a molar ratio of Pb: (Mg + Nb) = 1: 1,
Stir well at room temperature and add Pb (Mg _1/3 Nb _2/3 ) O ₃ (P
(MN) precursor solution was synthesized.

The solution was diluted about 3-fold with 2-methoxyethanol to obtain a coating solution. Next, on the electrode layer,
The coating solution was applied by a spin coater, dried, and then heat-treated at 300 ° C. for 1 minute to form a gel film. After repeating the application of the coating solution and the heat treatment, 8
Firing at 30 ° C. for 1 minute (in air) is performed, and Pb (Mg
_{A 1/3} Nb _2/3 ) O ₃ thin film was obtained.

A resist is applied on the obtained dielectric thin film, exposed and developed by a photolithography process, and the dielectric film is patterned into the same pattern shape as in Example 1 by wet etching using the resist as a mask. Then, the same thin-layer capacitor as in Example 1 was manufactured.

The impedance characteristics of the manufactured thin film capacitor at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP42, manufactured by Hulett Packard).
91A). As a result, the capacitance component is 20
A value of 1.0 nF and an inductance component of 40 pH was obtained.
After the above measurement, when the cross section of the multilayer thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.5 μm.

[0070]

As described in detail above, in the thin film capacitor of the present invention, the first capacitor in the pair of capacitive elements is located on the same plane.
Since the electrode layer (positive electrode layer) and the second electrode layer (negative electrode layer) are formed, the distance between the positive electrode layer and the negative electrode layer can be reduced, thereby shortening the current path. In addition, the inductance can be reduced. Also, by connecting a plurality of capacitor elements in parallel, the effective inductance can be reduced to 1 / n. Furthermore, since each electrode layer can be connected at the connection terminal electrode, lamination becomes easy. Furthermore, since the capacitor take-out member used for the contact with the outside can be formed on the uppermost electrode layer, the mounting becomes easy. Therefore, according to the present invention, a low-inductance thin-film capacitor that can be easily stacked and mounted can be provided.

[Brief description of the drawings]

1A is a plan view showing a thin film capacitor of the present invention, and FIG. 1B is a side view of FIG.

FIG. 2 is a view for explaining a method for manufacturing a thin film capacitor of the present invention.

FIG. 3 is an exploded perspective view showing a capacitor element of the thin film capacitor of the present invention.

FIG. 4 is a plan view of a capacitor element of the thin film capacitor of the present invention.

FIG. 5 is a side view of the vicinity of a positive electrode connecting portion in FIG. 4;

FIG. 6 is a plan view showing an electrode layer and a dielectric layer of FIG.

FIG. 7 is an exploded perspective view showing a capacitor element of a laminated type thin film capacitor.

FIG. 8 is an exploded perspective view showing a conventional thin film capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Dielectric layer 2 ... Positive electrode layer (1st electrode layer) 3 ... Negative electrode layer (2nd electrode layer) 4 ... Substrate 5 ... Connection terminal electrode A, B ...・ Capacitance element C ・ ・ ・ Capacitor element 7 ・ ・ ・ Positive electrode connection part 8 ・ ・ ・ Negative electrode connection part 10, 11 ・ ・ ・ Capacity extraction member 13 ・ ・ ・ Connection part

Claims (2)

[Claims] 1. A first capacitor having a first electrode layer formed on an upper surface of a dielectric layer and a second electrode layer formed on a lower surface, a second electrode layer formed on an upper surface of the dielectric layer, and a first electrode layer formed on a lower surface. Are formed in parallel with each other, and the first capacitance element and the second capacitance element are arranged side by side.
The first electrode layers and the second electrode layers of the capacitor element are arranged with a plurality of capacitor elements connected via connection terminal electrodes separated from each other, and the first electrode layer of the plurality of capacitor elements is A thin-film capacitor, wherein electrode layers are electrically connected to each other and the second electrode layers are each electrically connected by a capacitance extracting member. 2. A first capacitive element comprising a plurality of electrode layers and a plurality of dielectric layers alternately laminated, wherein the first and second electrode layers are alternately formed as a first electrode layer or a second electrode layer from below. A plurality of electrode layers and a plurality of dielectric layers are alternately stacked, and the electrode layers are arranged side by side with a second capacitor element having a second electrode layer or a first electrode layer alternately from below. Arranging a plurality of capacitor elements formed by connecting the first electrode layers of the first capacitance element and the second capacitance element and the second electrode layers via a connection terminal electrode; A thin-film capacitor, wherein the first electrode layers and the second electrode layers of the plurality of capacitor elements are electrically connected to each other by a capacitance extracting member.