JPH11345936A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of preventing a noise component generated due to the effect of a high speed circuit block, which is quickly switched in a semiconductor, from affecting other circuit block lines and suppressing the noise component. SOLUTION: A semiconductor chip 2 on a semiconductor 1 is formed in a state of being divided into a high speed circuit block 21 and a circuit block 22. The block 21 is connected to a power supply terminal (VCC1) 3 for supplying 1st power supply VCC1 through a bonding wire 6, and the block 22 is connected to plural power supply terminals (VCC2) 4a to 4c for supplying 2nd power supply VCC2 through respective bonding wires 7a to 7c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for suppressing noise generated by high-speed switching of a semiconductor integrated circuit inside or around a semiconductor.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a circuit that performs switching in a plurality of circuits on the same chip sharing a power supply and a ground wiring generates noise and superimposes noise on a ground potential and a power supply potential. It may affect other circuits on the same chip.

To solve this problem, Japanese Patent Application Laid-Open No.
In the semiconductor integrated circuit disclosed in Japanese Patent Application Publication No. 284953, wirings 301 to 43 are individually provided from a power supply terminal 31 to each of circuit blocks 41 to 43 in the semiconductor 30 as shown in FIG.
03 and the ground terminal 32 to the circuit block 4
Wirings 304 to 306 are individually provided for each of 1 to 43.

As a result, other circuits are not affected by noise generated when a circuit in the semiconductor 30 switches, and a normal logic signal can be stably output.

[0005]

In the above-mentioned conventional semiconductor integrated circuit, the wiring from the power supply terminal to each circuit block is individually divided. However, the same power supply terminal of the semiconductor chip is used as the power supply terminal. I have.

Therefore, when there is a circuit block operating at high speed in a semiconductor chip, noise flows into another circuit block via the same power supply point in a narrow semiconductor chip, and the noise passes through a power supply line. As a result, there is a problem that noise flows out to other circuit blocks and the noise level of the entire semiconductor deteriorates.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problem and to prevent noise components generated by the influence of a high-speed circuit block which switches at high speed inside a semiconductor from affecting other circuit block lines. An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing components.

[0008]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a high-speed circuit block including a circuit operating at high speed inside a semiconductor; a circuit block including a circuit other than the high-speed circuit block; And a second power supply terminal provided separately from the first power supply terminal and for supplying power to the high-speed circuit block.

That is, the semiconductor integrated circuit of the present invention divides a power supply signal of a high-speed circuit block inside a semiconductor from a common power supply used in another circuit block, and separates a power supply signal from an external terminal of the common power supply. It has an external terminal.

By providing an external terminal for power supply provided separately from the external terminal of the common power supply, a noise component that is input to a high-speed signal and is generated in the high-speed circuit block unit can be used to reduce noise components in other circuit block units in the semiconductor. It does not flow to another I / O terminal, and noise generated from the semiconductor itself can be reduced.

Further, by dividing the external terminal for supplying power to the high-speed circuit block from the external terminal of the common power supply of another circuit block, it becomes possible to add a noise suppression component to the high-speed circuit block by itself. Further noise reduction can be performed.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor integrated circuit according to one embodiment of the present invention. In the figure, semiconductor 1
The semiconductor chip 2 on which the high-speed circuit block 21 and the circuit block 22 are formed is mounted.

The high-speed circuit block 21 has a first power supply VCC.
1 is connected to a power supply terminal (VCC1) 3 for supplying the second power supply VCC2, and the circuit block 22 is connected to the power supply terminal (VCC1) for supplying the second power supply VCC2.
2) Connected to 4a-4c by bonding wires 7a-7c. Reference numeral 5 denotes a plurality of inner leads provided on the semiconductor 1.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention. In the figure, a semiconductor 1 includes a high-speed circuit block 21 and circuit blocks 22 to 24.
It is composed of

The high-speed circuit block 21 has a power supply terminal (VCC)
1) are connected to 3 via a power supply line 101, the circuit blocks 22 to 25 are connected to a power supply terminal (VCC2) 4 via a power supply line 102, respectively, and the high-speed circuit block 21 and the circuit blocks 22 to 25 are grounded terminals ( GND) 8 via a ground line 103.

Power supply line 101 of high-speed circuit block 21
Is connected to a power supply terminal (VCC1) 3 for supplying power, which is different from a power supply terminal (VCC2) 4 of a common power supply (not shown) used in the other circuit blocks 22 to 24. The generated noise component is determined by the semiconductor 1
Of the other circuit blocks 22 to 24 and I / O (input / output) terminals 111 to 113 to prevent noise from flowing out from the I / O terminals 111 to 113 of the other circuit blocks 22 to 24, 1 reduces noise generated from itself.

First, in a circuit design stage before the semiconductor 1 is created, a clock section or the like that operates at a high speed in a semiconductor block is extracted in advance. In the semiconductor design stage, the extracted block is used as a high-speed circuit block 21 in the semiconductor chip 2 shown in FIG. 1 and a power supply unit (not shown) different from a power supply unit (not shown) for supplying power to other circuit blocks 22. (Not shown).

Here, for simplicity of explanation, the high-speed circuit block 21 is laid out at the end of the semiconductor chip 2 for easy understanding. Power supply units (power supply terminals 3 and 3)
4), the same effect as that of the present invention can be obtained.

In the actual manufacturing stage of the semiconductor 1, the connection of the high-speed circuit block 21 to the power supply section is made by bonding wires 6 only to the power supply terminal (VCC 1) 3 which is an inner lead pin for supplying power. I have to. The power supply to the other circuit blocks 22 is performed in the same manner as before, and the power supply terminals (VCC2) 4, 4
a to 4c. The semiconductor 1 designed as described above has a circuit block configuration in which an external power supply terminal is divided as shown in FIG.

FIG. 3 is a plan view showing a state in which a semiconductor according to one embodiment of the present invention is arranged on a printed circuit board.
FIG. 3 shows a semiconductor 1 formed as described above laid out on an actual printed circuit board 10.

Each of the ground terminals (GND) 8a to 8c is directly connected to a ground layer (not shown),
1 power supply terminal (VCC1)
2) 4a to 4d are also connected to a power supply layer (not shown). Power supply terminal (VCC1) 3 of high-speed circuit block 21
Is divided by using the parasitic inductance of the pattern 9 by drawing a certain pattern line length, that is, by connecting to the common power supply unit with a pattern line length longer than the power supply terminals (VCC2) 4a to 4d.

FIG. 4 is a diagram for explaining the operation inside the semiconductor integrated circuit according to one embodiment of the present invention. The operation inside the semiconductor integrated circuit will be described with reference to FIG.
When a high-speed signal such as a clock is input from the input terminal 13 to the high-speed circuit block 21, a noise 104 is generated in the noise source 21a due to a switching operation in the high-speed circuit block 21 or the like.

This noise 104 is generated by the first power supply (VCC
The power flows out to the power supply line and the output terminal 15 in 1), respectively.
If the same power supply (common power supply 11) is used in the semiconductor chip 2, the noise component flowing through the power supply
04 flows out to another circuit block 22 in the same manner, and the output terminal 16 is affected.

In order to improve this, the common power supply 11 is separated from the power supply line of the high-speed circuit block 21 and utilizes the parasitic inductance due to the inner lead 5, that is, the parasitic inductance derived from the pattern 9 shown in FIG. A parasitic inductance 12 is formed, and this noise 10
4 is prevented from flowing to the other circuit blocks 22 and the output terminal 16, and the noise level of the semiconductor 1 itself is reduced.

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention. In the figure, in another embodiment of the present invention, a common power supply 11 supplies a power supply terminal (VC).
C1) The configuration is the same as that of the embodiment of the present invention shown in FIG. 2 except that the noise suppressing component 17 and the bypass capacitor 18 are added up to 3, and the same components are denoted by the same reference numerals. is there. The operation of the same component is the same as that of the embodiment of the present invention.

The semiconductor 1 according to another embodiment of the present invention has the same configuration as that of the first embodiment of the present invention, but the high-speed circuit block 21 is provided with a separate power supply, so that one embodiment of the present invention If the inductance in the circuit is insufficient, the noise suppression component
By adding the bypass capacitor 18, the noise generated at this portion can be further reduced.

As described above, the power supply line 101 of the high-speed circuit block 2 in the semiconductor 1 is connected to the other circuit blocks 22 to 24.
Power terminals (VCC2) 4, 4 of the common power supply 11 used in
power supply terminal (VCC1) 3 for power supply different from a to 4d
, The noise 104 generated in the high-speed circuit block 21 is transmitted to other blocks 22 to 22 in the semiconductor 1.
24 and I / O terminals 111-113
Outflow of noise from the other I / O terminals 111 to 113 can be prevented, and noise generated from the semiconductor 1 itself can be reduced.

That is, it is possible to prevent the noise 104 generated due to the influence of the high-speed circuit block 21 that switches at high speed inside the semiconductor 1 from affecting the lines of the other circuit blocks 22 to 24, thereby suppressing the noise 104. Can be.

The power supply terminal (VCC1) 3 for supplying power to the high-speed circuit block 21 is connected to the other circuit blocks 22 to 2.
4, the power supply terminal (VCC2) of the common power supply 11 used in 4,
4a to 4d, the high-speed circuit block 2
A noise suppression component 17 such as an inductance can be added to the portion 1. Thereby, the noise 104 generated by the switching of the high-speed circuit block 21 can be further reduced.

That is, the noise level can be further reduced by individually and easily adding the noise suppression component 17 to the noise generation of the semiconductor 1 alone and the generation of the noise 104 from the high-speed circuit block 21. it can.

[0031]

As described above, according to the present invention, a second power supply terminal for supplying power to a high-speed circuit block comprising a circuit operating at high speed inside a semiconductor and a circuit other than the high-speed circuit block are used. By separately installing the first power supply terminal for supplying power to the circuit block, a noise suppression component can be individually and easily provided for noise generation from the semiconductor alone and noise generation from the high-speed circuit block. In addition, there is an effect that the noise level can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 3 is a plan view showing a state in which a semiconductor according to one embodiment of the present invention is arranged on a printed circuit board by wiring.

FIG. 4 is a diagram for explaining an operation inside a semiconductor integrated circuit according to one embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor 2 Semiconductor chip 3 Power supply terminal (VCC1) 4, 4a-4d Power supply terminal (VCC2) 5 Inner lead 6, 7a-7c Bonding wire 8, 8a-8e Ground terminal 9 Pattern 10 Printed circuit board 11 Common power supply 12 Parasitic inductance 17 Noise suppression component 18 Bypass capacitor 21 High-speed circuit block 22-24 Circuit block

Claims (4)

[Claims] A high-speed circuit block including a circuit operating at high speed inside a semiconductor; a circuit block including a circuit other than the high-speed circuit block; a first power supply terminal for supplying power to the circuit block; A second power supply terminal provided separately from the first power supply terminal and configured to supply power to the high-speed circuit block. 2. The semiconductor device according to claim 1, wherein a length of a pattern wiring connected to the second power terminal is longer than a length of a pattern wiring connected to the first power terminal when the semiconductor is mounted on a wiring board. 2. The semiconductor integrated circuit according to claim 1, wherein 3. The semiconductor integrated circuit according to claim 2, wherein said first and second power supply terminals are connected to a common power supply. 4. The power supply device according to claim 3, further comprising a suppression component disposed between said second power supply terminal and said common power supply and for suppressing propagation of noise generated in said high-speed circuit block. Semiconductor integrated circuit.