JP2002164508A - Protective circuit of pad - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain deterioration of high frequency characteristic by reducing wiring length from a pad to an amplifying circuit. SOLUTION: Diodes 3, 4 which are used for making an excess signal generated on the pad 2 by static electricity or the like flow into a power source Vcc are connected with not a metal wiring 6 between the pad 2 and the amplifying circuit 7 but the pad 2 itself. Consequently, it is made unnecessary that the metal wiring 6 between the pad 2 and the amplifying circuit 7 is made long to connect the diodes 3, 4, and wiring length between the pad 2 and the amplifying circuit 7 can be reduced, so that influence of noise or the like on a high frequency signal flowing on a wiring is restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pad protection circuit, and more particularly, to a pad protection circuit suitable for use in a circuit for protecting a data input / output pad provided on a semiconductor chip from static electricity or the like.

[0002]

2. Description of the Related Art FIG. 4 schematically shows a chip layout of a general semiconductor integrated circuit. In FIG. 4, reference numeral 101 denotes an IC chip, and a plurality of data input / output pads 102 are arranged around the IC chip. These pads 102
Are electrically connected to a lead frame or a printed circuit board (not shown) by bonding wires 103. Inside of pad 102, ie, IC chip 1
01 is a core unit 104 on which a logic circuit is mounted.
Exists.

Normally, ICs are generated by static electricity or noise externally applied through pads 102 for data input / output.
A protection circuit is provided for the pad 102 so that the chip 101 is not destroyed. FIG. 5 is a diagram showing a configuration of a conventional pad protection circuit. In FIG. 5, the amplification circuit 1
Reference numeral 11 denotes an amplifier for amplifying a signal input / output to / from the core unit 104 via the pad 102, and is provided on the outermost periphery of the core unit 104. A pad protection circuit is provided between the amplifier circuit 111 and the pad 102.

That is, the pad protection circuit includes the pad 10
The two diodes 113 and 114 are connected in the same direction from the ground to the power supply Vcc via the metal wiring 112 extending from the metal wiring 112, and between the metal wiring 112 extending from the pad 102 and the metal wiring 116 extending from the amplifier circuit 111. Is connected to a resistor 115. With such a configuration, an excessive signal generated by static electricity or noise is supplied to the power supply Vcc by the diodes 113 and 114, and an excessive current is prevented from flowing into the core unit 104 through the amplifier circuit 111.

[0005]

However, in the above-described conventional technique, since a pad protection circuit including diodes 113 and 114 is provided between the pad 102 and the amplifier circuit 111, the wiring between the pad 102 and the amplifier circuit 111 is not provided. The distance will be long. Therefore, especially the IC chip 10
In the case where 1 is equipped with a high-frequency circuit, there is a problem that high-frequency signals to be input and output are affected by noise and the like on long wirings, and high-frequency characteristics are deteriorated.

The present invention has been made to solve such a problem, and an object of the present invention is to reduce the wiring length from a pad to an amplifier circuit so that deterioration of high frequency characteristics can be suppressed. .

[0007]

SUMMARY OF THE INVENTION A pad protection circuit according to the present invention is a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted. A protection circuit provided, wherein the protection circuit includes a semiconductor element for flowing a generated excess signal to ground or a power supply, and the semiconductor element is connected to the pad.

Another aspect of the present invention is a protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted. A resistor connected between the pad and an amplifier circuit for amplifying a signal input / output via the pad, and a resistor connected to the pad, for flowing an excessive signal generated to ground or a power supply. A semiconductor element.

According to another aspect of the present invention, the semiconductor element comprises two diodes, and at least one of the two diodes is arranged in an empty space generated between an adjacent pad and its protection circuit. I do.

Another aspect of the present invention is a protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted. The protection circuit includes a semiconductor element for flowing the generated excess signal to the ground or a power supply, and the semiconductor element is connected to a wiring provided outside the pad.

Another aspect of the present invention is a protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted. A resistor connected between the pad and an amplifier circuit for amplifying a signal input / output via the pad, and a wiring connected outside of the pad to connect an excess signal generated to a ground or a power supply. And a semiconductor element for pouring into the device.

Since the present invention comprises the above technical means, it is not necessary to lengthen the wiring between the pad and the amplifier circuit to connect the semiconductor element of the pad protection circuit, and the wiring length between the pad and the amplifier circuit is eliminated. Can be shortened.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of a pad protection circuit according to the first embodiment. In FIG.
Reference numeral 1 denotes an IC chip, and a plurality of data input / output pads 2 are arranged around the IC chip.

In FIG. 1, one pad 2 is representatively represented.
Only a plurality of pads 2 are arranged in the same manner as in the chip layout of FIG. 4, and are electrically connected to a lead frame or a printed circuit board by bonding wires.

Inside the pad 2, that is, in the center of the IC chip 1, there is a core unit 8 on which a logic circuit is mounted. An amplifier circuit 7 for amplifying a signal input / output to / from the core unit 8 via the pad 2 is provided on the outermost periphery of the core unit 8.

Also in the present embodiment, a protection circuit is provided for the pad 2 in order to prevent the IC chip 1 from being damaged by static electricity or noise externally applied through the pad 2. This pad protection circuit includes two diodes 3 and 4 and a resistor 5.

In this embodiment, the resistance 5 is
As in the conventional case, the connection is made between the metal wiring 6 extending from the pad 2 and the metal wiring 9 extending from the amplifier circuit 7. On the other hand, the two diodes 3 and 4 are connected not to the metal wiring 6 but to the pad 2 itself.

That is, the first diode 3 is connected between the ground and the pad 2, and the second diode 4 is connected between the pad 2 and the power supply Vcc. At this time, these two diodes 3 and 4 are connected in series via the pad 2 such that the forward direction is directed from the ground to the power supply Vcc.

With this configuration, even if an excessive signal is generated on the pad 2 due to static electricity or noise, it is supplied to the power supply Vcc via the diodes 3 and 4. As a result, it is possible to prevent an unnecessarily large current from flowing into the logic circuit in the core unit 8 through the amplification circuit 7.

In this embodiment, the two diodes 3 and 4 are connected to the metal wiring 6 between the pad 2 and the amplifier circuit 7.
Instead, the connection is made to the pad 2 itself, so that it is not necessary to lengthen the metal wiring 6 to connect the diodes 3 and 4, and the wiring length between the pad 2 and the amplifier circuit 7 can be shortened. As a result, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art.

In addition, the distance from the chip edge to the core portion edge in the pad region (the region other than the core portion 8) including the protection circuit is shortened to the extent that the wiring length between the pad 2 and the amplifier circuit 7 can be reduced. Accordingly, the area of the core portion 8 can be increased accordingly. Thereby, IC
There is also an advantage that more circuit elements constituting a logic circuit important for the chip 1 can be integrated in the core unit 8.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram illustrating a configuration example of a pad protection circuit according to the second embodiment. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

In FIG. 2, reference numeral 10 denotes an IC chip,
A plurality of data input / output pads 2 are arranged in the peripheral portion. Although only one pad 2 is shown as a representative in FIG. 2, a plurality of pads 2 are actually arranged similarly to the chip layout of FIG. Connected.

The inside of the pad 2, that is, the IC chip 10
A core unit 8 on which a logic circuit is mounted is present at the center of the block. An amplifier circuit 7 for amplifying a signal input / output to / from the core unit 8 via the pad 2 is provided on the outermost periphery of the core unit 8. Between the pad 2 and the amplifier circuit 7, as in the first embodiment, metal wires 6, 9, 9
And the resistor 5.

In this embodiment, the metal wiring 11 is provided on the side opposite to the pad 2 with respect to the metal wiring 6, that is, outside the pad 2. The two diodes 3 and 4 are connected to the metal wiring 11.

That is, the first diode 3 is connected between the ground and the metal wiring 11, and the second diode 4 is connected between the metal wiring 11 and the power supply Vcc. At this time, these two diodes 3 and 4 are connected in series via the metal wiring 11 such that the forward direction is directed from the ground to the power supply Vcc.

With such a configuration, even if an excessive signal is generated on the pad 2 due to static electricity or noise, it flows into the power supply Vcc via the diodes 3 and 4. As a result, it is possible to prevent an unnecessarily large current from flowing into the logic circuit in the core unit 8 through the amplification circuit 7.

In this embodiment, the two diodes 3 and 4 are connected to the metal wiring 6 between the pad 2 and the amplifier circuit 7.
However, since the connection is made outside the pad 2, it is not necessary to lengthen the metal wiring 6 to connect the diodes 3 and 4, and the wiring length between the pad 2 and the amplifier circuit 7 can be shortened. it can. As a result, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art.

Further, in the above-described first embodiment, since the diodes 3 and 4 are connected to both sides of the pad 2,
The spacing between adjacent pads 2 is wider than in the prior art. On the other hand, according to the second embodiment, since the diodes 3 and 4 are connected to both sides of the metal wiring 11 having a width smaller than that of the pad 2, the interval between the adjacent pads 2 is substantially the same as that of the related art. Can be suppressed.

In this embodiment, the bonding wire is connected to the pad 2, but may be connected to the metal wiring 11.

Next, a third embodiment of the present invention will be described. FIG. 3 is a diagram illustrating a configuration example of a pad protection circuit according to the third embodiment. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

In the pad protection circuit of the third embodiment, two diodes 3 and 4 are connected to the pad 2 itself, as in the first embodiment described above. It is ingenious.

That is, in the first embodiment, the two diodes 3 and 4 are both arranged right beside the pad 2.
On the other hand, in the third embodiment, as shown in FIG. 3, the first diode 3 connected to one pad 2 and the other pad 2 And the second diode 4 connected to the vertical line are arranged in the vertical direction.

That is, when the plurality of pads 2 are arranged side by side with the protection circuits in the horizontal direction, some space is generated between adjacent protection circuits. In this embodiment, at least one of the two diodes 3 and 4 (the first diode 3 in the case of FIG. 3) is arranged by utilizing this space.

With this arrangement, the vertical distance from the chip edge to the core edge in the pad area is reduced while the horizontal distance, which is the distance between adjacent pads 2, is suppressed to the same level as in the related art. be able to. Therefore, the area of the core unit 8 can be increased without increasing the chip size, and more circuit elements can be integrated in the core unit 8.

It should be noted that each of the embodiments described above is merely an example of a concrete example for carrying out the present invention, and the technical scope of the present invention is interpreted in a limited manner. It must not be. That is, the present invention can be embodied in various forms without departing from the spirit or main features thereof. For example, in the above embodiment, the excess signal generated on the pad 2 is
Although it is designed to flow into the cc, it may be flown into the ground.

[0037]

As described above, according to the present invention, it is not necessary to lengthen the wiring between the pad and the amplifier circuit for connecting the semiconductor element of the pad protection circuit. The wiring length between them can be shortened. Therefore, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a pad protection circuit according to a first embodiment.

FIG. 2 is a diagram illustrating a configuration example of a pad protection circuit according to a second embodiment;

FIG. 3 is a diagram illustrating a configuration example of a pad protection circuit according to a third embodiment;

FIG. 4 is a diagram schematically showing a chip layout of a general semiconductor integrated circuit.

FIG. 5 is a diagram showing a configuration of a conventional pad protection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IC chip 2 Pad 3, 4 Diode 5 Resistance 6 Metal wiring 7 Amplification circuit 8 Core part 9 Metal wiring 10 IC chip 11 Metal wiring 20 IC chip

Claims (5)

[Claims] 1. A protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, wherein the protection circuit includes: A pad protection circuit including a semiconductor element for flowing generated excessive signals to ground or a power supply, wherein the semiconductor element is connected to the pad. 2. A protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, wherein the pad and the pad A resistor connected between the amplifier and an amplifier circuit for amplifying a signal input / output via the input / output terminal; and a semiconductor element connected to the pad and for flowing the generated excess signal to ground or a power supply. A pad protection circuit, characterized in that: 3. The semiconductor device according to claim 1, wherein the semiconductor element comprises two diodes, and at least one of the two diodes is arranged in an empty space formed between an adjacent pad and its protection circuit. 4. A pad protection circuit according to claim 1. 4. A protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, wherein the protection circuit comprises: A pad protection circuit including a semiconductor element for flowing generated excessive signals to ground or a power supply, wherein the semiconductor element is connected to a wiring provided outside the pad. 5. A protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, wherein the pad and the pad A resistor connected between an amplifier circuit for amplifying a signal input and output through the pad, and a semiconductor element connected to a wiring provided outside the pad for flowing an excessive signal generated to ground or a power supply A pad protection circuit, comprising: