JPH0832200A - Electronic circuit board and printed wiring board - Google Patents

Electronic circuit board and printed wiring board

Info

Publication number
JPH0832200A
JPH0832200A JP6161104A JP16110494A JPH0832200A JP H0832200 A JPH0832200 A JP H0832200A JP 6161104 A JP6161104 A JP 6161104A JP 16110494 A JP16110494 A JP 16110494A JP H0832200 A JPH0832200 A JP H0832200A
Authority
JP
Japan
Prior art keywords
capacitor
signal line
line
board according
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6161104A
Other languages
Japanese (ja)
Other versions
JP3554028B2 (en
Inventor
Toru Otaki
徹 大滝
Tomoyasu Arakawa
智安 荒川
Yasushi Takeuchi
靖 竹内
Hideho Inagawa
秀穂 稲川
Toru Aisaka
徹 逢坂
Yoshimi Terayama
芳実 寺山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP16110494A priority Critical patent/JP3554028B2/en
Publication of JPH0832200A publication Critical patent/JPH0832200A/en
Application granted granted Critical
Publication of JP3554028B2 publication Critical patent/JP3554028B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Abstract

PURPOSE:To take the shortest course for a high frequency current to flow for the transition period of a digital signal from Low condition to High condition by mounting capacitor parts on both the section between a signal line and a power source and the section between the signal line and GND, in the vicinity of an IC terminal outputting the digital signal. CONSTITUTION:IC1 and IC 10 are mounted by soldering on the land parts having conductive layers provided on a printed wiring board, and the output signal pin 3 of IC 1, to a signal line 7, and a power source pin 2, to a power source pin 5, and a GND pin 4, to a GND line 6, are electrically connected, respectively. A capacitor 9 is inserted between the signal line 7 and the GND line 5, and also a capacitor 8 is inserted between the signal line 7 and the power source line 5. Accordingly, the loop of the flow of the high frequency currents of very high frequency components which are produced when the digital signal changes from Low to High become the shortest, and the radiation in normal mode and also the power stabilize, and the radiation in common mode is suppressed, too.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電気回路板及びプリント
配線板に関し、更に詳しくはデジタル回路に好適に使用
し得る電気回路板及び該電気回路板に使用し得るプリン
ト配線板に回する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric circuit board and a printed wiring board, and more particularly to an electric circuit board suitable for digital circuits and a printed wiring board usable for the electric circuit board.

【0002】[0002]

【従来の技術】従来より信号線が不要な信号輻射を受け
る結果、ノイズを拾ってしまい誤動作等が発生するとい
う問題があった。このため従来より不要輻射を小さくす
る対策として、信号線に抵抗やフェライトビーズを挿入
したり、信号線とグランド(GND)線との間にコンデ
ンサを挿入することが行なわれている。信号線とGND
間にコンデンサを挿入する場合は抵抗およびインダクタ
ンスと組み合わせローパスフィルタを形成するのが一般
的である。
2. Description of the Related Art Conventionally, there has been a problem that noise is picked up and malfunction occurs as a result of receiving unnecessary signal radiation from a signal line. Therefore, conventionally, as a measure for reducing unnecessary radiation, a resistor or a ferrite bead is inserted in the signal line, or a capacitor is inserted between the signal line and the ground (GND) line. Signal line and GND
When inserting a capacitor between them, it is general to form a low-pass filter in combination with a resistor and an inductance.

【0003】特に、このような不要輻射対策は100M
H以上の高周波成分が発生する回路において重要であ
り、近年のデジタル回路の発展は不要輻射対策の重要性
を再認識させている。
In particular, such an unnecessary radiation countermeasure is 100M.
This is important in circuits that generate high-frequency components of H or higher, and the recent development of digital circuits has made us re-recognize the importance of measures against unnecessary radiation.

【0004】従来の不要輻射対策の一例を図面を用いて
説明する。
An example of conventional measures against unwanted radiation will be described with reference to the drawings.

【0005】図6は従来の電気回路板に配置された各電
気部品の配置の一例を説明するための模式的配置図であ
る。
FIG. 6 is a schematic layout diagram for explaining an example of the layout of each electric component arranged on a conventional electric circuit board.

【0006】図6において、1はクワッド フラット
パッケージタイプ(Quad Flat Packag
e;QFPタイプ)のデジタルIC(集積回路素子)、
3は出力信号ピン、4はGNDピン、6はGND線、7
は信号線、9はコンデンサ、10はスモール アウトラ
イン パッケージタイプ(Small Outline
Package;SOPタイプ)のIC、11はIC
10の入力信号ピン、である。
In FIG. 6, 1 is a quad flat
Package type (Quad Flat Pack
e; QFP type) digital IC (integrated circuit element),
3 is an output signal pin, 4 is a GND pin, 6 is a GND line, 7
Is a signal line, 9 is a capacitor, and 10 is a small outline package type (Small Outline).
Package; SOP type IC, 11 is IC
10 input signal pins.

【0007】図6に示されるように、信号線7とGND
線6とはIC1の端子側でコンデンサ9を介して接続さ
れている。
As shown in FIG. 6, the signal line 7 and the GND
The line 6 is connected to the terminal side of the IC 1 via a capacitor 9.

【0008】このようなコンデンサ9の挿入によって、
周波数の非常に高い領域においてコンデンサ9を通るル
ープを形成することで不要輻射対策が行なわれている。
By inserting the capacitor 9 as described above,
A countermeasure against unwanted radiation is taken by forming a loop through the capacitor 9 in a very high frequency region.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、図6に
示されるような信号線7とGND線6との間にのみコン
デンサ9を挿入するだけでは、信号レベルがハイ(Hi
gh)からロー(Low)に変化する場合は問題がない
が、信号レベルがLowからHighに変化する場合は
充分な対策とはいえない場合がある。
However, if the capacitor 9 is inserted only between the signal line 7 and the GND line 6 as shown in FIG. 6, the signal level becomes high (Hi.
When gh) changes to low, there is no problem, but when the signal level changes from low to high, it may not be a sufficient countermeasure.

【0010】図7は図6に示される電気回路板の回路の
一部を示す概略的回路図である。この図を用いて上記理
由を説明する。
FIG. 7 is a schematic circuit diagram showing a part of the circuit of the electric circuit board shown in FIG. The above reason will be described with reference to this drawing.

【0011】図7において、22はIC1中のバッフ
ァ、26はIC10中のバッファ、27はIC1のバイ
パスコンデンサ、28,29,30,31は夫々電源線
パターンのインダクタンス、32はIC10のバイパス
コンデンサである。尚、図中において図6と同じ番号の
ものは図6と同じものを指している。
In FIG. 7, 22 is a buffer in IC1, 26 is a buffer in IC10, 27 is a bypass capacitor of IC1, 28, 29, 30 and 31 are inductances of power supply line patterns, and 32 is a bypass capacitor of IC10. is there. In the figure, the same numbers as those in FIG. 6 indicate the same items as those in FIG.

【0012】周波数の非常に高い領域において不要輻射
対策を行なう場合、対策する高周波電流の流れる経路を
短くし、高周波電流がつくるループ面積を小さくするこ
とは重要である。
When taking countermeasures against unwanted radiation in a very high frequency region, it is important to shorten the path through which the high-frequency current flows and to reduce the loop area formed by the high-frequency current.

【0013】そこで、図6及び図7に示されるように信
号線7とGND線6との間にコンデンサ9を介装するこ
とにより、高周波がつくるループ面積を小さくしようと
していた。
Therefore, as shown in FIG. 6 and FIG. 7, the capacitor 9 is interposed between the signal line 7 and the GND line 6 to reduce the loop area formed by the high frequency.

【0014】しかしながら、信号レベルがHigh→L
owの場合は図中25の矢印に示されるような短い経路
のループが形成されるものの、Low→Highの場合
は図中34の矢印に示されるような長い経路のループが
形成される。
However, the signal level changes from High to L
In the case of ow, a loop of a short route as shown by the arrow 25 in the drawing is formed, but in the case of Low → High, a loop of a long route as shown by the arrow 34 in the drawing is formed.

【0015】つまり、図に示されるような不要輻射対策
の場合、HighからLowへの過渡期は充分な効果が
出ても、LowからHighへの過渡期の場合は充分な
対策とはならない場合があった。
That is, in the case of the countermeasure against unnecessary radiation as shown in the figure, when the transition period from High to Low has a sufficient effect, but in the transition period from Low to High, the countermeasure is not sufficient. was there.

【0016】このように、高周波電流の流れる経路が長
くなると、直接的にノーマルモードの放射が大きくなる
ばかりか、ICの電源,グランド系が不安定となり、結
果としてコモンモードの放射も増加し、不要輻射対策の
効果が小さくなる場合があった。
As described above, when the path through which the high-frequency current flows becomes long, not only the normal mode radiation becomes large directly, but also the power supply and the ground system of the IC become unstable, and as a result, the common mode radiation also increases. In some cases, the effect of measures against unwanted radiation was diminished.

【0017】尚、ノーマルモードの放射は信号線とグラ
ンドからなるループに流れる電流から生じる放射であ
り、コモンモード放射はコモンモード電位(多くの場合
グランド電位)によりケーブル等をアンテナとして放射
される放射のことである。
The normal mode radiation is the radiation generated from the current flowing in the loop composed of the signal line and the ground, and the common mode radiation is the radiation radiated by the common mode potential (in many cases, the ground potential) using the cable or the like as the antenna. That is.

【0018】本発明は電気回路、特にデジタル信号を取
扱う電気回路で問題となる不要輻射の問題が生じないか
実質的に生じない電気回路板及び該電気回路板に使用し
得るプリント配線板を提供することを目的とする。
The present invention provides an electric circuit board which does not or does not substantially cause the problem of unnecessary radiation which is a problem in an electric circuit, particularly an electric circuit which handles digital signals, and a printed wiring board which can be used for the electric circuit board. The purpose is to do.

【0019】また本発明は特に周波数の高い領域におい
て高い不要輻射対策の効果を有する電気回路板及び該電
気回路板に使用し得るプリント配線板を提供することを
目的とする。
Another object of the present invention is to provide an electric circuit board having a high effect of preventing unwanted radiation especially in a high frequency region and a printed wiring board which can be used for the electric circuit board.

【0020】更に本発明は、より広い周波数帯域におい
て高い不要輻射対策を行なうことが可能な電気回路板及
び該電気回路板に使用し得るプリント配線板を提供する
ことを目的とする。
A further object of the present invention is to provide an electric circuit board capable of taking high measures against unwanted radiation in a wider frequency band, and a printed wiring board that can be used for the electric circuit board.

【0021】加えて本発明は、信号線のLowからHi
ghへの過渡期及びHighからLowへの過渡期のい
ずれにおいても効果的に不要輻射対策を行なうことが可
能な電気回路板及び該電気回路板に使用し得るプリント
配線板を提供することを目的とする。
In addition, according to the present invention, the signal line is changed from Low to Hi.
An object of the present invention is to provide an electric circuit board and a printed wiring board that can be used for the electric circuit board, which can effectively take measures against unwanted radiation in both the transition period to gh and the transition period from High to Low. And

【0022】[0022]

【課題を解決するための手段】上記目的を達成する本発
明の電気回路板は、基板上に配された複数の端子を有す
る集積回路素子と、該集積回路素子の前記端子近傍にお
いて、前記端子と接続される信号線と電源線及び信号線
とグランド線との間にコンデンサを有することを特徴と
する。
An electric circuit board according to the present invention which achieves the above object comprises an integrated circuit element having a plurality of terminals arranged on a substrate, and the terminal in the vicinity of the terminal of the integrated circuit element. A capacitor is provided between the signal line and the power supply line connected to and the signal line and the ground line.

【0023】また、上記目的を達成する本発明のプリン
ト配線板は、基体と、該基体上の集積回路素子が配され
る位置に、前記集積回路素子の複数の端子に対応して設
けられたランド部と該ランド部に接続された配線とを有
するプリント配線板において、前記ランド部近傍で前記
配線の1つと該配線とは異なる2つの配線との間に夫々
コンデンサを有することを特徴とする。
Further, the printed wiring board of the present invention which achieves the above object is provided at a base and a position on the base where an integrated circuit element is arranged, corresponding to a plurality of terminals of the integrated circuit element. In a printed wiring board having a land portion and a wiring connected to the land portion, a capacitor is provided between one of the wirings and two wirings different from the wiring in the vicinity of the land portion. .

【0024】[0024]

【作用】上記した構成とすることによって、信号レベル
がHighからLowに変化する場合も、またLowか
らHighに変化する場合も各コンデンサによって不要
輻射の要因となる高周波電流のループをより小さい面積
(高周波電流の流れる経路をより短く)にできるため、
充分な不要輻射対策を行なうことができる。
With the above-mentioned configuration, the high-frequency current loop that causes unnecessary radiation is reduced by each capacitor when the signal level changes from High to Low and from Low to High. Since the path through which high-frequency current flows can be made shorter,
It is possible to take sufficient measures against unnecessary radiation.

【0025】また、信号線を更に電源線とグランド線を
隣接させてブロックすることによって、より一層の不要
輻射対策を行なうことができる。
Further, by blocking the signal line with the power supply line and the ground line adjacent to each other, it is possible to further prevent unwanted radiation.

【0026】[0026]

【実施例】以下、図面を用いて本発明を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

【0027】<実施例1>図1は本発明の第1の実施例
を説明するための電気回路板の各部品の模式的配置を説
明する模式図(以下「模式的配置図」)である。
<Embodiment 1> FIG. 1 is a schematic view (hereinafter, referred to as “schematic layout drawing”) illustrating a schematic layout of each component of an electric circuit board for explaining a first embodiment of the present invention. .

【0028】本実施例においては、信号線7とGND線
6との間にコンデンサ9が別部品として実装、挿入され
ているだけでなく、信号線7と電源線5との間に更に別
部品としてコンデンサ8が実装、挿入されている。
In the present embodiment, not only is the capacitor 9 mounted and inserted as a separate component between the signal line 7 and the GND line 6, but also another component is provided between the signal line 7 and the power supply line 5. A capacitor 8 is mounted and inserted as.

【0029】IC1及びIC10は夫々プリント配線板
上に形成された導電層を有するランド部に半田付けによ
って実装されている。
The ICs 1 and 10 are mounted by soldering on lands having a conductive layer formed on the printed wiring board.

【0030】従って、IC1の出力信号ピン3は信号線
7と、電源ピン2は電源線5と、GNDピン4はGND
線6と夫々電気的に接続されている。
Therefore, the output signal pin 3 of the IC 1 is the signal line 7, the power supply pin 2 is the power supply line 5, and the GND pin 4 is GND.
The lines 6 are electrically connected to each other.

【0031】なお、図1において、IC1は図6と同様
に4方向にリードピンがでているQFPタイプのデジタ
ルICで、たとえばCMOSのデジタルICなどであ
る。また、IC10も図6と同様に2方向にリードピン
がでているSOPタイプのデジタルICの例で示してあ
る。
In FIG. 1, IC1 is a QFP type digital IC having lead pins extending in four directions as in FIG. 6, and is, for example, a CMOS digital IC. Similarly to FIG. 6, the IC 10 is also shown as an example of a SOP type digital IC having lead pins extending in two directions.

【0032】図2に、図1の電気回路板の回路の一部を
示す概略的回路図を示す。
FIG. 2 is a schematic circuit diagram showing a part of the circuit of the electric circuit board shown in FIG.

【0033】本実施例においては、信号線7と電源線5
との間にコンデンサ8を挿入してあるので、特にデジタ
ル信号がLowからHighに変化する時に発生する非
常に高い周波数成分の高周波電流は図中33で示した矢
印の経路で流れるためループが最短になり、ノーマルモ
ードの放射はもちろん、電源も安定化するためコモンモ
ードの放射もおさえることができる。
In this embodiment, the signal line 7 and the power line 5
Since the capacitor 8 is inserted between and, the high frequency current of a very high frequency component generated especially when the digital signal changes from Low to High flows in the route indicated by the arrow 33 in the figure, so that the loop is shortest. Therefore, not only the normal mode radiation but also the common mode radiation can be suppressed because the power supply is stabilized.

【0034】もちろん、HighからLowへ変化する
ときには図中25の経路で高周波電流は流れるのでやは
りループは最短になり不要な輻射をおさえることができ
る。
Of course, when changing from High to Low, a high frequency current flows through the path 25 in the figure, so that the loop is also shortest and unnecessary radiation can be suppressed.

【0035】又、コンデンサ8及び9は、できる限りI
Cの各ピンと信号線7、電源線5、GND線6との接続
部の近くに配されることが望ましい。これは、図1及び
図2からも理解されるように、コンデンサ8及び9がI
C1のピンと離れる程、形成される電流の流れる経路が
長くなり、ループの面積が大きくなって放射を抑えるこ
とが難しくなるためである。
The capacitors 8 and 9 are connected to the capacitor I as much as possible.
It is desirable to be arranged near the connection portion between each pin of C and the signal line 7, power supply line 5, and GND line 6. This is because the capacitors 8 and 9 are I.sub.2, as can be seen from FIGS.
This is because as the distance from the pin of C1 increases, the path through which the current is formed becomes longer, the area of the loop increases, and it becomes difficult to suppress radiation.

【0036】また、コンデンサ8と9の容量を等しい容
量にすることには必ずしも必要ない。集積回路素子の特
性に応じてコンデンサの容量を変えることは好ましいこ
とである。
Further, it is not always necessary to make the capacitors 8 and 9 have the same capacitance. It is preferable to change the capacitance of the capacitor according to the characteristics of the integrated circuit device.

【0037】たとえば、信号を出力する集積回路素子の
立上り、立下り時間の特性を比較し、立上り時間が立下
り時間より速い場合は信号線と電源線との間に接続する
コンデンサ(コンデンサ8)の容量を大きくし、信号の
立下り時間が速い場合は信号線とグランド線との間に接
続するコンデンサ(コンデンサ9)の容量を大きくする
ことが望ましい。
For example, the characteristics of rise and fall times of integrated circuit elements that output signals are compared. If the rise time is faster than the fall time, a capacitor (capacitor 8) connected between the signal line and the power supply line. It is desirable to increase the capacitance of the capacitor and increase the capacitance of the capacitor (capacitor 9) connected between the signal line and the ground line when the signal fall time is fast.

【0038】コンデンサ8と9の容量は、好ましくは1
0pF以上、100pF以下、より好ましくは15pF
以上、80pF以下、さらに好ましくは20pF以上、
60pF以下とするのが望ましい。
The capacitance of capacitors 8 and 9 is preferably 1
0 pF or more and 100 pF or less, more preferably 15 pF
Or more, 80 pF or less, more preferably 20 pF or more,
It is preferably 60 pF or less.

【0039】もちろん、これらの値は不要輻射対策を行
ないたい目的の周波数に応じて適宜選択されるのが好ま
しい。
Of course, it is preferable that these values are appropriately selected according to the target frequency for which unwanted radiation countermeasures are desired.

【0040】<実施例2>図3に本発明の第2の実施例
の電気回路板の各部品の模式的配置図を示す。
<Embodiment 2> FIG. 3 shows a schematic layout of each component of an electric circuit board according to a second embodiment of the present invention.

【0041】本実施例では実施例1で説明した2つのコ
ンデンサ8,9に加えてIC1の信号ピン3とコンデン
サ8及び9との間に抵抗12を挿入してある。尚、抵抗
12はインダクタンス成分を有するものを代わりに介挿
しても良い。
In this embodiment, in addition to the two capacitors 8 and 9 described in the first embodiment, a resistor 12 is inserted between the signal pin 3 of the IC 1 and the capacitors 8 and 9. Note that the resistor 12 may have a component having an inductance component instead.

【0042】本実施例によれば、実施例1の場合に較べ
てより低い周波数帯域において不要輻射の問題を低減す
ることができた。
According to this embodiment, the problem of unwanted radiation can be reduced in the lower frequency band as compared with the case of the first embodiment.

【0043】尚、コンデンサの容量や抵抗の大きさを適
宜選択することが好ましい。一般には、容量もしくは抵
抗が小さい程高く周波数側に、大きい程低い周波数側に
効果がある。ただし、必要以上に容量もしくは抵抗を大
きくすると信号波形がなまるので注意が必要である。
It should be noted that it is preferable to appropriately select the capacitance and resistance of the capacitor. Generally, the smaller the capacitance or resistance, the higher the frequency side, and the larger the capacitance, the lower the frequency side. However, note that if the capacitance or resistance is increased more than necessary, the signal waveform becomes blunt.

【0044】<実施例3>図4に本発明の第3の実施例
の電気回路板の各部品の模式的配置図を示す。
<Embodiment 3> FIG. 4 shows a schematic layout of each part of an electric circuit board according to a third embodiment of the present invention.

【0045】本実施例では実施例2と同様に2つのコン
デンサと1つの抵抗を不要輻射対策のために有するに加
えて、信号線7の一方の側に電源線5を他方の側にGN
D線6を信号線7に近接して沿って配してある。
In this embodiment, in addition to having two capacitors and one resistor as a countermeasure against unnecessary radiation as in the second embodiment, the power supply line 5 is provided on one side of the signal line 7 and the GN is provided on the other side.
The D line 6 is arranged along and close to the signal line 7.

【0046】コンデンサ8は電源線5と信号線7の間
に、コンデンサ9は信号線7とGND線6の間に、そし
て信号線7の途中には抵抗12を夫々挿入している。
A capacitor 8 is inserted between the power supply line 5 and the signal line 7, a capacitor 9 is inserted between the signal line 7 and the GND line 6, and a resistor 12 is inserted in the middle of the signal line 7.

【0047】もちろん、本実施例の場合も抵抗12はイ
ンダクタンス成分を有するものを用いて良い。
Of course, also in this embodiment, the resistor 12 may have an inductance component.

【0048】GND線6と電源線5は夫々信号線7に近
接して配されガードした構造とされている。電源線5は
IC10の下を通ってIC10の電源ピン17に接続さ
れている。またGND線6はIC10の下を通ってIC
10のGNDピン18に接続される。もちろん実施例1
及び2においても各線の接続先は同じである。
The GND line 6 and the power supply line 5 are arranged close to the signal line 7, respectively, and have a guarded structure. The power supply line 5 passes under the IC 10 and is connected to the power supply pin 17 of the IC 10. Also, the GND line 6 passes under the IC 10 and the IC
10 to GND pin 18. Of course, Example 1
Also in 2 and 2, the connection destination of each line is the same.

【0049】IC10側で電源線5及びGND線6がI
C10のパッケージの下側を通って各ピンに接続された
例を示してあるが、これは、信号線7のガードを信号線
7と信号ピン11との接続部分まで行なうためである。
The power supply line 5 and the GND line 6 are I on the IC 10 side.
An example is shown in which each pin is connected through the lower side of the package of C10, but this is to protect the signal line 7 up to the connection between the signal line 7 and the signal pin 11.

【0050】従って、IC10の各ピンの位置などによ
って、この配線の引き廻しは適宜変更できる。
Therefore, the routing of this wiring can be appropriately changed depending on the position of each pin of the IC 10.

【0051】本実施例によれば実施例1に較べてより低
い周波数から高い周波数まで不要輻射に対して効果があ
った。
According to the present embodiment, compared with the first embodiment, there is an effect against unwanted radiation from a lower frequency to a higher frequency.

【0052】又、本実施例は信号線7を電源線5及びG
ND線6でガードしているばかりでなく、コンデンサ8
及び9と抵抗12の配置の仕方から実施例2に較べても
より不要輻射に対する効果が高い。
In this embodiment, the signal line 7 is connected to the power supply lines 5 and G.
Not only guarding with ND line 6, but also capacitor 8
9 and the resistor 12 are arranged, the effect of unwanted radiation is higher than that of the second embodiment.

【0053】つまり、電源5及びGND線6による信号
線7のガードは各配線間に容量が形成され、これが不要
輻射に対して効果をあげる。
That is, in the guard of the signal line 7 by the power source 5 and the GND line 6, a capacitance is formed between the wirings, which is effective against unnecessary radiation.

【0054】また、コンデンサ8及び9が実施例2に較
べてIC1側に近づいて配されているので(実施例2で
は抵抗12の分だけ離れてコンデンサ8及び9が配され
ている)、先述したようによりループが小さくなり不要
輻射に対する一層の効果がある。
Since the capacitors 8 and 9 are arranged closer to the IC1 side than in the second embodiment (in the second embodiment, the capacitors 8 and 9 are arranged apart from the resistor 12 by the resistor 12). As a result, the loop becomes smaller, which is more effective against unwanted radiation.

【0055】<実施例4>図5に本発明の第4の実施例
の電気回路板の各部品の模式的配置図を示す。
<Embodiment 4> FIG. 5 shows a schematic layout of each part of an electric circuit board according to a fourth embodiment of the present invention.

【0056】本実施例では上記各実施例と異なり、コン
デンサ8及び9を別部品として実装しておらず、プリン
ト配線板に作り込んでいる。
In the present embodiment, unlike the above-mentioned embodiments, the capacitors 8 and 9 are not mounted as separate parts but are built in the printed wiring board.

【0057】つまり、導電層を櫛形パターン状とし、各
突出した部分同士が接触しないように対向させて組み合
わせ、すなわち、一方の配線の導電層の突部の間と他方
の配線の突部が位置するように配され容量を形成する。
That is, the conductive layers are formed in a comb pattern and are combined so as to face each other so that the protruding portions do not come into contact with each other, that is, between the protruding portions of the conductive layer of one wiring and the protruding portions of the other wiring are positioned. To form a capacitor.

【0058】図5で説明すれば信号線7のIC1側にお
いて信号線7に交わるように枝部(突部)7aを形成
し、該枝部7aの間に電源線5から延びた枝部(突部)
5a又はGND線6から延びた枝部(突部)6aが位置
するように導電層が形成されている。
Referring to FIG. 5, branch portions (protrusions) 7a are formed on the IC1 side of the signal line 7 so as to intersect with the signal line 7, and a branch portion (projection) extending from the power supply line 5 between the branch portions 7a ( Projection)
The conductive layer is formed so that the branch portion (projection) 6a extending from 5a or the GND line 6 is located.

【0059】尚、本実施例においても、信号線7を電源
線5及びGND線6がガードしているのは実施例3と同
様である。
In this embodiment as well, the signal line 7 is guarded by the power supply line 5 and the GND line 6 as in the third embodiment.

【0060】本実施例においては、容量がプリント配線
板に形成されているのでコンデンサをあらためて実装部
品として実装する必要がなく、実装コストや半田付不良
を生じず信頼性が向上する。
In this embodiment, since the capacitance is formed on the printed wiring board, it is not necessary to mount the capacitor as a mounting component anew, and the mounting cost and soldering failure do not occur, and the reliability is improved.

【0061】また、コンデンサはICの各ピンのより近
傍に形成可能なためより一層小さいループとすることが
容易である。
Since the capacitor can be formed closer to each pin of the IC, it is easy to form a smaller loop.

【0062】尚、本実施例で例示したコンデンサは図に
示されるような位置に限定されるものではなく、一部が
IC1のパッケージの下側になるようにしても良い。
The capacitor exemplified in the present embodiment is not limited to the position shown in the figure, and a part may be under the package of IC1.

【0063】コンデンサは、図示される形態以外に変形
可能であるし、プリント配線板の基材を間にして上下方
向に対向電極を設けてコンデンサ構造を形成してもよい
ものである。
The capacitor can be modified other than the illustrated form, and a capacitor structure may be formed by providing counter electrodes in the vertical direction with the base material of the printed wiring board in between.

【0064】[0064]

【発明の効果】デジタル信号を出力するIC端子の近傍
で信号線−電源および信号線−GND間の双方に、コン
デンサ部品を実装するか、あるいはプリントパターン等
で容量性のパターンを形成することで、HighからL
ow状態への信号変化のみならず特にデジタル信号がL
owからHigh状態への過渡期において高周波電流が
流れる経路を最短にできるため不要輻射対策に効果が大
きい。
EFFECT OF THE INVENTION By mounting a capacitor component or forming a capacitive pattern such as a printed pattern on both the signal line-power source and the signal line-GND near the IC terminal for outputting a digital signal. , High to L
Not only the signal change to the ow state, but especially the digital signal is L
Since the path through which the high-frequency current flows can be minimized during the transition period from the ow to the High state, it is highly effective as a countermeasure against unwanted radiation.

【0065】また、信号線の一部または全部を電源線と
GND線の双方でガードすることで、電源とGNDの双
方に信号線から容量を付加した特性を示し、さらに効果
的である。
Further, by guarding a part or all of the signal line with both the power supply line and the GND line, it is possible to exhibit a characteristic that capacitance is added from the signal line to both the power supply and the GND, which is more effective.

【0066】尚、本発明は上記した実施例に限定される
ことはなく、本発明の主旨の範囲内で適宜変形、組合せ
できることはいうまでもないことである。
It is needless to say that the present invention is not limited to the above-mentioned embodiments, and can be appropriately modified and combined within the scope of the gist of the present invention.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電気回路板の模式的配置を説明する模
式図である。
FIG. 1 is a schematic diagram illustrating a schematic arrangement of an electric circuit board of the present invention.

【図2】本発明の電気回路板の回路構成を説明するため
の概略的回路図である。
FIG. 2 is a schematic circuit diagram for explaining a circuit configuration of an electric circuit board of the present invention.

【図3】本発明の電気回路板の模式的配置を説明する模
式図である。
FIG. 3 is a schematic diagram illustrating a schematic arrangement of an electric circuit board of the present invention.

【図4】本発明の電気回路板の模式的配置を説明する模
式図である。
FIG. 4 is a schematic diagram illustrating a schematic arrangement of an electric circuit board of the present invention.

【図5】本発明の電気回路板の模式的配置を説明する模
式図である。
FIG. 5 is a schematic diagram illustrating a schematic arrangement of an electric circuit board of the present invention.

【図6】従来の電気回路板の模式的配置を説明する模式
図である。
FIG. 6 is a schematic diagram illustrating a schematic arrangement of a conventional electric circuit board.

【図7】従来の電気回路板の回路構成を説明するための
概略的回路図である。
FIG. 7 is a schematic circuit diagram for explaining a circuit configuration of a conventional electric circuit board.

【符号の説明】[Explanation of symbols]

1 IC(集積回路素子) 2 電源ピン 3 出力信号ピン 4 GNDピン 5 電源線 6 GND線 7 信号線 8 コンデンサ 9 コンデンサ 10 IC 11 入力信号ピン 12 抵抗 1 IC (Integrated Circuit Element) 2 Power Supply Pin 3 Output Signal Pin 4 GND Pin 5 Power Supply Line 6 GND Line 7 Signal Line 8 Capacitor 9 Capacitor 10 IC 11 Input Signal Pin 12 Resistance

───────────────────────────────────────────────────── フロントページの続き (72)発明者 稲川 秀穂 東京都大田区下丸子3丁目30番2号キヤノ ン株式会社内 (72)発明者 逢坂 徹 東京都大田区下丸子3丁目30番2号キヤノ ン株式会社内 (72)発明者 寺山 芳実 東京都大田区下丸子3丁目30番2号キヤノ ン株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideho Inagawa, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor, Toru Osaka, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Yoshimi Terayama 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (19)

【特許請求の範囲】[Claims] 【請求項1】 基板上に配された複数の端子を有する集
積回路素子と、該集積回路素子の前記端子近傍におい
て、前記端子と接続される信号線と電源線及び信号線と
グランド線との間にコンデンサを有することを特徴とす
る電気回路板。
1. An integrated circuit element having a plurality of terminals arranged on a substrate, and a signal line and a power supply line connected to the terminal and a signal line and a ground line in the vicinity of the terminal of the integrated circuit element. An electric circuit board having a capacitor between them.
【請求項2】 前記集積回路素子はデジタル信号を取扱
う請求項1に記載の電気回路板。
2. The electric circuit board according to claim 1, wherein the integrated circuit device handles a digital signal.
【請求項3】 前記コンデンサは実装部品である請求項
1に記載の電気回路板。
3. The electric circuit board according to claim 1, wherein the capacitor is a mounted component.
【請求項4】 前記コンデンサは前記基体上に形成され
た導電層を有する請求項1に記載の電気回路板。
4. The electric circuit board according to claim 1, wherein the capacitor has a conductive layer formed on the substrate.
【請求項5】 前記導電層は櫛形パターンを有する請求
項4に記載の電気回路板。
5. The electric circuit board according to claim 4, wherein the conductive layer has a comb pattern.
【請求項6】 前記信号線と接続される前記端子はデジ
タル信号を出力する請求項1に記載野電気回路板。
6. The electric circuit board according to claim 1, wherein the terminal connected to the signal line outputs a digital signal.
【請求項7】 前記コンデンサの容量は10pF以上1
00pF以下の容量を有する請求項1に記載の電気回路
板。
7. The capacitance of the capacitor is 10 pF or more 1
The electric circuit board according to claim 1, having a capacitance of 00 pF or less.
【請求項8】 前記信号線と前記電源線との間に設けら
れた前記コンデンサの容量と、前記信号線と前記グラン
ド線との間に設けられた前記コンデンサの容量は等しい
請求項1に記載の電気回路板。
8. The capacitance of the capacitor provided between the signal line and the power supply line is equal to the capacitance of the capacitor provided between the signal line and the ground line. Electric circuit board.
【請求項9】 前記信号線と前記電源線との間に設けら
れた前記コンデンサの容量と、前記信号線と前記グラン
ド線との間に設けられた前記コンデンサの容量は異なっ
ている請求項1に記載の電気回路板。
9. The capacitance of the capacitor provided between the signal line and the power supply line is different from the capacitance of the capacitor provided between the signal line and the ground line. The electric circuit board according to.
【請求項10】 前記集積回路素子の特性に応じて前記
コンデンサの容量が変えられている請求項1に記載の電
気回路板。
10. The electric circuit board according to claim 1, wherein the capacitance of the capacitor is changed according to the characteristics of the integrated circuit element.
【請求項11】 基体と、該基体上の集積回路素子が配
される位置に、前記集積回路素子の複数の端子に対応し
て設けられたランド部と該ランド部に接続された配線と
を有するプリント配線板において、前記ランド部近傍で
前記配線の1つと該配線とは異なる2つの配線との間に
夫々コンデンサを有することを特徴とするプリント配線
板。
11. A base, a land portion provided at a position on the base where the integrated circuit element is arranged, corresponding to a plurality of terminals of the integrated circuit element, and a wiring connected to the land portion. A printed wiring board having the same, wherein each of the wirings has a capacitor between one of the wirings and two wirings different from the wiring in the vicinity of the land portion.
【請求項12】 前記配線の1つは信号線として使用さ
れ、該配線とは異なる2つの配線は1つが電源線とし
て、残りの1つがグランド線として使用される請求項1
1に記載のプリント配線板。
12. One of the wirings is used as a signal line, and two wirings different from the wirings are used as a power supply line and the remaining one is used as a ground line.
The printed wiring board according to 1.
【請求項13】 前記信号線はデジタル信号を取扱う請
求項12に記載のプリント配線板。
13. The printed wiring board according to claim 12, wherein the signal line handles a digital signal.
【請求項14】 前記コンデンサは前記基体上に形成さ
れた導電層によって形成されている請求項11に記載の
プリント配線板。
14. The printed wiring board according to claim 11, wherein the capacitor is formed of a conductive layer formed on the substrate.
【請求項15】 前記導電層は櫛形パターンを有する請
求項14に記載のプリント配線板。
15. The printed wiring board according to claim 14, wherein the conductive layer has a comb pattern.
【請求項16】 前記コンデンサの容量は夫々等しい請
求項11に記載のプリント配線板。
16. The printed wiring board according to claim 11, wherein the capacitors have the same capacitance.
【請求項17】 前記コンデンサの容量は夫々異なる請
求項11に記載のプリント配線板。
17. The printed wiring board according to claim 11, wherein the capacitors have different capacities.
【請求項18】 前記コンデンサの容量は集積回路素子
の特性に応じて異なっている請求項17に記載のプリン
ト配線板。
18. The printed wiring board according to claim 17, wherein the capacitance of the capacitor differs depending on the characteristics of the integrated circuit device.
【請求項19】 前記コンデンサの容量は10pF以上
100pF以下の容量を有する請求項11に記載のプリ
ント配線板。
19. The printed wiring board according to claim 11, wherein the capacitor has a capacitance of 10 pF or more and 100 pF or less.
JP16110494A 1994-07-13 1994-07-13 Electric circuit board and printed wiring board Expired - Fee Related JP3554028B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16110494A JP3554028B2 (en) 1994-07-13 1994-07-13 Electric circuit board and printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16110494A JP3554028B2 (en) 1994-07-13 1994-07-13 Electric circuit board and printed wiring board

Publications (2)

Publication Number Publication Date
JPH0832200A true JPH0832200A (en) 1996-02-02
JP3554028B2 JP3554028B2 (en) 2004-08-11

Family

ID=15728687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16110494A Expired - Fee Related JP3554028B2 (en) 1994-07-13 1994-07-13 Electric circuit board and printed wiring board

Country Status (1)

Country Link
JP (1) JP3554028B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006098076A1 (en) * 2005-03-15 2006-09-21 Murata Manufacturing Co., Ltd. Circuit board
JP2008124105A (en) * 2006-11-09 2008-05-29 Seiko Epson Corp Multilayer printed-wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006098076A1 (en) * 2005-03-15 2006-09-21 Murata Manufacturing Co., Ltd. Circuit board
JP2008124105A (en) * 2006-11-09 2008-05-29 Seiko Epson Corp Multilayer printed-wiring board

Also Published As

Publication number Publication date
JP3554028B2 (en) 2004-08-11

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