WO2002043150A1 - Pad protective circuit - Google Patents

Pad protective circuit Download PDF

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Publication number
WO2002043150A1
WO2002043150A1 PCT/JP2001/010099 JP0110099W WO0243150A1 WO 2002043150 A1 WO2002043150 A1 WO 2002043150A1 JP 0110099 W JP0110099 W JP 0110099W WO 0243150 A1 WO0243150 A1 WO 0243150A1
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Prior art keywords
pad
protection circuit
circuit
diodes
power supply
Prior art date
Application number
PCT/JP2001/010099
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French (fr)
Japanese (ja)
Inventor
Takeshi Ikeda
Hiroshi Miyagi
Original Assignee
Niigata Seimitsu Co., Ltd.
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Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Publication of WO2002043150A1 publication Critical patent/WO2002043150A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a pad protection circuit, and is particularly suitable for use in a circuit for protecting a data input / output pad provided on a semiconductor chip from static electricity or the like.
  • FIG. 1 schematically shows a chip layout of a general semiconductor integrated circuit.
  • reference numeral 101 denotes an IC chip, and a plurality of data input / output pads 102 are arranged around the IC chip. These pads 102 are electrically connected to a lead frame or a printed circuit board (not shown) by bonding wires 103. Inside the pad 102, that is, in the center of the IC chip 101, there is a core 104 on which a logic circuit is mounted.
  • a protection circuit is provided for the pad 102 so that the IC chip 101 is not destroyed by static electricity or noise externally applied through the data input / output pad 102.
  • FIG. 2 is a diagram showing a configuration of a conventional pad protection circuit.
  • an amplifier circuit 111 amplifies signals input to and output from the core unit 104 via the pad 102, and is provided at the outermost periphery of the core unit 104.
  • a pad protection circuit is provided between the amplifier circuit 111 and the pad 102.
  • the pad protection circuit is composed of a metal wiring 1 extending from the node 102.
  • the two diodes 1 13 and 1 14 are connected in the same direction from ground to the power supply Vcc via 1 2, and the metal wiring 1 1 2 extending from the pad 102 and the amplifier circuit are connected. It is configured by connecting a resistor 115 between the metal wiring 111 extending from 111. With such a configuration, excessive signals generated by static electricity and noise flow into the power supply V cc by the diodes 113 and 114, and excess current flows into the core 104 through the amplifier circuit 111. Is prevented.
  • the present invention has been made to solve such a problem, and it is an object of the present invention to reduce the wiring length from a pad to an amplifier circuit so that deterioration of high-frequency characteristics can be suppressed. . Disclosure of the invention
  • a pad protection circuit is a protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted.
  • the protection circuit includes a semiconductor element for flowing the generated excess signal to ground or a power supply, and the semiconductor element is connected to the pad.
  • a protection circuit provided for the pad is provided in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logical circuit is mounted.
  • the above pad and the above pad A resistor connected between the amplifier and an amplifier circuit for amplifying a signal input / output via the input / output terminal; and a semiconductor element connected to the pad for flowing an excessive signal generated to the ground or a power supply. It is characterized by having.
  • the semiconductor device includes two diodes, and at least one of the two diodes is disposed in an empty space generated between an adjacent pad and its protection circuit.
  • a protection provided for the pad is provided in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted.
  • a protection circuit provided for the pad is provided in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted. And a resistor connected between the pad and an amplifier circuit for amplifying a signal input / output via the pad, and an excess signal generated by being connected to a wiring provided outside the pad. And a semiconductor element for flowing the current into a ground or a power supply.
  • the present invention comprises the above technical means, it is not necessary to lengthen the wiring between the pad and the amplifier circuit to connect the semiconductor element of the pad protection circuit, and the wiring between the pad and the amplifier circuit is not required.
  • the length can be shortened. Therefore, the influence of noise or the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art.
  • FIG. 1 is a diagram schematically showing a chip layout of a general semiconductor integrated circuit.
  • FIG. 2 is a diagram showing a configuration of a conventional pad protection circuit.
  • FIG. 3 is a diagram illustrating a configuration example of the pad protection circuit according to the first embodiment.
  • FIG. 4 is a diagram illustrating a configuration example of a pad protection circuit according to the second embodiment.
  • FIG. 5 is a diagram illustrating a configuration example of a pad protection circuit according to the third embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of the pad protection circuit according to the first embodiment.
  • reference numeral 1 denotes an IC chip, and a plurality of data input / output pads 2 are arranged around the IC chip.
  • FIG. 3 shows only one pad 2 as a representative, but actually a plurality of pads 2 are arranged in the same manner as the chip layout in FIG. It is electrically connected to the circuit board.
  • a core unit 8 Inside the pad 2, that is, at the center of the IC chip 1, there is a core unit 8 on which a logic circuit is mounted.
  • An amplifier circuit 7 for amplifying a signal input / output to / from the core unit 8 via the pad 2 is provided on the outermost periphery of the core unit 8.
  • a protection circuit is provided for head 2.
  • This pad protection circuit includes two diodes 3 and 4 and a resistor 5.
  • the resistor 5 is connected between the metal wiring 6 extending from the pad 2 and the metal wiring 9 extending from the amplifier circuit 7 as in the related art.
  • the two diodes 3 and 4 are connected not to the metal wiring 6 but to the pad 2 itself.
  • the first diode 3 is connected between the ground and the pad 2
  • the second diode 4 is connected between the pad 2 and the power supply Vcc. At this time, these two diodes 3 and 4 are connected in series via the pad 2 so that the forward direction is directed from the ground to the power supply Vcc.
  • the two diodes 3 and 4 are connected to the pad 2 itself instead of the metal wiring 6 between the pad 2 and the amplifier circuit 7, so that the diodes 3 and 4 are connected. Therefore, the length of the metal wiring 6 does not need to be increased, and the wiring length between the pad 2 and the amplifier circuit 7 can be reduced. As a result, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art.
  • the distance from the chip edge to the core edge in the pad area (area other than the core section 8) including the protection circuit is shortened by the extent that the wiring length between the pad 2 and the amplifier circuit 7 can be shortened. Therefore, the area of the core 8 can be increased accordingly. As a result, there is an advantage that more circuit elements constituting a logic circuit important for the IC chip 1 can be integrated in the core unit 8 more.
  • FIG. 4 is a diagram illustrating a configuration example of a pad protection circuit according to the second embodiment.
  • the same components as those shown in FIG. 3 are denoted by the same reference numerals.
  • reference numeral 10 denotes an IC chip, and a plurality of data input / output pads 2 are arranged around the IC chip. Although only one pad 2 is shown in FIG. 4 as a representative, in practice, a plurality of pads 2 are arranged in the same manner as the chip layout of FIG. It is electrically connected to the printed circuit board.
  • the pad 2 Inside the pad 2, that is, at the center of the IC chip 10, there is a core unit 8 on which a logic circuit is mounted.
  • An amplifier circuit 7 for amplifying a signal input / output to / from the core unit 8 via the pad 2 is provided on the outermost periphery of the core unit 8.
  • the pad 2 and the amplifier circuit 7 are connected by metal wires 6 and 9 having a shorter length and a resistor 5 as compared with the related art.
  • the metal wiring 11 is provided on the opposite side of the metal wiring 6 from the pad 2, that is, outside the metal pad 6. Then, two diodes 3 and 4 are connected to this metal wiring 11.
  • the first diode 3 is connected between the ground and the metal wiring 11, and the second diode 4 is connected between the metal wiring 11 and the power supply V cc. At this time, these two diodes 3 and 4 are connected in series via the metal wiring 11 such that the forward direction is directed from the ground to the power supply Vcc.
  • the two diodes 3 and 4 are connected to the outside of the pad 2 instead of the metal wiring 6 between the pad 2 and the amplifier circuit 7, so that the diodes 3 and 4 are connected. It is not necessary to lengthen the metal wiring 6 to connect the wirings, and the wiring length between the pad 2 and the amplifier circuit 7 can be shortened. As a result, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art.
  • the diode 3 , 4 are connected to both sides of pad 2, so the space between adjacent pads 2 is wider than before.
  • the diodes 3 and 4 are connected to both sides of the metal wiring 11 having a width smaller than that of the pad 2, so that the distance between the adjacent pads 2 is different from the conventional one. It can be suppressed to the same extent.
  • the bonding wire is described as being connected to the pad 2, but may be connected to the metal wiring 11.
  • FIG. 5 is a diagram illustrating a configuration example of a pad protection circuit according to the third embodiment.
  • the same components as those shown in FIG. 3 are denoted by the same reference numerals.
  • the pad protection circuit of the third embodiment is similar to the pad protection circuit of the first embodiment.
  • the two diodes 3 and 4 are connected to the diode 2 itself, but the arrangement of the diodes 3 and 4 is modified.
  • FIG. As shown in the figure, of the two horizontally adjacent pads 2, a first diode 3 connected to one pad 2 and a second diode connected to the other pad 2 4 and are arranged vertically.
  • the excess signal generated in the pad 2 is supplied to the power supply V cc, but may be supplied to the ground.
  • the present invention is useful for shortening the wiring length from a pad to an amplifier circuit so that deterioration of high-frequency characteristics can be suppressed.

Abstract

Diodes (3, 4) for causing an excess signal generated in a pad because of static electricity to flow into a power supply (Vcc) are connected to the pad (2) itself not to a metallic line (6) between the pad (2) and an amplifier circuit (7). It is unnecessary to increase the length of the metallic line (6) between the pad (2) and the amplifier circuit (7) to connect the diodes (3, 4), and consequently it is possible to short the length of the line between the pad (2) and the amplifier circuit (7). Thus, noise hardly influences the high-frequency signal transmitted through the lines.

Description

明 細 書 パッ ドの保護回路 技術分野  Description Pad protection circuit Technical field
本発明はパッ ドの保護回路に関し、 特に、 半導体チップに備えられる データ入出力用のパッ ドを静電気等から保護するための回路に用いて好 適なものである。 背景技術  The present invention relates to a pad protection circuit, and is particularly suitable for use in a circuit for protecting a data input / output pad provided on a semiconductor chip from static electricity or the like. Background art
図 1 に、 一般的な半導体集積回路のチップレイァゥ トを概略的に示す 。 図 1 において、 1 0 1 は I Cチップであり、 その周辺部にデータ入出 力用のパッ ド 1 0 2が複数配置されている。 これらのパッ ド 1 0 2は、 ボンディ ングワイヤ 1 0 3によって図示しないリー ドフレームあるいは プリ ン ト回路基板と電気的に接続されている。 パッ ド 1 0 2の内側、 す なわち I Cチップ 1 0 1 の中心部には、 論理回路が実装されるコア部 1 0 4が存在する。  FIG. 1 schematically shows a chip layout of a general semiconductor integrated circuit. In FIG. 1, reference numeral 101 denotes an IC chip, and a plurality of data input / output pads 102 are arranged around the IC chip. These pads 102 are electrically connected to a lead frame or a printed circuit board (not shown) by bonding wires 103. Inside the pad 102, that is, in the center of the IC chip 101, there is a core 104 on which a logic circuit is mounted.
通常、 データ入出力用のパッ ド 1 0 2 を通して外部から与えられる静 電気や雑音などによって I Cチップ 1 0 1が破壊されないように、 パッ ド 1 0 2に対して保護回路が設けられる。  Usually, a protection circuit is provided for the pad 102 so that the IC chip 101 is not destroyed by static electricity or noise externally applied through the data input / output pad 102.
図 2は、 従来のパッ ド保護回路の構成を示す図である。 図 2 において 、 増幅回路 1 1 1 は、 パッ ド 1 0 2 を介してコア部 1 0 4に入出力され る信号の増幅を行う ものであり、 コア部 1 0 4の最外周に設けられる。 この増幅回路 1 1 1 とパッ ド 1 0 2 との間にパッ ド保護回路が設けられ る。  FIG. 2 is a diagram showing a configuration of a conventional pad protection circuit. In FIG. 2, an amplifier circuit 111 amplifies signals input to and output from the core unit 104 via the pad 102, and is provided at the outermost periphery of the core unit 104. A pad protection circuit is provided between the amplifier circuit 111 and the pad 102.
すなわち、 パッ ド保護回路は、 ノ、 °ッ ド 1 0 2から伸びるメタル配線 1 1 2 を介して 2つのダイオー ド 1 1 3 , 1 1 4をグラン ドから電源 V c cへと同方向に向けて接続するとともに、 パッ ド 1 0 2から伸びるメタ ル配線 1 1 2 と増幅回路 1 1 1から伸びるメタル配線 1 1 6 との間に抵 抗 1 1 5 を接続することによって構成される。 このような構成により、 静電気やノイズによって発生する過剰な信号がダイオー ド 1 1 3 ， 1 1 4によって電源 V c c に流し込まれ、 増幅回路 1 1 1 を通じてコア部 1 0 4内に過剰電流が流れ込むのを防止している。 That is, the pad protection circuit is composed of a metal wiring 1 extending from the node 102. The two diodes 1 13 and 1 14 are connected in the same direction from ground to the power supply Vcc via 1 2, and the metal wiring 1 1 2 extending from the pad 102 and the amplifier circuit are connected. It is configured by connecting a resistor 115 between the metal wiring 111 extending from 111. With such a configuration, excessive signals generated by static electricity and noise flow into the power supply V cc by the diodes 113 and 114, and excess current flows into the core 104 through the amplifier circuit 111. Is prevented.
しかしながら、 上記従来の技術では、 パッ ド 1 0 2 と増幅回路 1 1 1 との間にダイオー ド 1 1 3 , 1 1 4を含むパッ ド保護回路が設けられる ため、 パッ ド 1 0 2 と増幅回路 1 1 1 との配線距離が長くなつてしまう 。 そのため、 特に I Cチップ 1 0 1が高周波回路を実装している場合に は、 入出力される高周波信号が長い配線上でノイズ等の影響を受けてし まい、 高周波特性が劣化してしまうという問題があった。  However, in the above-mentioned conventional technology, since a pad protection circuit including diodes 113 and 114 is provided between the pad 102 and the amplifier circuit 111, the pad 102 and the amplifier 102 are not connected to each other. The wiring distance to the circuit 1 1 1 becomes longer. Therefore, especially when the IC chip 101 is mounted with a high-frequency circuit, a high-frequency signal to be input and output is affected by noise or the like on a long wiring, thereby deteriorating the high-frequency characteristics. was there.
本発明は、 このような問題を解決するために成されたものであり、 パ ッ ドから増幅回路までの配線長を短く して高周波特性の劣化を抑制でき るようにすることを目的とする。 発明の開示  The present invention has been made to solve such a problem, and it is an object of the present invention to reduce the wiring length from a pad to an amplifier circuit so that deterioration of high-frequency characteristics can be suppressed. . Disclosure of the invention
本発明によるパッ ドの保護回路は、 複数のパッ ドが配列されるパッ ド 領域と、 論理回路が実装されるコア部とを有する半導体集積回路におい て、 上記パッ ドに対して設けられる保護回路であって、 上記保護回路は 、 発生した過剰信号をグランドまたは電源に流し込むための半導体素子 を含み、 上記半導体素子を上記パッ ドに接続したことを特徴とする。 本発明の他の態様では、 複数のパッ ドが配列されるパッ ド領域と、 論 理回路が実装されるコア部とを有する半導体集積回路において、 上記パ ッ ドに対して設けられる保護回路であって、 上記パッ ドと上記パッ ドを 介して入出力される信号の増幅を行う増幅回路との間に接続された抵抗 と、 上記パッ ドに対して接続され、 発生した過剰信号をグラン ドまたは 電源に流し込むための半導体素子とを備えたことを特徴とする。 A pad protection circuit according to the present invention is a protection circuit provided for a pad in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted. Wherein the protection circuit includes a semiconductor element for flowing the generated excess signal to ground or a power supply, and the semiconductor element is connected to the pad. According to another aspect of the present invention, in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logical circuit is mounted, a protection circuit provided for the pad is provided. And the above pad and the above pad A resistor connected between the amplifier and an amplifier circuit for amplifying a signal input / output via the input / output terminal; and a semiconductor element connected to the pad for flowing an excessive signal generated to the ground or a power supply. It is characterized by having.
本発明のその他の態様では、 上記半導体素子は 2つのダイォー ドから 成り、 上記 2 つのダイオー ドの少なく とも一方を、 隣接するパッ ドおよ びその保護回路の間に生じる空きスペースに配置したことを特徴とする 本発明のその他の態様では、 複数のパッ ドが配列されるパッ ド領域と 、 論理回路が実装されるコア部とを有する半導体集積回路において、 上 記パッ ドに対して設けられる保護回路であって、 上記保護回路は、 発生 した過剰信号をグラン ドまたは電源に流し込むための半導体素子を含み 、 上記パッ ドの外側に設けた配線に上記半導体素子を接続したことを特 徴とする。  According to another aspect of the present invention, the semiconductor device includes two diodes, and at least one of the two diodes is disposed in an empty space generated between an adjacent pad and its protection circuit. According to another aspect of the present invention, in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, a protection provided for the pad is provided. A circuit, wherein the protection circuit includes a semiconductor element for flowing a generated excess signal to a ground or a power supply, and is characterized in that the semiconductor element is connected to a wiring provided outside the pad. .
本発明のその他の態様では、 複数のパッ ドが配列されるパッ ド領域と 、 論理回路が実装されるコア部とを有する半導体集積回路において、 上 記パッ ドに対して設けられる保護回路であって、 上記パッ ドと上記パッ ドを介して入出力される信号の増幅を行う増幅回路との間に接続された 抵抗と、 上記パッ ドの外側に設けた配線に接続され、 発生した過剰信号 をグラン ドまたは電源に流し込むための半導体素子とを備えたことを特 徴とする。  According to another aspect of the present invention, in a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, a protection circuit provided for the pad is provided. And a resistor connected between the pad and an amplifier circuit for amplifying a signal input / output via the pad, and an excess signal generated by being connected to a wiring provided outside the pad. And a semiconductor element for flowing the current into a ground or a power supply.
本発明は上記技術手段より成るので、 パッ ド保護回路の半導体素子を 接続するためにパッ ドと増幅回路との間の配線を長く しなくても済み、 パッ ドと増幅回路との間の配線長を短くすることができる。 したがって 、 配線上を流れる高周波信号に対するノイズ等の影響を抑制することが でき、 従来に比べて高周波特性を向上させることができる。 図面の簡単な説明 Since the present invention comprises the above technical means, it is not necessary to lengthen the wiring between the pad and the amplifier circuit to connect the semiconductor element of the pad protection circuit, and the wiring between the pad and the amplifier circuit is not required. The length can be shortened. Therefore, the influence of noise or the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art. BRIEF DESCRIPTION OF THE FIGURES
図 1 は、 一般的な半導体集積回路のチップレイアウ トを概略的に示す 図である。  FIG. 1 is a diagram schematically showing a chip layout of a general semiconductor integrated circuit.
図 2は、 従来のパッ ド保護回路の構成を示す図である。  FIG. 2 is a diagram showing a configuration of a conventional pad protection circuit.
図 3は、 第 1 の実施形態によるパッ ド保護回路の構成例を示す図であ る。  FIG. 3 is a diagram illustrating a configuration example of the pad protection circuit according to the first embodiment.
図 4は、 第 2の実施形態によるパッ ド保護回路の構成例を示す図であ る。  FIG. 4 is a diagram illustrating a configuration example of a pad protection circuit according to the second embodiment.
図 5は、 第 3の実施形態によるパッ ド保護回路の構成例を示す図であ る。 発明を実施するための最良の形態  FIG. 5 is a diagram illustrating a configuration example of a pad protection circuit according to the third embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の一実施形態を図面に基づいて説明する。  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
図 3は、 第 1 の実施形態によるパッ ド保護回路の構成例を示す図であ る。 図 3 において、 1 は I Cチップであり、 その周辺部にデータ入出力 用のパッ ド 2が複数配置されている。  FIG. 3 is a diagram illustrating a configuration example of the pad protection circuit according to the first embodiment. In FIG. 3, reference numeral 1 denotes an IC chip, and a plurality of data input / output pads 2 are arranged around the IC chip.
なお、 図 3では代表として 1個のパッ ド 2のみを示しているが、 実際 には図 1 のチップレイァゥ 卜と同様に複数のパッ ド 2が配列されており 、 ボンディ ングワイヤによってリードフレームあるいはプリ ント回路基 板と電気的に接続されている。  Note that FIG. 3 shows only one pad 2 as a representative, but actually a plurality of pads 2 are arranged in the same manner as the chip layout in FIG. It is electrically connected to the circuit board.
パッ ド 2 の内側、 すなわち I Cチップ 1 の中心部には、 論理回路が実 装されるコア部 8が存在する。 このコア部 8の最外周には、 パッ ド 2 を 介してコア部 8 に入出力される信号の増幅を行う増幅回路 7が設けられ る。  Inside the pad 2, that is, at the center of the IC chip 1, there is a core unit 8 on which a logic circuit is mounted. An amplifier circuit 7 for amplifying a signal input / output to / from the core unit 8 via the pad 2 is provided on the outermost periphery of the core unit 8.
本実施形態においても、 パッ ド 2 を通して外部から与えられる静電気 や雑音などによって I Cチップ 1が破壊されないようにするために、 ノヽ ッ ド 2 に対して保護回路を設けている。 このパッ ド保護回路は、 2つの ダイオー ド 3 , 4および抵抗 5 を備えて構成される。 Also in the present embodiment, in order to prevent the IC chip 1 from being destroyed by static electricity or noise externally applied through the pad 2, A protection circuit is provided for head 2. This pad protection circuit includes two diodes 3 and 4 and a resistor 5.
本実施形態において、 抵抗 5 については、 従来と同様に、 パッ ド 2か ら伸びるメタル配線 6 と増幅回路 7から伸びるメタル配線 9 との間に接 続される。 一方、 2つのダイオー ド 3 , 4は、 メタル配線 6ではなく、 パッ ド 2そのものに接続している。  In the present embodiment, the resistor 5 is connected between the metal wiring 6 extending from the pad 2 and the metal wiring 9 extending from the amplifier circuit 7 as in the related art. On the other hand, the two diodes 3 and 4 are connected not to the metal wiring 6 but to the pad 2 itself.
すなわち、 グラン ドとパッ ド 2 との間に第 1 のダイオー ド 3 を接続し 、 パッ ド 2 と電源 V c c との間に第 2のダイオー ド 4 を接続する。 この とき、 これら 2つのダイオー ド 3 , 4を、 共に順方向がグラン ドから電 源 V c c の方向に向くようにパッ ド 2 を介して直列に接続する。  That is, the first diode 3 is connected between the ground and the pad 2, and the second diode 4 is connected between the pad 2 and the power supply Vcc. At this time, these two diodes 3 and 4 are connected in series via the pad 2 so that the forward direction is directed from the ground to the power supply Vcc.
このような構成により、 静電気やノイズによってパッ ド 2 に過剰な信 号が発生しても、 それがダイオー ド 3 , 4を介して電源 V c c に流し込 まれる。 これにより、 増幅回路 7 を通じてコア部 8内の論理回路に必要 以上に大きな電流が流れ込むのを防止することができる。  With such a configuration, even if an excessive signal is generated in the pad 2 due to static electricity or noise, the signal is supplied to the power supply V cc via the diodes 3 and 4. As a result, it is possible to prevent an unnecessarily large current from flowing into the logic circuit in the core unit 8 through the amplifier circuit 7.
また、 本実施形態では、 2つのダイオー ド 3 ， 4を、 パッ ド 2 と増幅 回路 7 との間のメタル配線 6ではなくパッ ド 2 自体に接続しているので 、 ダイオー ド 3 ， 4を接続するためにメタル配線 6 を長くする必要がな く、 パッ ド 2 と増幅回路 7 との間の配線長を短くすることができる。 こ れにより、 配線上を流れる高周波信号に対するノイズ等の影響を抑制す ることができ、 従来に比べて高周波特性を向上させることができる。 また、 パッ ド 2 と増幅回路 7 との間の配線長を短くできる分だけ、 保 護回路を含むパッ ド領域 （コア部 8以外の領域） におけるチップエッジ からコア部エッジまでの距離を短くすることができ、 それだけコア部 8 の面積を大きく とることができる。 これにより、 I Cチップ 1 にとつて 重要な論理回路を構成する回路素子をコア部 8 に対してより多く集積化 することができるというメ リ ッ トも有する。 次に、 本発明の第 2の実施形態について説明する。 Also, in the present embodiment, the two diodes 3 and 4 are connected to the pad 2 itself instead of the metal wiring 6 between the pad 2 and the amplifier circuit 7, so that the diodes 3 and 4 are connected. Therefore, the length of the metal wiring 6 does not need to be increased, and the wiring length between the pad 2 and the amplifier circuit 7 can be reduced. As a result, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art. In addition, the distance from the chip edge to the core edge in the pad area (area other than the core section 8) including the protection circuit is shortened by the extent that the wiring length between the pad 2 and the amplifier circuit 7 can be shortened. Therefore, the area of the core 8 can be increased accordingly. As a result, there is an advantage that more circuit elements constituting a logic circuit important for the IC chip 1 can be integrated in the core unit 8 more. Next, a second embodiment of the present invention will be described.
図 4は、 第 2の実施形態によるパッ ド保護回路の構成例を示す図であ る。 この図 4において、 図 3 に示した構成要素と同一の構成要素には同 一の符号を付している。  FIG. 4 is a diagram illustrating a configuration example of a pad protection circuit according to the second embodiment. In FIG. 4, the same components as those shown in FIG. 3 are denoted by the same reference numerals.
図 4において、 1 0は I Cチップであり、 その周辺部にデータ入出力 用のパッ ド 2が複数配置されている。 この図 4でも代表として 1個のパ ッ ド 2のみを示しているが、 実際には図 1 のチップレイアウ トと同様に 複数のパッ ド 2が配列されており、 ボンディ ングワイヤによってリー ド フレームあるいはプリ ン ト回路基板と電気的に接続されている。  In FIG. 4, reference numeral 10 denotes an IC chip, and a plurality of data input / output pads 2 are arranged around the IC chip. Although only one pad 2 is shown in FIG. 4 as a representative, in practice, a plurality of pads 2 are arranged in the same manner as the chip layout of FIG. It is electrically connected to the printed circuit board.
パッ ド 2の内側、 すなわち I Cチップ 1 0の中心部には、 論理回路が 実装されるコア部 8が存在する。 このコア部 8の最外周には、 パッ ド 2 を介してコア部 8に入出力される信号の増幅を行う増幅回路 7が設けら れる。 パッ ド 2 と増幅回路 7 との間は、 第 1 の実施形態と同様に、 従来 に比べて長さの短いメタル配線 6 , 9 と抵抗 5 とによって接続される。 本実施形態においては、 メタル配線 6 に対してパッ ド 2 の反対側、 す なわちパッ ド 2の外側に、 メタル配線 1 1 を設けている。 そして、 2つ のダイオー ド 3 ， 4をこのメタル配線 1 1 に接続している。  Inside the pad 2, that is, at the center of the IC chip 10, there is a core unit 8 on which a logic circuit is mounted. An amplifier circuit 7 for amplifying a signal input / output to / from the core unit 8 via the pad 2 is provided on the outermost periphery of the core unit 8. As in the first embodiment, the pad 2 and the amplifier circuit 7 are connected by metal wires 6 and 9 having a shorter length and a resistor 5 as compared with the related art. In the present embodiment, the metal wiring 11 is provided on the opposite side of the metal wiring 6 from the pad 2, that is, outside the metal pad 6. Then, two diodes 3 and 4 are connected to this metal wiring 11.
すなわち、 グラン ドとメタル配線 1 1 との間に第 1 のダイオード 3 を 接続し、 メタル配線 1 1 と電源 V c c との間に第 2のダイオー ド 4を接 続する。 このとき、 これら 2つのダイオー ド 3 ， 4を、 共に順方向がグ ラン ドから電源 V c c の方向に向くようにメタル配線 1 1 を介して直列 に接続する。  That is, the first diode 3 is connected between the ground and the metal wiring 11, and the second diode 4 is connected between the metal wiring 11 and the power supply V cc. At this time, these two diodes 3 and 4 are connected in series via the metal wiring 11 such that the forward direction is directed from the ground to the power supply Vcc.
このような構成により、 静電気やノイズによってパッ ド 2 に過剰な信 号が発生しても、 それがダイオード 3 ， 4を介して電源 V c c に流し込 まれる。 これにより、 増幅回路 7 を通じてコア部 8内の論理回路に必要 以上に大きな電流が流れ込むのを防止することができる。 With such a configuration, even if an excessive signal is generated in the pad 2 due to static electricity or noise, it flows into the power supply V cc via the diodes 3 and 4. This makes it necessary for the logic circuit in the core unit 8 through the amplifier circuit 7. It is possible to prevent a larger current from flowing.
また、 本実施形態では、 2つのダイオー ド 3 ， 4を、 パッ ド 2 と増幅 回路 7 との間のメタル配線 6ではなく、 パッ ド 2の外側に接続している ので、 ダイオー ド 3 , 4を接続するためにメタル配線 6 を長くする必要 がなく、 パッ ド 2 と増幅回路 7 との間の配線長を短くすることができる 。 これにより、 配線上を流れる高周波信号に対するノイズ等の影響を抑 制することができ、 従来に比べて高周波特性を向上させることができる さ らに、 上述した第 1 の実施形態では、 ダイオー ド 3 , 4をパッ ド 2 の両側に接続していたので、 隣接するパッ ド 2の間隔は従来に比べて広 くなる。 これに対して、 第 2 の実施形態によれば、 パッ ド 2より も幅の 狭いメタル配線 1 1 の両側にダイオード 3 , 4を接続しているので、 隣 接するパッ ド 2の間隔は従来と同程度に抑えることができる。  Also, in this embodiment, the two diodes 3 and 4 are connected to the outside of the pad 2 instead of the metal wiring 6 between the pad 2 and the amplifier circuit 7, so that the diodes 3 and 4 are connected. It is not necessary to lengthen the metal wiring 6 to connect the wirings, and the wiring length between the pad 2 and the amplifier circuit 7 can be shortened. As a result, the influence of noise and the like on the high-frequency signal flowing on the wiring can be suppressed, and the high-frequency characteristics can be improved as compared with the related art. In addition, in the first embodiment, the diode 3 , 4 are connected to both sides of pad 2, so the space between adjacent pads 2 is wider than before. On the other hand, according to the second embodiment, the diodes 3 and 4 are connected to both sides of the metal wiring 11 having a width smaller than that of the pad 2, so that the distance between the adjacent pads 2 is different from the conventional one. It can be suppressed to the same extent.
なお、 本実施形態において、 ボンディ ングワイヤはパッ ド 2 に接続す るものとして説明したが、 メタル配線 1 1 に接続するようにしても良い  In the present embodiment, the bonding wire is described as being connected to the pad 2, but may be connected to the metal wiring 11.
次に、 本発明の第 3の実施形態について説明する。 Next, a third embodiment of the present invention will be described.
図 5は、 第 3の実施形態によるパッ ド保護回路の構成例を示す図であ る。 この図 5において、 図 3 に示した構成要素と同一の構成要素には同 一の符号を付している。  FIG. 5 is a diagram illustrating a configuration example of a pad protection circuit according to the third embodiment. In FIG. 5, the same components as those shown in FIG. 3 are denoted by the same reference numerals.
第 3の実施形態のパッ ド保護回路は、 上述した第 1 の実施形態と同様 に、 ノ、。ッ ド 2そのものに 2 つのダイオー ド 3 ， 4 を接続したものである が、 ダイオー ド 3 ， 4の配置に工夫を加えている。  The pad protection circuit of the third embodiment is similar to the pad protection circuit of the first embodiment. The two diodes 3 and 4 are connected to the diode 2 itself, but the arrangement of the diodes 3 and 4 is modified.
すなわち、 第 1 の実施形態では、 2つのダイオー ド 3 , 4を共にパッ ド 2の真横に配置していた。 これに対して、 第 3の実施形態では、 図 5 に示すように、 横方向に隣接する 2つのパッ ド 2のうち、 一方のパッ ド 2 に接続された第 1 のダイォー ド 3 と、 他方のパッ ド 2 に接続された第 2のダイォ一 ド 4 とを縦方向に並べて配置している。 That is, in the first embodiment, the two diodes 3 and 4 are both arranged right beside the pad 2. On the other hand, in the third embodiment, FIG. As shown in the figure, of the two horizontally adjacent pads 2, a first diode 3 connected to one pad 2 and a second diode connected to the other pad 2 4 and are arranged vertically.
つまり、 複数のパッ ド 2 をその保護回路と共に横方向に並べて配列し た場合、 隣接する保護回路の間には若干のスペースが生じる。 本実施形 態では、 このスペースを利用して、 2つのダイオー ド 3 ， 4のうちの少 なく とも一方 （図 5の場合は第 1 のダイオー ド 3 ) を配置する。  In other words, when a plurality of pads 2 are arranged side by side with the protection circuits, some space is created between adjacent protection circuits. In this embodiment, at least one of the two diodes 3 and 4 (the first diode 3 in FIG. 5) is arranged using this space.
このように配置することにより、 隣接するパッ ド 2 の間隔である横方 向の距離を従来と同程度に抑えつつ、 パッ ド領域におけるチップエッジ からコア部エッジまでの縦方向の距離を短くすることができる。 よって 、 チップサイズを大きくすることなく コア部 8の面積を大きく とること ができ、 より多くの回路素子をコア部 8に集積化することができる。 なお、 以上に説明した各実施形態は、 何れも本発明を実施するにあた つての具体化の一例を示したものに過ぎず、 これらによって本発明の技 術的範囲が限定的に解釈されてはならないものである。 すなわち、 本発 明はその精神、 またはその主要な特徴から逸脱することなく、 様々な形 で実施することができる。  This arrangement reduces the vertical distance from the chip edge to the core edge in the pad area while keeping the horizontal distance, which is the distance between adjacent pads 2, at about the same level as before. be able to. Therefore, the area of the core unit 8 can be increased without increasing the chip size, and more circuit elements can be integrated in the core unit 8. It should be noted that each of the embodiments described above is merely an example of a specific embodiment for carrying out the present invention, and the technical scope of the present invention is interpreted in a limited manner. It must not be. That is, the present invention can be implemented in various forms without departing from its spirit or its main features.
例えば、 上記実施形態では、 パッ ド 2 に発生した過剰信号を電源 V c c に流し込むようにしてるが、 グラン ドに流し込むようにしても良い。 産業上の利用可能性  For example, in the above embodiment, the excess signal generated in the pad 2 is supplied to the power supply V cc, but may be supplied to the ground. Industrial applicability
本発明は、 パッ ドから増幅回路までの配線長を短く して高周波特性の 劣化を抑制できるようにするのに有用である。  INDUSTRIAL APPLICABILITY The present invention is useful for shortening the wiring length from a pad to an amplifier circuit so that deterioration of high-frequency characteristics can be suppressed.

Claims

請 求 の 範 囲 The scope of the claims
1 . 複数のパッ ドが配列されるパッ ド領域と、 論理回路が実装されるコ ァ部とを有する半導体集積回路において、 上記パッ ドに対して設けられ る保護回路であつて、 1. In a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, a protection circuit provided for the pad,
上記保護回路は、 発生した過剰信号をグラン ドまたは電源に流し込む ための半導体素子を含み、 上記半導体素子を上記パッ ドに接続したこと を特徴とするパッ ドの保護回路。  The protection circuit for a pad according to claim 1, wherein the protection circuit includes a semiconductor element for flowing a generated excess signal to a ground or a power supply, and the semiconductor element is connected to the pad.
2 . 複数のパッ ドが配列されるパッ ド領域と、 論理回路が実装されるコ ァ部とを有する半導体集積回路において、 上記パッ ドに対して設けられ る保護回路であって、  2. In a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, a protection circuit provided for the pad,
上記パッ ドと上記パッ ドを介して入出力される信号の増幅を行う増幅 回路との間に接続された抵抗と、  A resistor connected between the pad and an amplifier circuit for amplifying a signal input / output via the pad;
上記パッ ドに対して接続され、 発生した過剰信号をグランドまたは電 源に流し込むための半導体素子とを備えたことを特徴とするパッ ドの保 護回路。  A pad protection circuit, comprising: a semiconductor element connected to the pad and configured to allow a generated excess signal to flow to a ground or a power supply.
3 . 上記半導体素子は 2 つのダイオー ドから成り、 上記 2 つのダイォー ドの少なく とも一方を、 隣接するパッ ドおよびその保護回路の間に生じ る空きスペースに配置したことを特徴とする請求の範囲第 1項に記載の パッ ドの保護回路。  3. The semiconductor device comprises two diodes, and at least one of the two diodes is arranged in an empty space created between an adjacent pad and its protection circuit. Pad protection circuit as described in paragraph 1.
4 . 上記半導体素子は 2 つのダイオー ドから成り、 上記 2 つのダイォー ドの少なく とも一方を、 隣接するパッ ドおよびその保護回路の間に生じ る空きスペースに配置したことを特徴とする請求の範囲第 2項に記載の パッ ドの保護回路。  4. The semiconductor device comprises two diodes, and at least one of the two diodes is arranged in an empty space created between an adjacent pad and its protection circuit. Pad protection circuit as described in paragraph 2.
5 . 複数のパッ ドが配列されるパッ ド領域と、 論理回路が実装されるコ ァ部とを有する半導体集積回路において、 上記パッ ドに対して設けられ る保護回路であつて、 5. In a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, the semiconductor integrated circuit is provided for the pad. Protection circuit,
上記保護回路は、 発生した過剰信号をグラン ドまたは電源に流し込む ための半導体素子を含み、 上記パッ ドの外側に設けた配線に上記半導体 素子を接続したことを特徴とするパッ ドの保護回路。  A protection circuit for a pad, wherein the protection circuit includes a semiconductor element for flowing a generated excess signal to a ground or a power supply, and the semiconductor element is connected to a wiring provided outside the pad.
6 . 複数のパッ ドが配列されるパッ ド領域と、 論理回路が実装されるコ ァ部とを有する半導体集積回路において、 上記パッ ドに対して設けられ る保護回路であつて、  6. In a semiconductor integrated circuit having a pad region in which a plurality of pads are arranged and a core portion on which a logic circuit is mounted, a protection circuit provided for the pad,
上記パッ ドと上記パッ ドを介して入出力される信号の増幅を行う増幅 回路との間に接続された抵抗と、  A resistor connected between the pad and an amplifier circuit for amplifying a signal input / output via the pad;
上記パッ ドの外側に設けた配線に接続され、 発生した過剰信号をグラ ン ドまたは電源に流し込むための半導体素子とを備えたことを特徴とす るパッ ドの保護回路。  A pad protection circuit, comprising: a semiconductor element connected to a wiring provided outside the pad, for flowing an excessive signal generated to a ground or a power supply.
PCT/JP2001/010099 2000-11-22 2001-11-19 Pad protective circuit WO2002043150A1 (en)

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JP2000-356674 2000-11-22

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
JP2007094367A (en) * 2005-06-30 2007-04-12 Seiko Epson Corp Integrated circuit device and electronic equipment

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0314265A (en) * 1989-06-12 1991-01-22 Mitsubishi Electric Corp Semiconductor device
JPH0629466A (en) * 1992-07-09 1994-02-04 Nec Corp Semiconductor integrated circuit
JPH11261011A (en) * 1998-03-06 1999-09-24 Nec Corp Protection circuit for semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0314265A (en) * 1989-06-12 1991-01-22 Mitsubishi Electric Corp Semiconductor device
JPH0629466A (en) * 1992-07-09 1994-02-04 Nec Corp Semiconductor integrated circuit
JPH11261011A (en) * 1998-03-06 1999-09-24 Nec Corp Protection circuit for semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007094367A (en) * 2005-06-30 2007-04-12 Seiko Epson Corp Integrated circuit device and electronic equipment

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