JPH06310656A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce propagation of noise of a data circuit to a clock circuit. CONSTITUTION:In a semiconductor circuit containing a clock circuit 22 and a data circuit 31 which are formed on a semiconductor substrate 103, power supply lines 12 and 22 supplying power to the clock circuit and power supply lines 11 and 21 supplying power to the data circuit are formed separately. By coupling them commonly to a bonding pad coupled to an external terminal for power input, noise propagation is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and further to a power supply technology therefor.
The present invention relates to a technique effectively applied to a multiplexer LSI or a demultiplexer LSI as SI.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is necessary to supply power for the operation of each module (block), and such a power supply line is usually made of aluminum wiring.

By the way, for example, a communication LSI has a data system circuit including a logic circuit and a clock system circuit such as a clock generation unit, and a power supply line for supplying power to the data system circuit and a clock generation unit. The power supply line for supplying power to the clock system circuit such as
It was not separated, nor was it necessary.

An example of a document describing the supply technology of semiconductor integrated circuits is "LSI Handbook (page 275)" issued by Ohmsha, Ltd. on November 30, 1984.

[0005]

However, as described above, in the semiconductor integrated circuit having the data system circuit including the logic circuit and the clock system circuit such as the clock generator, the power supply of the data system circuit is performed. The power fluctuation of the line, that is, noise is propagated to the power supply line of the clock system circuit, which may cause jitter in the clock signal.
Therefore, it has been found by the inventor that as the operating frequency of the logic circuit increases, the clock jitter further reduces the timing margin of the logic circuit, thereby limiting the maximum operating frequency of the logic circuit. .

An object of the present invention is to prevent noise from a power supply line of a data system circuit from propagating to a power supply line of a clock system circuit operating at the highest operating frequency or a multi-phase clock system circuit corresponding to the clock circuit. To do.

Another object of the present invention is to reduce clock jitter, improve the timing margin of the logic circuit, and improve the maximum operating frequency of the logic circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit including a clock system circuit and a data system circuit, which are formed on one semiconductor substrate, a power supply line for supplying power to the clock system circuit and the data system. A power supply line for supplying power to the circuit is formed separately from each other,
It is commonly connected to a bonding pad that is connected to an external terminal for power input.

[0011]

According to the above means, the power supply line for supplying power to the clock system circuit and the power supply line for supplying power to the data system circuit are formed separately from each other, The common connection to the bonding pad connected to the external terminal for power input means that the power supply line of the data system circuit is connected to the power supply line of the clock system circuit through the bonding pad that has a low impedance. Therefore, the power supply fluctuation of the data system circuit does not propagate to the clock system circuit, and the occurrence of jitter due to the fluctuation of the power supply line of the clock system circuit is suppressed. This achieves an improvement in the timing margin of the logic circuit.

[0012]

1 shows the layout of a semiconductor integrated circuit according to an embodiment of the present invention.

Although not particularly limited, the semiconductor integrated circuit shown in FIG. 1 is a multiplexer as a communication LSI, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. It

In FIG. 1, 101 is a Vcc bonding pad for supplying a high potential side power source, and 10
Reference numeral 2 is a Vss bonding pad for supplying a low potential side power source. The Vcc bonding pad 101,
The Vss bonding pad 102 is connected to an external power supply terminal for enabling external power supply by a bonding wire.

Reference numeral 103 denotes a semiconductor substrate. On the semiconductor substrate 103, an output buffer for enabling data processing and a result of the processing, a data circuit 31 including various logic circuits, and two types of clock circuits. 41 and 42 are formed. The clock circuit 41 is a circuit that operates at the highest frequency or a multi-phase clock circuit corresponding thereto, while the clock circuit 42 is a clock circuit that operates at a lower frequency than the clock circuit 41.

Corresponding to the data circuit 31, the clock circuit 41, and the clock circuit 42, power supply lines 21, 22, 23 for supplying the high potential side power supply Vcc and a power supply for supplying the low potential side power supply Vss. Supply lines 11, 12, 13
Are individually formed. The power supply lines 21, 22, 2
3 is coupled to the Vcc bonding pad 101, and the power supply lines 21, 22, and 23 share the Vcc bonding pad 101. Similarly, the power supply line 11,
12 and 13 are coupled to the Vss bonding pad 102, and the Vss bonding pad 102 is shared by the power supply lines 11, 12, and 13. In this embodiment, the power supply lines are individually formed in this way, and
By being commonly coupled to the Vcc bonding pad 101 and the Vss bonding pad 102, it is possible to prevent power fluctuations from the power supply lines 11 and 21 of the data circuit 31, that is, noise, from propagating to the power supply line of the clock circuit 41. ing.

FIG. 2 shows an AC equivalent circuit for the power supply lines of the data circuit 31 and the clock circuit 41 in FIG.

In FIG. 2, Z1, Z3, and Z4 are impedances of power supply lines, for example, resistances or inductance components of bonding wires and wirings inside the package. Z2 is the impedance of the logic circuit in the data circuit 31, and Z5 is the impedance of the logic circuit in the clock circuit 41. Further, ΔIn is a current fluctuation due to noise or impedance fluctuation of the logic circuit included in the data circuit 31.

In FIG. 2, if the power supply fluctuation due to ΔIn occurs in the data circuit 31, the fluctuation amount ΔVCLK propagating to the clock circuit 41 is expressed by the following equation. ΔVCLK = (Z1 * Z2 * Z5 (Z1 + Z4 + Z5) ΔIn) / ((Z1 + Z4 + Z5) ² (Z2 + Z3) + Z1 (Z4 + Z5)) …… (1) Here, Z2 Z5 >> Z1, Z3, Z4,
The equation (1) becomes ΔVCLK ≈ Z1ΔIn (2), and this equation (2) shows that the power fluctuation amount ΔVCLK propagating to the clock circuit 41 can be made small if Z1 is sufficiently small.

Therefore, it is possible to suppress the propagation of the power supply fluctuation of the data system to the clock system through the pad portion having the low impedance, reduce the jitter due to the fluctuation of the clock power supply line, and improve the timing margin. Can be improved.

As described above, according to the present embodiment, since the Vcc bonding pads 101 and 102 are connected to the external power source 50 having a low internal impedance via the power source supply line having a low impedance, the power supply of the data circuit 31 is performed. Vcc bonding pad 101 and Vss bonding pad 102 having low impedance due to power fluctuation on the line side
It is not propagated to the power supply line of the clock circuit 41 via the power supply line, and it is possible to suppress the occurrence of jitter due to power supply fluctuation of the power supply lines 12 and 22 of the clock circuit 41.
As a result, the timing margin of the logic circuit included in the data circuit 31 can be improved, and the maximum operating frequency of the logic circuit can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the number of data circuits and clock circuits can be changed appropriately.

In the above description, the case where the invention made by the present inventor is mainly applied to a multiplexer as a communication LSI which is a field of application which is the background of the invention has been described, but the present invention is not limited thereto. ,
It can be widely applied to various semiconductor integrated circuits.

The present invention can be applied on condition that at least a clock system circuit is included.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a power supply line for supplying power to the clock system circuit and a power supply line for supplying power to the data system circuit are formed separately from each other, and external terminals for power supply input are provided. The power supply line of the data system circuit is connected to the power supply line of the clock system circuit through the bonding pad that has a low impedance by commonly connecting to the bonding pad connected to the data system circuit. It is not necessary to propagate the power supply fluctuation to the clock system circuit, and it is possible to suppress the occurrence of jitter due to the fluctuation of the power supply line of the clock system circuit. Further, since it is possible to improve the timing margin of the logic circuit, the maximum operating frequency of the logic circuit can be increased.

[Brief description of drawings]

FIG. 1 is a layout explanatory diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a layout diagram of power supply lines in the semiconductor integrated circuit.

[Explanation of symbols]

 11, 12, 13 Power supply lines 21, 22, 23 Power supply lines 31 Data circuit 41 Clock circuit 42 Clock circuit 50 External power supply 101 Vcc bonding pad 102 Vss bonding pad 103 Semiconductor substrate

Claims (3)

[Claims] 1. A semiconductor integrated circuit including a clock system circuit and a data system circuit, which are formed on one semiconductor substrate, and a power supply line for supplying power to the clock system circuit, and the data system. A semiconductor integrated circuit, wherein a power supply line for supplying power to the circuit is formed separately from each other, and is commonly connected to a bonding pad connected to an external terminal for power input. 2. When a plurality of clock system circuits having different operation clocks are formed, the power supply line of the clock system circuit that handles the clock with the shortest cycle and the power supply line of the other clock system circuits are separately provided. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed and is commonly connected only by a bonding pad connected to an external terminal for power input. 3. The semiconductor integrated circuit according to claim 1, wherein the power supply lines include a high potential side power supply line and a low potential side power supply line.