JPH11340805A - Timer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timer circuit capable of being used for measurement over a long time, without the use of an externally mounted capacitor and has less dispersion in its measurement time. SOLUTION: In this timer circuit that has a 1st transistor(TR) Q13, a 1st current source I5 supplying a constant current between a collector and an emitter of the 1st TR Q13, a resistor R1 provided between a base of the 1st TR Q13 and a constant level point, a 2nd TR Q1, a 2nd current source I1 supplying a constant current between a collector and an emitter of the 2nd TR Q1, a capacitor C1 provided between a base of the 2nd TR Q1 and the constant level point, and a comparison means that compares the charging voltage of the capacitor C1 with a voltage across the resistor for detecting that the size relation of the voltages is reversed, the 1st TR Q13 and the 2nd TR Q1 are formed on the same silicon substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for performing time control, such as a timer circuit and an oscillation circuit built in an IC.

[0002]

2. Description of the Related Art Conventionally, when an IC such as a timer circuit is used,
The area occupied by a capacitor in an IC is large, and particularly when a large-capacity capacitor is required, the area occupied is extremely large, and in many cases, an external capacitor must be used.

In a timer circuit which charges a capacitor with a constant current and measures the time based on the charging time, it is easy to implement a circuit capable of measuring a long time by using a capacitor built in the IC. Since there is a limit to the capacity value that can be obtained, it is necessary to generate a small current. At this time, the transistor had to be operated in a very small current region, and thus lacked stability. In order to prevent this, there has been a method in which a certain amount of current is applied to a transistor and a base current of the transistor is used as a charging current.

Japanese Utility Model Laid-Open No. 63-30027 discloses an example of a timer circuit in which an input bias current of a comparator is used as a constant current for charging a capacitor for the purpose of extending a timer time. FIG. 3 is a circuit diagram when the timer circuit is realized using the same comparator as that of the first embodiment of the present invention.

In the circuit shown in FIG. 3, the timer time T1 is calculated as follows: T1 = C1 × (Vref−VCEsatQ7) / (I1
/ HFEQ1). Here, VCEsatQ7: collector-emitter saturation voltage of Q7 hFEQ1: current amplification factor of Q1. In the above equation, circuit constants that can be easily realized inside the IC include: C1 = 100 pF, VCEsatQ7 = 0.1 V, I1
= 1 μA, hFEQ1 = 100, and when Vref = 2.1 V, the timer time T1 can be set to 20 msec, and the timer time can be lengthened.

[0006]

However, in this method, since the absolute error of the hFE of the transistor directly affects the timer time, the variation in the timer time is large. Absolute error of hFE of transistor is -50% to + 100%
Then, the error of the timer time T1 is also -50% to +100.
%.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and does not use an external capacitor.
Provided is a timer circuit which can measure for a long time and has a small variation in measurement time.

[0008]

According to a first aspect of the present invention, there is provided a first transistor, a first current source for flowing a constant current between a collector and an emitter of the first transistor, and the first transistor. A resistor provided between the base of the transistor and the constant potential point; a second transistor;
A second current source for flowing a constant current between the collector and the emitter of the transistor, a capacitor provided between the base of the second transistor and a constant potential point, a charging voltage of the capacitor and a voltage generated in the resistor. To the voltage
A timer circuit having comparison means for detecting that the magnitude relationship between these voltages has been reversed, wherein the first transistor and the second transistor are formed on the same silicon substrate.

The invention according to claim 2 is the timer circuit according to claim 1, wherein a plurality of the first transistors and a plurality of second transistors are provided.

According to a third aspect of the present invention, there is provided a comparator having a differential input stage composed of a bipolar transistor, a capacitor provided between one input of the differential input stage and a constant potential point, A resistor provided between the other input of the differential input stage and a constant potential point, a transistor having a base terminal connected to the resistor, and a current source for flowing a constant current between the collector and the emitter of the transistor And a timer circuit built in the IC.

The invention according to claim 4 is the timer circuit according to claim 3, wherein a plurality of the differential input stages and a plurality of transistors are provided.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention is as follows.
This will be described with reference to the circuit diagram inside the IC shown in FIG. Note that the elements described below are all elements provided inside the IC. Q1, Q2, Q10, Q11, Q12, Q in the figure
13 is a PNP transistor, Q3, Q4, Q5, Q6
Q7, Q8 and Q9 are NPN transistors. I1,
I2, I3, I4 and I5 are constant current sources. B1, B
2, B3 are buffer elements, C1 is a charging capacitor, and R1 is a resistor for generating a reference voltage. In addition, I1
I5 also indicates the current value supplied by these constant current sources with the same reference numerals. In addition, C1 and R1 have the same reference numerals and represent the capacitance value of the capacitor and the resistance value of the resistor.

CTL, Vref, VCC, GND, OU
T is a terminal provided on the IC. CTL is a control terminal, Vref is a constant voltage supply terminal, VCC is a power supply terminal, GND is a ground terminal, and OUT is an output terminal.

PNP transistors Q1, Q2, NPN transistors Q3, Q4, Q5, Q6, constant current sources I1, I
2, I3, I4 and the buffer element B3 constitute a PNP differential input comparator. The bases of Q1 and Q2 are the inputs of the comparator, and the output of B3 is the output of the comparator.

A capacitor C1 for charging the base current of Q1 is connected to the base of Q1, which is one input of the comparator. A resistor R1 for generating a reference voltage of the comparator is connected to the base of Q2, which is the other input of the comparator. further,
The base of a PNP transistor Q13 is connected to R1 to allow a base current to flow through R1. A current source I5 for supplying a constant current to Q13 is connected to the emitter of Q13. B which is the output of the comparator
The output of No. 3 is connected to the output terminal OUT of the IC.

The control terminal CTL is connected to the bases of NPN transistors Q7, Q8 via buffer elements B1, B2. The buffer elements B1 and B2 are for supplying a sufficient base current to Q7 and Q8. Q7 is for discharging the electric charge of the capacitor C1 and resetting the timer, and Q8 is for fixing the output of the comparator to the low level.

The NPN transistor Q9 and the PNP transistors Q10 and Q11 are circuits for providing a comparator with hysteresis. PNP transistor Q12
Is Q11 in the circuit for providing the hysteresis.
Are used to clamp the upper limit when charging the capacitor C1, and its emitter is connected to C1 and its base is connected to the constant voltage supply terminal Vref.

Next, the operation of the first embodiment will be described. Q
1 is lower than the base potential of Q2, Q1
And the emitter of Q2 are connected and at the same potential,
Becomes smaller than the base-emitter voltage of Q1, and Q2 turns off. Then Q2
Q3, which is connected in series with Q3, is also turned off, and Q4, which forms a current mirror with Q3, is also turned off. Then, the potential of the collector of Q4 increases, and the potential of the base of Q5 connected thereto also increases. Then, Q5 is turned on and the potential of the collector of Q5 falls, so that Q6 connected to the same point
The potential of the base also drops. Then, Q6 turns off,
The collector potential of Q6 rises and the output of the comparator becomes H
It becomes the high level. Conversely, when the base potential of Q1 is higher than the base potential of Q2, Q6 turns on, the collector potential of Q6 drops, and the output of the comparator goes low.

Q7 and Q8 are turned ON and OFF according to the potential level of the control terminal CTL. When the potential level of the CTL terminal is High, Q7 and Q8 are turned on. Q7 is ON
Then, the charge of the capacitor C1 connected to the collector of Q7 is discharged, and the timer is reset. Also, Q
8 turns ON, the output of the comparator turns ON / OFF of Q6.
It is fixed at the Low level irrespective of OFF.

When the potential level of the CTL terminal becomes low, Q7 and Q8 are turned off. When Q7 turns off, C
1 is ready for charging, and the timer starts counting. When Q8 is turned off, the output of the comparator is released from the fixed low level state, and Q6 is turned on / off.
The state is determined by OFF. However, CTL
Immediately after the terminal is set to Low, the charge of the capacitor C1 is discharged, and the base potential of Q1 is lower than the base potential of Q2. Then, since Q6 is turned off, the output of the comparator becomes High.

The base potentials of Q1 and Q2, which are input to the comparator, are determined as follows. When the potential level of the CTL terminal is High and Q7 is ON, the base potential of Q1 is the collector-emitter saturation voltage VC of Q7.
It becomes the same as EsatQ7. On the other hand, the base potential of Q2 is a voltage R1 × (I5 / hFEQ13) generated when the base current of Q13 flows through the resistor R1. Here, hFEQ13 is the current amplification factor of Q13. R
If 1 × (I5 / hFEQ13) is set higher than VCEsatQ7, Q6 turns off, but since Q8 controlled by the CTL terminal is on, the output level of this comparator becomes Low.

When the potential level of the CTL terminal is set to Low,
When Q7 is turned off, the base current of Q1 flows into the capacitor C1, so that the base potential of Q1 rises with time. At this time, Q8 is also turned off, so that the output of the comparator is in a state determined by Q6. CT
Immediately after the L terminal is changed from High to Low, Q6 is
FF is performed, and the output of the comparator becomes High.

The potential level of the CTL terminal is changed from High to L
Assuming that the time inverted to ow is zero, Q at time T
1 is ((I1 / hFEQ1) × T) / C
It becomes 1. Here, hFEQ1 is the current amplification factor of Q1. On the other hand, the base potential of Q2 is R1 regardless of time.
× (I5 / hFEQ13) Constant.

The base potential of Q1 ((I1 / hFE
Q1) × T) / C1 is the base potential of Q2, R1 ×
Q6 is OF while lower than (I5 / hFEQ13)
F and Q8 controlled by CTL terminal is also OFF
Therefore, the output level of the comparator becomes High. Over time, the base potential of Q1 rises,
Eventually, it exceeds the base potential of Q2. Then, Q6 is OF
The state changes from F to ON, and the output level changes from High to Low.
Flip to

Therefore, the CTL terminal is changed from High to Low.
The time required for the base potential of Q1 to reach the same potential as the base potential of Q2 from the time of inversion to the output terminal O
The UT can be detected as the time during which the UT is outputting the High level, and the detection time T1 is T1 = C1 × (R1 × (I5 / hFEQ13) −VCE
satQ7) / (I1 / hFEQ1).

When the base potential of Q1 exceeds the base potential of Q2, the collector current of Q11 suddenly flows into C1 by the action of Q9, Q10 and Q11, causing the base potential of Q1 to rise and causing a state transition immediately. determine. At this time, Q12 acts as an element that clamps the upper limit of the base potential of Q1. This is because if the base potential of Q1, that is, the charging voltage of C1 becomes too high, a large driving capability is required for Q7 or B1 when the charge of the capacitor C1 is discharged again in Q7 to reset the timer circuit. is there. Further, B3 functions as a buffer element for appropriately driving a circuit connected to the subsequent stage of the timer circuit.

In the above-mentioned timer circuit, by using the base current of the transistor as the charging current for the time measuring capacitor, it is possible to charge with a very small current, and the timer time can be lengthened. At the same time, a comparison constant voltage, which is the base potential of Q2, is generated by flowing the base current of transistor Q13 through resistor R1. Therefore, the error of the timer time due to the variation in the hFE of the transistor is only the relative error of the hFE of Q1 and Q13 since the hFE of Q1 and Q13 is in the denominator and the numerator when the calculation formula of the detection time T1 is referred to. At this time, VCEsatQ7 is R1 × (I5 / hFEQ1
Since it is minute compared to 3), it can be ignored. Here, since all the transistors are provided in the same IC, they are manufactured through the same process, and the relative error of hFE between each transistor is very small as compared with the absolute error. The error in the detection time T1 is also very small.

The upper limits of values that can be easily realized as circuit constants inside the IC are I1 = 1 μA, I5 = 1 mA, and C1 =
100 pF, R1 = 210 kΩ, hFEQ1 = 100,
hFEQ13 = 100, VCEsatQ7 = about 0.1 V, and at this time, T1 becomes 20 msec. Also,
The relative error of hFE between Q1 and Q9 is about ± 10%,
At this time, the error of T1 is also ± 10%.

Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment is a low-frequency oscillating circuit having a high-precision oscillating frequency utilizing charging and discharging of a capacitor provided inside an IC.

This oscillation circuit comprises constant current sources I10 and I2
0, capacitor C10, resistor R10, PNP transistors Q14, Q20, Q70, Q80, Q100, NPN
Transistors Q30, Q40, Q50, Q60, Q9
0, a constant voltage supply terminal Vref, a power supply terminal VCC, and a ground terminal GND. Where I10,
I20 represents a constant current source and also represents a current value supplied by these constant current sources. Also, C10 and R10 are
The capacitance value and the resistance value of these elements are also shown at the same time as expressing the capacitor and the resistance. Further, Vref represents a constant voltage supply terminal, and also represents a voltage applied to this terminal.

The transistors Q14 and Q20 form a differential input stage, and when one of the transistors is turned on, the other is turned off, depending on the level of the base potential of these transistors. The transistors Q50 and Q60 have a similar relationship. However, since Q14 and Q20 are PNP transistors, the one with a lower base potential is ON.
On the other hand, since Q50 and Q60 are NPN transistors, the transistor having a higher base potential is turned on. Furthermore, Q1
4 and Q50, and the bases of Q20 and Q60 are connected to each other. If the base potential of Q14 is lower than the base potential of Q20, the base potential of Q50 is lower than the base potential of Q60, and Q14 and Q60 are turned on. Then Q
20 and Q50 are turned off. Conversely, if the base potential of Q14 is higher than the base potential of Q20, Q14 and Q14
60 is turned off, and Q20 and Q50 are turned on.

When the base potential of Q14 is lower than the base potential of Q20, Q14 is turned on and Q50 is turned off, so that capacitor C10 is charged with the base current of Q14, and the potential of Q14 rises with time. On the other hand, Q6
0 is also turned on, so the Q connected in series with this Q60
70 is turned on, and Q80 forming a current mirror with this Q70 is also turned on. Then, Q100 connected in series to Q80 is also turned on. As a result, the resistor R10 has
Base current IBQ100 of PNP transistor Q100
And the base current IB of the NPN transistor Q60
Outflow of Q60 occurs. At this time, the inflow current IBQ10
The current ratio (n1) of the current mirror including the PNP transistors Q70 and Q80 is set in advance so that 0 becomes larger than the outflow current IBQ60. Then, the base potential of Q60, that is, the base potential of Q20 becomes a value obtained by adding R10 × (IBQ100−IBQ60) based on Vref.

When C10 is charged and the base potential of Q14 becomes higher than the base potential of Q20, Q14 becomes O
Since FF and Q50 are turned on, C10 is now set to Q50
Discharge at the base current of Then, the base potential of Q14 is reduced with time. On the other hand, Q20
Is also turned on, so that Q3 connected in series to this Q20
0 turns ON, and Q30 and Q constituting the current mirror
40 is also turned on. Then, the Q90 connected in series with the Q40 is also turned on. As a result, NP is added to the resistor R10.
Outflow of base current IBQ90 of N transistor Q90 and base current IBQ20 of PNP transistor Q20
Inflow occurs. At this time, the NPN transistor Q is set so that the outflow current IBQ90 becomes larger than the inflow current IBQ20.
Current ratio (n2) of current mirror consisting of 30, Q40
Is set in advance. Then, the base potential of Q60, that is, the base potential of Q20 becomes a value obtained by subtracting R10 × (IBQ90−IBQ20) with reference to Vref.

With the above setting, the potential of the upper terminal of the capacitor C10 becomes low potential Vref-R10 × (IBQ9
0-IBQ20) to high potential Vref + R10 × (IB
In the voltage range between Q100 and IBQ60), the oscillation circuit repeats charging with the base current IBQ14 of Q14 and discharging with the base current IBQ50 of Q50.

The second embodiment is an example in which the present invention is applied to an oscillation circuit. As in the first embodiment, the capacitor C10
A low frequency oscillation circuit is realized by using the base currents of the transistors Q14 and Q50 as the charge / discharge currents of the transistors Q14 and Q50. Further, by passing a current having a value equal to the difference between the base currents of the transistors Q90 and Q20 or the difference between the base currents of the transistors Q100 and Q60 to the resistor R10, two kinds of high and low reference voltages are generated. At this time, the oscillation frequency is determined by the ratio of the base currents of the transistors, as in the first embodiment. Therefore, the absolute error of hFE is canceled, and a high-precision low-frequency oscillation circuit can be realized.

[0036]

According to the present invention, there is provided a first transistor, a first current source for supplying a constant current between the collector and the emitter of the first transistor, and a connection between the base of the first transistor and a constant potential point. A resistor provided therebetween, a second transistor, a second current source for flowing a constant current between the collector and the emitter of the second transistor, and a resistor between a base of the second transistor and a constant potential point. And a comparing means for comparing the charging voltage of the capacitor with the voltage generated in the resistor, and detecting that the magnitude relationship between these voltages has been inverted. The second transistor is a timer circuit formed on the same silicon substrate.

That is, a reference voltage is generated by flowing a base current of the first transistor operating at a constant collector current to the resistor, and a base of the second transistor also operating at a constant collector current. The capacitor is charged and discharged using a current, and the comparing means compares the reference voltage with the charged voltage of the capacitor, and detects that the magnitude relationship between these voltages is inverted.

Therefore, the absolute variation in hFE of the transistor can be offset, and the timer time is not affected by the absolute variation in hFE. as a result,
Without using a large-capacity external capacitor, high-precision time measurement can be performed while performing long-time measurement using a capacitor provided inside the IC.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a timer circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an oscillation circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional timer circuit.

[Explanation of symbols]

Q1, Q2, Q10 to Q14, Q20, Q70, Q8
0, Q100 PNP transistors Q3 to Q9, Q30, Q40, Q50, Q60, Q90
NPN transistor I1 to I5, I10, I20 Constant current source B1 to B3 Buffer element C1, C10 Capacitor R1, R10 Resistance CTL Control terminal Vref Constant voltage supply terminal VCC Power supply terminal GND Ground terminal OUT Output terminal

Claims (4)

[Claims] 1. A first transistor, a first current source for flowing a constant current between a collector and an emitter of the first transistor, and a first current source provided between a base of the first transistor and a constant potential point. A second transistor, a second current source that allows a constant current to flow between the collector and the emitter of the second transistor, and a resistor between the base of the second transistor and a constant potential point. A capacitor for comparing a charging voltage of the capacitor with a voltage generated in the resistor, and detecting that the magnitude relationship between the voltages is inverted; and a first transistor and a second transistor, A timer circuit formed on the same silicon substrate. 2. The semiconductor device according to claim 1, wherein a plurality of said first transistors and a plurality of second transistors are provided.
2. The timer circuit according to 1. 3. A comparator having a differential input stage constituted by a bipolar transistor; a capacitor provided between one input of the differential input stage and a constant potential point; It is characterized by having a resistor provided between one input and a constant potential point, a transistor having a base terminal connected to the resistor, and a current source for flowing a constant current between the collector and the emitter of the transistor. A timer circuit built into an IC that performs 4. The timer circuit according to claim 3, wherein a plurality of differential input stages and transistors are provided.