JPH03145217A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To speed up rise and fall of an output terminal by devising the circuit such that a charge current or a discharge current of a capacitor is increased by turning-on a transistor(TR). CONSTITUTION:A charge/discharge circuit 5 for a capacitor C1 for oscillation prevention is provided newly. The charge/discharge circuit 5 consists of PNP TRs Q11, Q12, the base of the TR Q11 is connected to a base of a TR Q2, the collector is connected to the collector of a TR Q5, and the emitter is connected to the base of a TR Q3, respectively. Moreover, the base of the TR Q12 is connected to the emitter of a TR Q6, the collector connects to the collector of the TR Q6, and the emitter is connected to the base of a TR Q11 respectively. When a difference voltage between input terminals 1, 2 is larger than the base- emitter voltage VBE11(VBE12) of the TR Q11(Q12), the TR Q11(Q12) is turned on to speed up charge/discharge of the capacitor C1. Thus, quick rise and fall of an output terminal 4 is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit, and, for example, to a differential amplifier circuit provided at the output stage of an AD converter.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional differential amplifier circuit that is provided at the output stage of an AD converter and serves as a buffer amplifier. In the figure, Ql is an input stage PNP transistor, whose base is connected to input terminal 1, emitter is connected to the base of transistor Q2, and is connected to power supply vCC via constant current source 11, and collector is connected to GND.
It is connected to the. Dl is a diode, and its cathode and anode are connected to the emitter and the base of the transistor Ql, respectively. The input terminal 1 is given the output of the AD converter.

Q2. Q3 is a PNP transistor forming a differential pair. The emitters of transistors Q and Q3 are commonly connected, and this common connection point is connected to a power supply V via a constant current source I2. Connected to 0. Q4 is a PNP transistor in the input stage, the base of which is connected to the input terminal 2, the emitter of which is connected to the base of the transistor Q3, and the constant current source 13.
The collector is connected to the power supply VCC via the VCC, and the collector is connected to GND. D2 is a diode whose cathode and anode are connected to the emitter of the transistor 04' and the input terminal 2, respectively.

Q5. Q6 is an NPN transistor forming a current mirror circuit. The bases of transistors Q and QB are commonly connected. The collector of transistor Q2 is connected to the collector of transistor Q2, and the emitter is connected to GND. The transistor QB has its collector connected to the collector of the transistor Q3, its emitter connected to GND, and its base and collector connected in common.

3 is an output buffer circuit, and C1 is a capacitor for preventing oscillation. The output buffer circuit 3 is an NPN transistor Q
, Q , Q 5PNP transfer 8 9 Getter Q Resistor R1 Consists of diodes D, D for level shift, and constant current source I4. The transistor Q7 has a base connected to the collector of the transistor Q2, a collector connected to the power supply VCC, and an emitter connected to GND via the resistor Rt. Transistor Q8 has a base connected to the emitter of transistor Q7, and an emitter connected to GN.
D has a collector connected to a series circuit consisting of diodes D and D4, a constant current source, and a power source V. The capacitors C for oscillation prevention are connected between the base of the transistor Q7 and the collector of the transistor Q8, and the collector output of the transistor Q2 given through the base of the four transistors Q7 is connected to the capacitor C for preventing oscillation. , and prevents the output from the output terminal 4 from oscillating. The transistor Q9 is an output stage transistor, and has a base connected to a common connection point between the anode of the diode D3 and the constant current source I4, a collector connected to the power supply VCC, and an emitter connected to the output terminal 4. The transistor Qlo is also an output stage transistor, and has a base connected to the collector of the transistor Q8, an emitter connected to the output terminal 4, and a collector connected to GND. Note that the input terminal 2 and the output terminal 4 are short-circuited or connected via a feedback circuit, and the input terminal 2
It is assumed that the voltage follows the voltage at the output terminal 4.

Next, the operation will be explained. If the input terminals 1.2 and 2 are equally stable, the collector current 'C2 of the transistor Q and the collector current I of the transistor Q3.

3 will be equal. On the other hand, when the input voltages at input terminals 1 and 2 are no longer equal, the base-emitter voltage V of transistor Q and T2 B
62 transistor Q3 base-emitter voltage v B1
0, a potential difference ΔvBE (-VBE2-vBE3) occurs. In such a state, transistor Q2.
Collector current ratio I of Q3. 2/IC3 is determined by the following formula.

IC2”V~1ε...(1)C3v: Transistor thermal voltage Now, input terminal 1
When the voltage of V becomes lower than the voltage of input terminal 2, V
>V. In this case, BF2 8E3 ΔVBE is positive, and ΔVBE/VT>o. Therefore, from equation (1), it becomes IC3''C2.Transistor Q
, Q6 constitute a current mirror circuit. The collector current 2C5 of the transistor Q5 is determined by the collector current 2C6 of the transistor Q6. Also, 'CB=I
Since C3 becomes 'C5='C3, the capacitor C is charged by the difference current of IC2'C5, 'C2' and C3. When the charging voltage of the capacitor c1 becomes larger than the sum of the base-emitter voltage V of the transistor Q7 and the base-emitter voltage V of the transistor Q8 due to charging of the capacitor CI, the transistors E8 and Q are turned on and a constant current is generated. The current from source 4 passes through diodes D, D and transistor Q8 and exits to GND. Then, transistor Q9 is turned off, while transistor Q1o is turned on. Therefore, the potential of the output terminal 4 decreases, and the potential of the input terminal 2 also decreases, so that the potentials of the input terminals 1 and 2 become equal.

On the other hand, when the voltage at the input terminal 1 becomes higher than the voltage at the input terminal 2, v becomes smaller than v. In this case, BF2 8
E3 ΔV becomes negative, and ΔvBE/vT becomes 0. Therefore, from equation (1), Ic3>Ic2, and capacitor C1 is I. It is discharged by a differential current of 3-IC2.

When the charging voltage of capacitor C1 becomes smaller than V + V due to discharge of capacitor C, BE7 8E
8 The transistors Q and Q are turned off, and the current of the constant current source 4 flows into the bases of the transistors Q and Q1o. Then, transistor Q9 is turned on, while transistor Q1o is turned off. Therefore, the potential of the output terminal 4 increases, and the potential of the input terminal 2 also increases, so that the potentials of the input terminals 1 and 2 become equal.

[Problem to be solved by the invention]

In the conventional differential amplifier, the charging and discharging of the oscillation prevention capacitor C1 is done by the collector current of the transistor Q2! . 2 and the collector current of transistor Q! . Since this can be carried out only with a differential current of 3, it takes time to charge and discharge the transistor CI, and there is a problem that the rise and fall of the output are delayed as shown in FIG. As a solution to this problem, constant current source ■2
It may be possible to shorten the charging/discharging time of the capacitor C1 and make the fall and rise of the output faster by increasing the amount of current ■ to increase the difference between the collector current 1°2 and 'C3. However, if the current amount I2 of constant current source ■2 is increased, the current flowing through the entire circuit (circuit current) increases, and the transfer conductance given by ■/2vT increases, leading to an increase in oscillation. .

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a differential amplifier whose output can quickly fall and rise without increasing the circuit current.

[Means to solve the problem]

The differential amplifier according to the present invention has first and second input terminals, an output terminal, and a first conductivity type having a control electrode connected to the first input terminal and one electrode connected to a first potential. a first transistor, a second transistor of a first conductivity type whose control electrode is connected to a second input terminal and whose one electrode is connected to one electrode of the first transistor, and which constitutes a differential pair together with the first transistor;
a second transistor, one electrode of which is connected to the other electrode of the first transistor, and the other electrode of which is connected to a second potential.
a third transistor of conductivity type, a control electrode is connected to the control electrode of the third transistor, one electrode is connected to its own control electrode and also connected to the other electrode of the second transistor, and the other electrode is connected to the control electrode of the third transistor; connected to a second potential;
A fourth transistor of the second conductivity type constitutes a current mirror circuit together with the transistor; A fifth transistor of the first conductivity type is connected to the control electrode of the transistor, the control electrode is connected to the other electrode of the fifth transistor, one electrode is connected to one electrode of the fourth transistor, and the other electrode is connected to the fifth transistor. A sixth transistor of the first conductivity type is connected to the control electrode of the transistor, and a sixth transistor of the first conductivity type is connected to one electrode of the third transistor. A capacitor is charged and discharged according to the level difference of an input signal to a second input terminal, a control electrode is connected to the capacitor, one electrode is connected to the first potential, and the other electrode is connected to the output terminal, and the charging voltage of the capacitor is a seventh transistor of a second conductivity type that is turned on/off in accordance with the
The control W1 pole is connected to the capacitor, one electrode is connected to the output terminal, and the other electrode is connected to the second potential, and the seventh transistor is turned on/off with the opposite polarity to the on/off of the seventh transistor depending on the charging voltage of the capacitor. and an eighth transistor of the first conductivity type.

[Effect]

The fifth transistor in this invention turns on when the voltage at the second input terminal becomes higher than the voltage at the first input terminal by a predetermined value, and supplies current to the collector of the third transistor. The collector current of the third transistor is
The fourth transistor constitutes a current mirror together with the transistor
Since the fifth transistor is regulated by the collector current of the transistor, the current caused by turning on the fifth transistor becomes the charging current of the capacitor, and the charging current of the capacitor increases accordingly. On the other hand, the sixth transistor turns on when the voltage at the first input terminal becomes higher than the voltage at the second input terminal by a predetermined value, and supplies current to the collector of the fourth transistor. Then, the collector current of the third transistor, which together with the fourth transistor constitutes a current mirror circuit, increases.

This increased current becomes a discharge current of the capacitor, and the discharge current of the capacitor increases accordingly.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a differential amplifier circuit according to the present invention. In the figure, the difference from the conventional example shown in FIG.
This is a new feature.

The charge/discharge circuit 5 includes PNP) transistors Q1□, Q1□
Consists of. The transistor Qll has a base connected to the base of the transistor Q2, a collector connected to the collector of the transistor Q5, and an emitter connected to the base of the transistor Q3. The transistor Q12 has a base connected to the emitter of the transistor Qll, and a collector connected to the emitter of the transistor Qll.
The collector and emitter of B are connected to the base of transistor Q11, respectively. Other configurations are the same as before.

Next, the operation will be explained. When the voltages at the input terminals 1.2 are equal, the potentials of the base and emitter of each transistor Q11''12 are equal, and these transistors are turned off.Therefore, as in the conventional case, the voltage is 1 -1, and the capacitor C1 is not charged or discharged. C2C3 does not change, the potential at the output terminal 4 does not change, and the potential at the input terminal 1°2 remains equally stable.

Next, a case where the stable state is broken and the voltage at the input terminal 1 becomes higher than the voltage at the input terminal 2 in a stepwise manner as shown in FIG. 2 will be described. In this case, the voltage difference between the input terminal 1 and the input terminal 2 becomes larger than the base-emitter voltage vBE12 of the transistor Q1□ constituting the charge/discharge circuit 5, so the transistor Q12 is turned on. When the transistor Q12 is turned on, the collector current 1C6 of the transistor QB forming the current mirror circuit increases. As a result, the collector current of transistor Q5 C5
increases. In other words, the discharge current of the capacitor C1 increases compared to the conventional case, and the discharge time of the capacitor C1 becomes shorter than the conventional case. Therefore, the charging voltage of the capacitor C1 becomes smaller than 7+vBE8 earlier than in the conventional case, and the transistors Q7 and Q8 are turned off earlier. Therefore, as shown in FIG. 2, the voltage at the output terminal 4 rises quickly. As the voltage at the output terminal 4 increases, the voltage at the input terminal 2 also increases. When the voltage difference between input terminal 1 and input terminal 2 becomes smaller than the base-emitter voltage V of transistor Q12, transistor E1
2 Q1□ is turned off and the capacitor C is
1 is discharged. Therefore, the change in the rise of the voltage at the output terminal 4 has a slope with steps as shown in FIG. Thereafter, the voltage at the input terminal 2 increases and when it becomes equal to the voltage at the input terminal 1, the capacitor C1 no longer discharges and a stable state is reached.

Next, a case where the stable state is broken and the voltage at input terminal 1 becomes lower than the voltage at input terminal 2 in a stepwise manner as shown in FIG. 2 will be described. In this case, the voltage difference between input terminal 1 and input terminal 2 is determined by the voltage difference between transistor Q1. Since the voltage V between the base and emitter of the transformer EII becomes larger than the voltage V, the transistor Q turns on. When transistor Qll turns ON1, transistor Q which constitutes a current mirror circuit
The current supplied to the collector of 5 increases.

On the other hand, the collector current IC5 of the transistor Q5 is the collector current l of the transistor Q. is regulated to be equal to 6. Therefore, the current increased by turning on the transistor Q11 is applied to the capacitor CI as a charging current. As a result, the charging time for capacitor C1 becomes shorter. Therefore, the charging voltage of the capacitor C becomes larger than <■BE7+V earlier than before, and the transistors Q7°E8 and Q8 turn on earlier. Therefore, as shown in FIG. 2, the voltage at the output terminal 4 falls quickly. As the voltage at the output terminal 4 decreases, the voltage at the input terminal 2 also decreases. Then, when the voltage difference between the input terminals 1 and 2 becomes smaller than the base-emitter voltage V of the transistor Qll, the transistor EII Q1□ is turned off, and the capacitor C1 is charged by the same operation as the conventional one. Therefore, the fall of the voltage at the output terminal 4 has a slope with steps as shown in FIG. Thereafter, when the voltage at the input terminal 2 decreases and becomes equal to the voltage at the input terminal 1, the capacitor C1 is no longer charged and a stable state is reached. As described above, when the differential voltage between input terminals 1 and 2 becomes larger than the base-emitter type 11' 12 voltage V or V of the transistor QQ, the BEI
I BE12 Transistor Q or Q12 is turned on to speed up the charging and discharging of C1, so the output terminal 4
rises faster.

Note that the level shifting diodes D 1 and D 2 shown in the above embodiments are not necessarily provided.

4. It is also possible to construct a similar circuit by using the transistors and diodes shown in the above embodiments with opposite conductivity types, and in this case also, the same effects as in the above embodiments can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the control electrode is connected to the control electrode of the first transistor, the one electrode is connected to one electrode of the third transistor, and the other electrode is connected to the control electrode of the second transistor. a fifth transistor of the first conductivity type, a control electrode connected to the other electrode of the fifth transistor, one electrode connected to one electrode of the fourth transistor, and the other electrode connected to the control electrode of the fifth transistor. A sixth transistor of the first conductivity type is provided, and when the voltage at the second input terminal becomes higher than the voltage at the first input terminal by a predetermined value, the fifth transistor is turned on, and the collector current of the first transistor is turned on. When the voltage at the first input terminal is higher than the voltage at the second input terminal by a predetermined value, the sixth transistor is turned on and the current is supplied to the collector of the third transistor. Since the current is supplied to the collector of the fourth transistor by adding it to the collector current of The discharge current of the capacitor increases.

As a result, the charging and discharging time of the capacitor becomes faster, and the output rises and falls faster.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the differential amplifier circuit according to the present invention, FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional differential amplifier circuit. a circuit diagram showing the circuit;
FIG. 4 is a diagram for explaining the operation of the circuit shown in FIG. 3. In the figure, 1 and 2 are input terminals, 4 is an output terminal, Q,
Q, Q Q and Q12 are PNP 2 3
10' 11 transistors, Q, Q and Q9 are NPN transistors. Note that the same reference numerals in each figure indicate the same or corresponding parts. 1st Figure 4: Output terminal Q2. Q3. Q+o, Qn Q12: PNP transistor Qs, Qs, Qs: NPNh transistor diagram

Claims (1)

[Claims] (1) first and second input terminals, an output terminal, and a first transistor of a first conductivity type, each of which has a control electrode connected to the first input terminal and one electrode connected to a first potential. , a control electrode is connected to the second input terminal, and one electrode is connected to the first input terminal.
a second transistor of a first conductivity type connected to one electrode of the transistor and forming a differential pair together with the first transistor; one electrode connected to the other electrode of the first transistor, and the other electrode connected to the second transistor; a third transistor of a second conductivity type, each of which has a control electrode connected to the control electrode of the third transistor, and one electrode of which is connected to the control electrode of the second transistor; a fourth transistor of a second conductivity type, the other electrode of which is connected to the second potential, and which constitutes a current mirror circuit together with the third transistor; and a control electrode of which is connected to the first transistor. a fifth transistor of a first conductivity type, with one electrode connected to one electrode of the third transistor and the other electrode connected to the control electrode of the second transistor; a sixth transistor of a first conductivity type, one electrode of which is connected to the other electrode of the fifth transistor, one electrode of which is connected to one electrode of the fourth transistor, and the other electrode of which is connected to the control electrode of the fifth transistor; a capacitor connected to one electrode of the transistor No. 3 and charged and discharged according to the level difference between input signals to the first and second input terminals; a control electrode connected to the capacitor, and one electrode connected to the first potential; a seventh transistor of a second conductivity type, the other electrode of which is connected to the output terminal, and which is turned on/off depending on the charging voltage of the capacitor; a control electrode of which is connected to the capacitor; and one electrode of which is connected to the output terminal. , an eighth transistor of a first conductivity type, the other electrode of which is connected to the second potential, and which is turned on/off in a polarity opposite to that of the seventh transistor in accordance with the charging voltage of the capacitor; A differential amplifier circuit with