JPS5831614A - Triangle wave oscillator - Google Patents

Triangle wave oscillator

Info

Publication number
JPS5831614A
JPS5831614A JP56129371A JP12937181A JPS5831614A JP S5831614 A JPS5831614 A JP S5831614A JP 56129371 A JP56129371 A JP 56129371A JP 12937181 A JP12937181 A JP 12937181A JP S5831614 A JPS5831614 A JP S5831614A
Authority
JP
Japan
Prior art keywords
capacitor
transistors
transistor
potential
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56129371A
Other languages
Japanese (ja)
Other versions
JPS6410134B2 (en
Inventor
Toshihiko Ichise
俊彦 市瀬
Kiyoshi Hashimoto
清 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56129371A priority Critical patent/JPS5831614A/en
Publication of JPS5831614A publication Critical patent/JPS5831614A/en
Publication of JPS6410134B2 publication Critical patent/JPS6410134B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K4/00Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06Generating pulses having essentially a finite slope or stepped portions having triangular shape

Landscapes

  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

PURPOSE:To set potentials of upper and lower limit of a triangle wave to a desired value, by performing charge/discharge of a capacitor and determining both said potentials with a potential given externally. CONSTITUTION:Three transistors(TR) with arranged characteristics, 1, 2 and 3 are connected for common emitter and grounded via a constant current circuit 12. An emitter of TRs 4, 5 and 6 with opposite polarity as the TRs 1, 2 and 3 is connected to each base of the TRs 1, 2 and 3. The base of the TR4 is connected to a charge/discharge terminal of a capacitor 15, the base of the TRs 5, 6 is connected to a voltage source having equal voltages as desired minimum and maximum charging voltages Vmin and Vmax of the capacitor 15 respectively. A short-circuiting circuit of the capacitor 15 consisting of TRs 7 and 8 is connected to the TR6. A switch 20 is provided to the capacitor 15, and the potential of the upper and lower limit of a triangle wave can be set to a desired value, by changing over the switch 20 to the discharge position at the Vmax and to the charging position at the Vmin.

Description

【発明の詳細な説明】 本発明は、三角波の上限電位および下限電位を外部から
与えられる電位によシ定められ°るようにすることによ
って、三角波の上限電位および下限電位を所望の電位に
設定することができる三角波発振器を提供するものであ
る。
Detailed Description of the Invention The present invention sets the upper and lower limit potentials of the triangular wave to desired potentials by determining the upper and lower limit potentials of the triangular wave by externally applied potentials. The present invention provides a triangular wave oscillator that can perform

第1図は、本−発明の−実施例の構成を示した回路図で
、1ないし3は特性がそろっているNPN型のトランジ
スタ、4ないし7はPNP型のトランジスタ、8はNP
N型のトランジスタ、9ないし14は定電流回路、15
はコンデンサ、16. 17は抵抗器、18は三角波の
上限電位を設定する高電位信号が入力する高電位入力端
子、19は三角波の下限電位を設定する低電位信号が入
力する低電位入力端子、20はトランジスタ7のコレク
タ電流の有無に従って一端がアースされたコンデンサ1
5の他端を端子AまたはBK切シ換える、半導体素子に
よって構成されるスイッチ、 21は三角波を出力する
出力端子、22は電源である0ことで、トランジスタ1
々いし6を第1図に示したように接続し、トランジスタ
1,2および3のエミツタの電位をトランジスタ4,5
および6(入力段トランジスタ)の入力電位V・v−鞠
およびV−の3つの電位のうちで最も高い電位にするこ
とによりて、その最も高い電位に係るトランジスタ11
ないし301つだけが導通状態になり他の2つが非導通
状態となるような3入力回路が構成される0次に、以上
のように構成された本実施例の動作図に示した点aにお
ける電圧を示したタイムチャートであり、vrIMl!
およびvrninはそれぞれ高電位入力端子18および
低電位入力端子19に入力している信号の電位を示して
いる。また、第2図(b)ないしくf)はそれぞれ第1
図に示した点すないしfを流れる電流を示したタイムチ
ャートである。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, in which 1 to 3 are NPN type transistors with the same characteristics, 4 to 7 are PNP type transistors, and 8 is an NP type transistor.
N-type transistors, 9 to 14 are constant current circuits, 15
is a capacitor, 16. 17 is a resistor; 18 is a high potential input terminal to which a high potential signal for setting the upper limit potential of the triangular wave is input; 19 is a low potential input terminal to which a low potential signal for setting the lower limit potential of the triangular wave is input; 20 is the transistor 7; Capacitor 1 with one end grounded according to the presence or absence of collector current
A switch composed of a semiconductor element switches the other end of 5 to terminal A or BK, 21 is an output terminal that outputs a triangular wave, and 22 is a power supply.
The emitters of transistors 1, 2 and 3 are connected to each other as shown in FIG.
and 6 (input stage transistor) by setting the input potential to the highest potential among the three potentials V, V- and V-, and the transistor 11 related to the highest potential.
A three-input circuit is constructed in which only one input is in a conductive state and the other two are in a non-conductive state. Next, at point a shown in the operation diagram of this embodiment configured as described above, This is a time chart showing the voltage, vrIMl!
and vrnin indicate the potentials of the signals input to the high potential input terminal 18 and the low potential input terminal 19, respectively. In addition, Fig. 2(b) to f) are respectively the first
3 is a time chart showing the current flowing through points 1 to 3 shown in the figure.

先ず、スイッチ20が端子Bと接続している状態では、
コンデ/す15は定電流回路9の定電流により充電され
て、出力端子21の電位Vは第2図(a)K示したよう
に上昇する。このような状態においては、トランジスタ
3が導通状態になっており(第2図(d))、)ランジ
スタ1および2はそれぞれエミッタ電位がペース電位よ
りも高くなっていて第2図缶)および(e)に示したよ
うに非導通状態になっている。そして、出力端子21の
電位Vが高電位入力端子18の電位vrIIaXに達す
ると、トランジスタ1が導通状mKなる。このため、ト
ランジスタ1のコレクタに電流が流れて、トランジスタ
7および8が導通状態となり(第2図(e)および(f
))、トランジスタ3が第2図(d)に示したように非
導通状態になるとともに、スイッチ20が端子1Bから
端子Aに切り換ってコンデンサ15は定電流回路10を
通して放電をし始める。コンデンサ515の放電が進む
につれて、出力端子21の電位Vは第2図(&)K示し
たように下降する。このようなコ、ンデンサ15の放電
期間においては、トランジスタ7および8が導通状態に
なりているために、トランジスタ3は非導通状態になっ
ている。そして、出力端子21の電位Vが下降して低電
位入力端子19の電位v2に達すると、トランジスタ2
が第2図(e)に示したように導通状態になってトラン
ジス月が非導通状態になる。このために、iランジスタ
フおよびBが第一回(e)および(f)に示したように
非導通状態となりスイッチ20が端子Aから端子Bに切
り換ってコンデンサ15が充電し始められるとともに、
トランジスタ3が第2WJ(イ)K示したように導通状
態になってトランジスタ2力(非導通状態になる(第2
図(c) )。
First, when switch 20 is connected to terminal B,
The capacitor 15 is charged by the constant current of the constant current circuit 9, and the potential V of the output terminal 21 rises as shown in FIG. 2(a)K. In this state, the transistor 3 is in a conductive state (Fig. 2(d)), and the emitter potential of the transistors 1 and 2 is higher than the pace potential, respectively, and the transistors 1 and 2 are in a conductive state (Fig. As shown in e), it is in a non-conducting state. Then, when the potential V of the output terminal 21 reaches the potential vrIIaX of the high potential input terminal 18, the transistor 1 becomes conductive mK. Therefore, a current flows to the collector of transistor 1, and transistors 7 and 8 become conductive (Fig. 2(e) and (f).
)), the transistor 3 becomes non-conductive as shown in FIG. 2(d), the switch 20 switches from the terminal 1B to the terminal A, and the capacitor 15 begins to discharge through the constant current circuit 10. As the discharge of the capacitor 515 progresses, the potential V of the output terminal 21 decreases as shown in FIG. During such a discharge period of capacitor 15, transistors 7 and 8 are in a conductive state, and therefore transistor 3 is in a non-conductive state. Then, when the potential V of the output terminal 21 falls and reaches the potential v2 of the low potential input terminal 19, the transistor 2
becomes conductive as shown in FIG. 2(e), and the transistor becomes non-conductive. For this reason, as shown in the first steps (e) and (f), iRangistaph and B become non-conductive, the switch 20 switches from terminal A to terminal B, and the capacitor 15 begins to charge.
Transistor 3 becomes conductive as shown in the second WJ(a)K, and transistor 2 becomes non-conductive (second
Figure (c)).

以上のようにして、コンデンサ15は充放電を繰返えす
ため、出力端子21からは第2図(a)に示したような
上限電位−8、)下限電位vminの三角波が出力され
る。ここで1本実施例においては、コンデンサ15の充
放電が定電流回路9および10を介して行なわれるため
に、出力された三角波の発振局波数はvl−v2に比例
する。
As described above, since the capacitor 15 is repeatedly charged and discharged, a triangular wave having an upper limit potential of -8 and a lower limit potential vmin as shown in FIG. 2(a) is output from the output terminal 21. In this embodiment, since the capacitor 15 is charged and discharged via the constant current circuits 9 and 10, the oscillation local wave number of the output triangular wave is proportional to vl-v2.

以上説明したように本発明によれば、三角波の1上限電
位および下限電位を外部から電位を与えることKよって
所望の電位に設定することがセきるという利点がある。
As described above, the present invention has the advantage that the upper and lower limit potentials of the triangular wave can be set to desired potentials by applying potentials from outside.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成を示す回路図、第2図
は第1図に示した各点における電圧または電流を示した
タイムチャートである。 1、2.3.8・・・・・・・・・NPN型トランジス
タ、 4,5゜6.7  ・・・・・・・・・PNP 
型トランジスタ、  9ないし14、・・・・・・・・
・定電流回路、 15・・・・・・・・・コンデンサ、
16.17・・・・・・・・・抵抗器、 18・・・・
・・・・・高電位入力端子。 19・・・・・・・・・低電位入力端子、20・・・・
・・・−・スイッチ、21・・・・・・・・・出力端子
、 ”mtLK・・・・・・・・・高電位入力端子め電
位s  ■min・・・・・・・・・低電位入力端子の
電位、■・・・・・・・・・出力端子の電位。 特許出願人 松下電器産業株式会社 第1図 第2図
FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing voltages or currents at each point shown in FIG. 1, 2.3.8......NPN type transistor, 4,5゜6.7......PNP
type transistor, 9 to 14,...
・Constant current circuit, 15... Capacitor,
16.17...Resistor, 18...
...High potential input terminal. 19...Low potential input terminal, 20...
・・・−・Switch, 21・・・・・・Output terminal, “mtLK・・・・・・High potential input terminal potential s ■min・・・・・・・・・Low Potential of potential input terminal, ■・・・・・・・・・ Potential of output terminal. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)  特性のそろった第1.第2、第3の3個の同
極性トランジスタを互いに並列に且つそれらのエミッタ
を共通に接続し、第1.館2、第3の各トランジスタの
各ベースには第1ないし第3のトランジスタとそれぞれ
逆極性の第4.@5、第6のトランジスタの各エミッタ
をそれぞれ接続し、第4ないし第6のトランジスタの1
つのベースは、スイッチを介して充放電されるコンデン
サの充放電側端子に、他の2つのトランジスタの各ベー
スを前記コンデンサの所望の最低充電電圧vml。およ
に印加されている前記トランジスタK11i記コンテン
サの放電時にこのトランジスタの出力回路が短絡される
ように第7のトランジスタを接続し、前 。 記コンデンサの充電電圧がVnaxに達したときそれに
連動して前記スイッチを放電側に切換えるとと4に第7
0)ランジスタを導通させ、前記コンデンサの充電電圧
がvminに達したとき前記スイッチを充電側に切換え
るとともに第7のトランジスタを゛遮断するよう構成し
、出力がvmlnおよびvm&xの間で変化するよう構
成したことを特徴とする三角波発振器。
(1) The first type with the same characteristics. The second and third three transistors of the same polarity are connected in parallel with each other and their emitters are commonly connected. At the bases of each of the second and third transistors, there is a fourth transistor having a polarity opposite to that of the first to third transistors. @ Connect the emitters of the 5th and 6th transistors, and connect the 1st emitter of the 4th to 6th transistors.
One base is connected to the charging/discharging side terminal of the capacitor which is charged and discharged through a switch, and each base of the other two transistors is connected to the desired minimum charging voltage vml of the capacitor. The seventh transistor is connected in such a way that the output circuit of this transistor is short-circuited when the capacitor K11i is discharged. 4. When the charging voltage of the capacitor reaches Vnax, the switch is switched to the discharging side.
0) The transistor is made conductive, and when the charging voltage of the capacitor reaches vmin, the switch is switched to the charging side and the seventh transistor is turned off, so that the output changes between vmln and vm&x. A triangular wave oscillator characterized by:
(2)  第1ないし第6のトランジスタの各エミッタ
およびコンデンサの充電回路並びに放電回路ににはそれ
ぞれ定電流回路を直列に接続したことを特徴とする特許
請求の範囲第(1)項記載の三角波発振器。
(2) A triangular wave according to claim (1), characterized in that a constant current circuit is connected in series to each of the emitters of the first to sixth transistors and the charging circuit and discharging circuit of the capacitor. oscillator.
JP56129371A 1981-08-20 1981-08-20 Triangle wave oscillator Granted JPS5831614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56129371A JPS5831614A (en) 1981-08-20 1981-08-20 Triangle wave oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56129371A JPS5831614A (en) 1981-08-20 1981-08-20 Triangle wave oscillator

Publications (2)

Publication Number Publication Date
JPS5831614A true JPS5831614A (en) 1983-02-24
JPS6410134B2 JPS6410134B2 (en) 1989-02-21

Family

ID=15007921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56129371A Granted JPS5831614A (en) 1981-08-20 1981-08-20 Triangle wave oscillator

Country Status (1)

Country Link
JP (1) JPS5831614A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170493A (en) * 1984-02-11 1985-09-03 Taitetsuku:Kk Controller for capacitor-run type induction motor
JPS60170495A (en) * 1984-02-11 1985-09-03 Taitetsuku:Kk Position correcting system for induction motor drive device
EP0200011A1 (en) 1985-03-30 1986-11-05 Fuji Photo Film Co., Ltd. Heat-developable light-sensitive material
JPH01105375A (en) * 1987-10-16 1989-04-21 Omron Tateisi Electron Co Card reader provided with punching mechanism

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48102960A (en) * 1972-04-06 1973-12-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48102960A (en) * 1972-04-06 1973-12-24

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170493A (en) * 1984-02-11 1985-09-03 Taitetsuku:Kk Controller for capacitor-run type induction motor
JPS60170495A (en) * 1984-02-11 1985-09-03 Taitetsuku:Kk Position correcting system for induction motor drive device
EP0200011A1 (en) 1985-03-30 1986-11-05 Fuji Photo Film Co., Ltd. Heat-developable light-sensitive material
JPH01105375A (en) * 1987-10-16 1989-04-21 Omron Tateisi Electron Co Card reader provided with punching mechanism

Also Published As

Publication number Publication date
JPS6410134B2 (en) 1989-02-21

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