JP2796866B2 - Charge pump circuit - Google Patents

Description

The present invention relates to a terminal voltage of a capacitor as an oscillation control voltage applied to a voltage controlled oscillator in response to a control signal output from a phase comparator or the like in a PLL circuit. More particularly, the present invention relates to a charge pump circuit that surely stops charging and discharging of a capacitor when the charge pump circuit is turned off.

(Prior Art) FIG. 5 is a circuit diagram of an example of a conventional charge pump circuit that can be turned off. In FIG. 5, the output terminal 2 of the phase comparator 1 is connected via a resistor 3 to the bases of two NPN and PNP transistors 4 and 5 which are combined in a complementary manner on the input side. And one NPN transistor 4
Is connected to the power supply V via a resistor 6, and the collector of the other PNP transistor 5 is grounded via a resistor 7. Further, resistors 8 and 9 are interposed in series between the power supply V and the ground, and the connection points are connected to the emitters of the transistors 4 and 5, respectively. Further, two transistors 10, 11 of PNP and NPN combined in a complementary manner on the output side are interposed in series between the power supply V and the ground. Then, the collector of the transistor 4 is connected to the base of the transistor 10,
The collector of the transistor 5 is connected to the base of the transistor 11, respectively. Further, the connected collectors of the transistors 10 and 11 are connected to the input terminal 13 of the voltage controlled oscillator 12, and are grounded via a resistor 14 and a capacitor 15 in series.

Further, a PN is connected between the emitter and the base of the transistor 10.
A P transistor 16 is interposed, a resistor 17 is interposed between the emitter and base of the transistor 16, and the base is grounded via a resistor 18 and an NPN transistor 19 in series. Also, between the base of the transistor 11 and the ground
An NPN transistor 20 is interposed. Further, the bases of the transistors 19 and 20 are connected to the charge pump control signal input terminal 23 via the resistors 21 and 22, respectively.

In such a configuration, if the charge pump control signal applied to the charge pump control signal input terminal 23 is at “L” level, the transistors 19 and 20 are off and the transistor 16
Is also OFF. Therefore, if the control signal voltage output from the phase comparator 1 is higher than the reference voltage formed by the divided voltages by the resistors 8 and 9, one of the input-side complementary transistors is turned on and the other transistor is turned on. 5 is OFF.
Along with this, one of the complementary transistors on the output side
10 turns on, the other transistor 11 turns off, the charging current flows from the power supply V into the capacitor 15, and the oscillation control voltage applied to the input terminal 13 of the voltage controlled oscillator 12 increases. If the control signal voltage output from the phase comparator 1 is lower than the reference voltage, one transistor 4 on the input side is turned off and the other transistor 5 is turned on.
As a result, one transistor 10 on the output side is turned off.
And the other transistor 11 turns on, and the capacitor 15
Is discharged via the transistor 11, and the oscillation control voltage applied to the input terminal 13 of the voltage controlled oscillator 12 decreases.

When the charge pump control signal is at “H” level, the transistors 19 and 20 are turned on, and the transistor 16 is also turned on.
N. Therefore, the voltage between the base and the emitter of the transistors 10 and 11 on the output side is limited to the potential difference between the collector and the emitter of the transistors 16 and 20, and even if one of the transistors 4 and 5 on the input side is turned on. Transistors 10, 11
Are both kept OFF. As a result, charging and discharging of the capacitor 15 are stopped.

In this way, by turning off the charge pump circuit, the charge of the capacitor 15 is maintained as it is, and when the power supply to the PLL circuit is turned off once and then turned on again, the lock-up time can be reduced, and the charge to the capacitor 15 can be reduced. The useless power consumption of the charging current is eliminated.

(Problems to be Solved by the Invention) When the conventional charge pump circuit is turned off, the charge pump control signal must be set to “H” level and all of the transistors 16, 19, and 20 must be turned on. The power consumed by the transistors 16, 19, and 20 is wasted.
In this OFF state, the voltage between the base and the emitter of the complementary transistors 10 and 11 on the output side becomes the transistor 1
The voltage effect between the emitter and the collector of 6,20 is added, the OFF of the transistors 10 and 11 becomes uncertain, and there is a problem that the capacitor 10 is easily charged / discharged slightly.

The present invention has been made in view of the circumstances of the conventional charge pump circuit as described above, and provides a charge pump in which charging and discharging of a capacitor are reliably stopped when the charge pump circuit is OFF and power is not wasted. With the goal.

(Means for Solving the Problems) In order to achieve the above object, a charge pump circuit according to the present invention comprises two input-side complementary transistors according to the magnitude of a control signal voltage with respect to a reference voltage. One of which is turned on and the other is turned off. According to the on and off of these transistors, the other two transistors combined in the complementary type on the output side are turned on and the other is turned off to charge and discharge the capacitor. In the pump circuit, ON / O with the first resistor and the charge pump control signal
The switching element and the second resistor are sequentially connected in series to the FF, and the first and second switching elements are turned on when the switching element is ON.
The reference voltage is formed by a divided voltage by the resistance of the capacitor, and when the switching element is OFF, the two transistors on the input side are both turned OFF to turn off the two transistors on the output side, so that the two transistors on the output side are both turned OFF. It is configured to stop charging and discharging of electric charge.

(Operation) When the switching element is turned off by the charge pump control signal, the two complementary transistors on the input side are both turned off.
As a result, the complementary transistor on the output side is also reliably turned off, and charging and discharging of the capacitor are reliably stopped. Then, no current flows through the resistor for forming the reference voltage and any of the transistors,
There is no wasteful power consumption.

(Example) Hereinafter, an example of the present invention will be described with reference to FIG.
FIG. 1 is a circuit diagram of one embodiment of the charge pump circuit of the present invention. In FIG. 1, the same circuit elements as those in FIG. 5 are denoted by the same reference numerals.

In FIG. 1, an output terminal 2 of a phase comparator 1 is connected to two transistors NPN and PNP on the input side via a resistor 3.
Are connected to the bases, respectively. The bases of these transistors 4 and 5 are connected to a power supply V via a resistor 30 and grounded via a resistor 31. The emitters of the transistors 4 and 5 are connected via an NPN transistor 32 as a switching element. The emitter of one transistor 4 is connected to a power source V via a first resistor 8 and the emitter of the other transistor 5 Are grounded via the second resistor 9. And further, transistor 32
Is connected to the charge pump control signal input terminal 23 via the resistor 33. If the transistor 32 is ON, the two transistors 4 and 5 on the input side are combined in a complementary manner.

Further, the collector of the transistor 4 is connected to the power supply V via the PNP transistor 34 and to the base of the transistor 34. The collector of the transistor 5 is grounded via an NPN transistor 35, and is connected to the base of the transistor 35. Then, between the power supply V and the ground, two transistors 10, 11 of the PNP and NPN combined in a complementary manner on the output side are interposed in series, and the connected collector of these transistors 10, 11 is controlled by voltage. Connected to the input terminal 13 of the oscillator 12 and grounded via a resistor 14 and a capacitor 15 in series. Further, the base of one transistor 10 is connected to the base of transistor 34, and these two transistors 10, 34 form a constant current circuit. Similarly, the base of the other transistor 11 is
Of these two transistors 11,3
5 forms a constant current circuit.

In such a configuration, if the charge pump control signal applied to the charge pump control signal input terminal 23 is at “H” level, the transistor 32 is turned on, and the resistance between the emitters of the input transistors 4 and 5 and the resistances 8 and 9 are electrically connected. Connected, resistance 8,
The reference voltage is formed by the nine divided voltages. And
If the control signal voltage output from the phase comparator 1 is higher than this reference voltage, one transistor 4 is turned on and the other transistor 5 is turned off. Accordingly, transistors 10 and 34 are turned on, and transistors 11 and 35 are turned on.
Is turned off, the charging current flows from the power supply V into the capacitor 15, and the oscillation control voltage applied to the input terminal 13 of the voltage controlled oscillator 12 increases. If the control signal voltage output from the phase comparator 1 is lower than the reference voltage, one transistor 4 on the input side is turned off and the other transistor 5 is turned on. Along with this, transistors 10,34
Is turned off, the transistors 11 and 35 are turned on, the charge of the capacitor 15 is discharged via the transistor 11, and the oscillation control voltage applied to the input terminal 13 of the voltage controlled oscillator 12 decreases. Here, the value of the current flowing through the transistors 34 and 35 is defined by the resistor 8 or 9 and
If 5 and 11 are closely integrated, transistors 10 and 11
Is proportional to the current flowing through the transistors 34 and 35, and the capacitor 15 is charged and discharged by the constant current.

By the way, if the charge pump control signal is at the “L” level, the transistor 32 is turned off. Then, the voltage of the power supply V is applied to the emitter of one transistor 4 on the input side, the emitter of the other transistor 5 is at the ground voltage, and both transistors 4 and 5 are turned off. For this reason, the transistors 10 and 11 on the output side are both turned off, and charging and discharging of the capacitor 15 are stopped.

Here, when the charge pump circuit is OFF, all the transistors 4, 5, 10, 11, 34, and 35 are OFF, and there is no unnecessary power consumption. Moreover, transistors 10 and 11 are surely off
Therefore, the charging and discharging of the capacitor 15 is reliably stopped.

FIG. 2 is a circuit diagram of another embodiment of the charge pump circuit of the present invention. 2, the same circuit elements as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 2, the output terminal 2 of the phase comparator 1 is connected via a resistor 3 to the emitters of two NPN and PNP transistors 40 and 41 which are combined in a complementary manner on the input side. The base of one transistor 40 is grounded via the resistor 9, and the base of the other transistor 41 is connected to the power supply V via the resistor 8. Further, an NPN transistor 32 is interposed between the bases of these two transistors 40 and 41. Further, the collector of one transistor 40 is connected to the collector and base of transistor 34 and the base of transistor 10, and the collector of the other transistor 41 is connected to the collector and base of transistor 35 and the base of transistor 11.

In such a configuration, if the charge pump control signal applied to the charge pump control signal input terminal is at “H” level, the transistor 32 is turned on, and the input-side transistor
The resistors 8, 9 are electrically connected between the bases 40, 41 and the resistors 8, 9
A reference voltage is formed by the divided voltage. If the control signal voltage output from the phase comparator 1 is higher than the reference voltage, one transistor 40 is turned off and the other transistor 41 is turned on. In conjunction with this,
Transistors 10 and 34 turn off and transistors 11 and 35 turn on
Then, the charge of the capacitor 15 is discharged through the transistor 11, and the oscillation control voltage applied to the input terminal 13 of the voltage controlled oscillator 12 decreases. If the control voltage output from the phase comparator 1 is lower than the reference voltage, one transistor 40 is turned on and the other transistor 41 is turned off.
Becomes As a result, the transistors 10 and 34 are turned on, the transistors 11 and 35 are turned off, the charging current flows from the power supply V to the capacitor 15, and the oscillation control voltage applied to the input terminal of the voltage controlled oscillator 12 increases. I do.

When the charge pump control signal is at the “L” level, the transistor 32 is turned off. Then, the base of one transistor 40 is at the ground voltage, the base of the other transistor 41 is applied with the voltage of the power supply V, and the two transistors 40 and 41 are both turned off. Accordingly, the transistors 10 and 11 on the output side are also turned off, and charging and discharging of the capacitor 15 are stopped.

Here, in the embodiment shown in FIG. 2, similarly to the embodiment shown in FIG. 1, when the charge pump circuit is OFF, all the transistors 10, 11, 32, 34, 35, 40 and 41 are OFF. Therefore, there is no unnecessary power consumption, and the charging and discharging of the capacitor 15 is reliably stopped.

FIGS. 3 and 4 show a circuit in which the charge pump circuit of the present invention is applied so that the charging and discharging of the capacitor can be switched between a high speed and a steady speed. If used for a PLL circuit, the lock-up time of the PLL circuit can be shortened, and after the lock-up is completed, the response speed of the oscillation control voltage of the voltage controlled oscillator can be appropriately set, which is useful. Third
FIG. 4 is a circuit diagram of an application example of a charge pump circuit capable of switching a charge / discharge speed of a capacitor, and FIG. 4 is a diagram showing a charge speed of a capacitor of FIG. In FIG. 3, two sets of circuits from two transistors 4, 5 on the input side and two transistors 10 and 11 on the output side in FIG. 1 are connected in parallel. The circuit elements corresponding to those in FIG. 1 are denoted by the same reference numerals with a and b added thereto, and redundant description will be omitted.

In FIG. 3, the output terminal 2 of the phase comparator 1 is connected via a resistor 3 to the bases of two pairs of transistors 4 _a , 5 _a , 4 _b , 5 _b combined in a complementary manner on the input side. Is done. A connection point between two sets of transistors 10 _a , 11 _a , 10 _b , and 11 _b combined in a complementary manner on the output side is connected to the input terminal 13 of the voltage controlled oscillator 12, and a resistor 14 and a capacitor
15 is grounded in series. Further, the resistances _8a and _9a and the resistances _8b and _9b are set to have different resistance values. Also, the charge pump control signal input terminal 23 _a, 23 _b are separately and independently provided.

In such a configuration, the charge pump control signal input terminal charge pump control signals applied to the 23 _a, 23 _b is "H" level or "L" level, the transistor 4 _a of the corresponding input side, 5 _a or 4 _b, 5 _b Are ON / OFF controlled in the same manner as the circuit shown in FIG.

By the way, assuming that the resistances of the resistors 8 _b and 9 _b are larger than the resistors 8 _a and 9 _a , the current flowing through the transistors 10 _a and 11 _a is larger than the current flowing through the transistors 10 _b and 11 _b . Therefore, when the PLL circuit is activated and locked up, the charge pump control signal of the “H” level is applied to one of the charge pump control signal input terminals 23 _a having _a large charge current to the capacitor 15, so that the fourth state is obtained. As shown by the solid line in the figure, the charging voltage of the capacitor 15 rises sharply, and the lock-up time can be shortened. Then, after the lock-up completion, if giving the "H" level charge pump signal to the other of the charge pump control signal input terminal 23 _b, fourth
As shown by the broken line in the figure, the capacitor 15 is slowly charged and discharged, and an appropriate response speed can be obtained.

In the embodiment shown in FIG. 3, at the time of lock-up, both charge pump control signal input terminals _23a , 23
_b , an “H” level charge pump control signal is applied to both the transistors 15 _a , 11 _a , 10 _b , and 11 _b on the output side to charge and discharge the capacitor 15 steeply. Alternatively, a charge pump control signal of “H” level may be applied to one of the charge pump control input terminals 23 _a and 23 _b , and an “L” level may be applied to the other.

(Effect of the Invention) Since the charge pump circuit of the present invention is configured as described above, the following effects can be obtained.

When the charge pump circuit is OFF, all the transistors constituting the circuit are OFF, and no current flows through the resistor for forming the reference voltage, so that power is not wasted. Therefore, as shown in FIG. 3, even when a plurality of sets of circuits from two transistors combined in the complementary type on the input side to two transistors combined in the complementary type on the output side are connected in parallel, the power consumption is reduced. No problems occur. In addition, when the capacitor is OFF, the transistor that controls charging and discharging of the capacitor is surely OFF, and there is no danger of current leakage or the like.Therefore, charging and discharging of the capacitor are reliably stopped, and the terminal voltage of the capacitor is extended. Can hold time. Further, in the charge pump circuit of the present invention, the number of transistors for the circuit configuration is smaller than that of the conventional circuit, the circuit structure is simpler, the circuit can be manufactured at low cost, and it is suitable for mass production.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the charge pump circuit of the present invention, FIG. 2 is a circuit diagram of another embodiment of the charge pump circuit of the present invention, and FIG. FIG. 4 is a circuit diagram of an application example in which the charge / discharge of a capacitor can be switched between a high speed and a steady speed by applying the charge pump circuit of FIG. FIG. 5 is a circuit diagram showing an example of a conventional charge pump circuit which can be turned off. 1: phase _{comparator, 4,5,4 a, 5 a, 4} b, 5 b, 40,41: transistors combined in a complementary input _{side, 8,9,8 a, 9 a, 8} b, 9 _b : resistance forming reference voltage, 10,11,10 _a , 11 _a , 10 _b , 11 _b : output side complementary transistor, 15: capacitor, 23,23 _a , 23 _b : charge pump control signal input terminal, 32,32 _a, 32 _b: charge pump control signal in ON / OFF transistors.

Claims (1)

(57) [Claims] 1. One of two input-side complementary transistors is turned on and the other is turned off according to the magnitude of a control signal voltage with respect to a reference voltage, and the other is turned off. In a charge pump circuit that charges and discharges a capacitor by turning on one and turning off the other of two other transistors combined in a complementary manner on the side, the transistor is turned on by a first resistor and a charge pump control signal.
A switching element to be turned off and a second resistor are sequentially connected in series, and the reference voltage is formed by a divided voltage by the first and second resistors when the switching element is turned on, and the switching element is turned off. A charge pump circuit configured to turn off the two transistors on the input side at the time of turning off the two transistors on the output side to stop charging and discharging of the capacitor. .