JPH0119472Y2 - - Google Patents

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Publication number
JPH0119472Y2
JPH0119472Y2 JP17767180U JP17767180U JPH0119472Y2 JP H0119472 Y2 JPH0119472 Y2 JP H0119472Y2 JP 17767180 U JP17767180 U JP 17767180U JP 17767180 U JP17767180 U JP 17767180U JP H0119472 Y2 JPH0119472 Y2 JP H0119472Y2
Authority
JP
Japan
Prior art keywords
speed
voltage
switch
resistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17767180U
Other languages
Japanese (ja)
Other versions
JPS57100329U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17767180U priority Critical patent/JPH0119472Y2/ja
Publication of JPS57100329U publication Critical patent/JPS57100329U/ja
Application granted granted Critical
Publication of JPH0119472Y2 publication Critical patent/JPH0119472Y2/ja
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 この考案は、高速高圧パルス発生回路におい
て、高速スイツチとして用いるスイツチング素子
の高速性を損うことなく出力インピーダンスを下
げ、かつスイツチング素子を破壊から守る高速高
圧パルス発生回路に関する。
[Detailed description of the invention] This invention relates to a high-speed high-voltage pulse generation circuit that lowers the output impedance without impairing the high-speed performance of the switching element used as a high-speed switch in the high-speed high-voltage pulse generation circuit, and protects the switching element from destruction. .

従来、高速高圧パルスを発生させる回路とし
て、第1図に示すような高圧電源HVに抵抗R1
スイツチSWの直列回路を接続し、その中間の出
力点OUTから出力を取り出すものが用いられて
きている。すなわち、スイツチSWがオフ状態の
時、出力点OUTには高圧電源HVからの高電圧
が高抵抗R1を介して現われる。スイツチSWをオ
ン状態にすると、高電圧はアースと短絡状態にな
り、出力点OUTもアースと同電位になる。この
回路のスイツチSWにアバランシエトランジスタ
列等の高速高圧スイツチを用いると、高電圧で高
速の電圧ステツプ(パルス)が得られる。
Conventionally, as a circuit for generating high-speed high-voltage pulses, a circuit has been used that connects a series circuit of a resistor R1 and a switch SW to a high-voltage power supply HV, as shown in Figure 1, and takes out the output from an intermediate output point OUT. ing. That is, when the switch SW is in the off state, a high voltage from the high voltage power supply HV appears at the output point OUT via the high resistance R1 . When the switch SW is turned on, the high voltage is shorted to earth, and the output point OUT is also at the same potential as earth. If a high-speed, high-voltage switch such as an avalanche transistor array is used as the switch SW in this circuit, a high-speed voltage step (pulse) can be obtained at high voltage.

しかし、高速スイツチSWがオフ状態の時のイ
ンピーダンスは抵抗R1によつて決まるので非常
に高く、電圧が不安定となつてしまう。従つてイ
ンピーダンスを下げるためには、第2図に示すよ
うに並列にコンデンサCを接続しなければならな
いが、この回路では高速スイツチSWのオン状態
の時にはコンデンサCの放電電流が高速スイツチ
SWに流れてしまうことになる。この放電電流は
高速スイツチSWが高速であればあるほど大きな
ものとなり、従来の第2図のような回路でスイツ
チSWとして高速スイツチング素子を用いると、
この高速スイツチング素子の寿命が著しく短かく
なつてしまう。この現象は上述した放電電流のピ
ーク値が大きくなりすぎるのが原因であることが
実験の結果明らかになつたが、第3図に示すよう
にスイツチSWに流れる電流を制限するために単
に抵抗R2を直列に接続しただけでは、出力点
OUTに現われる電圧はコンデンサCと抵抗R2
よつて決定される時定数を持つているため、スイ
ツチSWの高速性が著しく損なわれてしまうこと
になる。
However, when the high speed switch SW is in the off state, the impedance is determined by the resistor R1 and is therefore very high, making the voltage unstable. Therefore, in order to lower the impedance, a capacitor C must be connected in parallel as shown in Figure 2, but in this circuit, when the high-speed switch SW is on, the discharge current of the capacitor C is equal to that of the high-speed switch SW.
It will flow to SW. The higher the speed of the high-speed switch SW, the larger this discharge current becomes.If a high-speed switching element is used as the switch SW in the conventional circuit shown in Fig. 2,
The life of this high-speed switching element is significantly shortened. Experiments revealed that this phenomenon was caused by the peak value of the discharge current becoming too large, but as shown in Figure 3, the resistor R was simply used to limit the current flowing through the switch SW. If you just connect 2 in series, the output point
Since the voltage appearing at OUT has a time constant determined by capacitor C and resistor R2 , the high speed performance of the switch SW will be significantly impaired.

この考案は以上のような点に鑑み、出力インピ
ーダンスを下げ、かつ高速のスイツチを安定に長
寿命で使用できるようにした高速高圧パルス発生
回路を提供するものである。
In view of the above points, this invention provides a high-speed, high-voltage pulse generation circuit that lowers the output impedance and allows high-speed switches to be used stably and with a long life.

第4図はこの考案の原理図を示したもので、抵
抗R1とスイツチSWが直列接続され、コンデンサ
Cが並列接続された回路に、このコンデンサCと
抵抗R3を直列に挿入接続したものである。この
ように構成し抵抗R3の値を適当な値に選べば、
出力点OUTから見たインピーダンスはスイツチ
SWがオフ状態でも抵抗R1一個の場合よりも大幅
に小さくすることができる。そして、スイツチが
オン状態の時では抵抗R3にコンデンサCの放電
電流が流れることによる電圧降下は出力点OUT
には現われず、出力点OUTの電圧はスイツチ
SWの内部抵抗を無視すれば直ちに零になる。し
かも、スイツチSWがオン状態になつた時に流れ
る電流は抵抗R3により制限されるので、スイツ
チSWに用いられる高速スイツチング素子がピー
ク電流で破壊されることはない。
Figure 4 shows the principle of this invention, in which capacitor C and resistor R 3 are inserted and connected in series in a circuit in which resistor R 1 and switch SW are connected in series, and capacitor C is connected in parallel. It is. If you configure it like this and choose the value of resistor R 3 to an appropriate value,
The impedance seen from the output point OUT is the switch
Even when SW is off, it can be made much smaller than when only one resistor R is used. When the switch is on, the voltage drop due to the discharge current of capacitor C flowing through resistor R3 is at the output point OUT.
does not appear on the switch, and the voltage at the output point OUT does not appear on the switch.
If the internal resistance of SW is ignored, it immediately becomes zero. Moreover, since the current that flows when the switch SW is turned on is limited by the resistor R3 , the high-speed switching element used in the switch SW will not be destroyed by the peak current.

次に、この考案の一実施例について説明する。
第5図は第4図の原理図に実際に負荷Lを接続し
た回路図であり、第6図は出力点OUTの電圧変
化の特性図である。負荷Lには高圧パルス以外に
他からの擾乱が加わつているために、パルス源の
インピーダンスが高いと非常に大きな変動が出力
点OUTに出てくるが、この考案のように構成す
ると第6図の特性図からもも明らかなように、時
点Aにおいては外部からの擾乱が入つているがそ
の大きさは実用上問題はないほど小さく、しかも
スイツチSWが動作を開始する時点Bの直前には
元通りの電圧まで回復していることがわかる。
Next, one embodiment of this invention will be described.
FIG. 5 is a circuit diagram in which a load L is actually connected to the principle diagram of FIG. 4, and FIG. 6 is a characteristic diagram of voltage change at the output point OUT. Since the load L is affected by disturbances from other sources in addition to high-voltage pulses, if the impedance of the pulse source is high, a very large fluctuation will appear at the output point OUT. As is clear from the characteristic diagram, there is an external disturbance at time A, but its magnitude is so small that it poses no practical problem, and furthermore, just before time B, when the switch SW starts operating, there is an external disturbance. It can be seen that the voltage has recovered to its original level.

以上のように、この考案は抵抗の接続箇所を工
夫しただけで、高速電圧パルス発生回路の高速性
を維持でき、しかもスイツチとして用いるスイツ
チング素子を破壊から防止できるので、その実用
効果は大である。
As described above, this idea has great practical effects because it is possible to maintain the high-speed performance of the high-speed voltage pulse generation circuit by simply changing the connection points of the resistors, and it also prevents the switching elements used as switches from being destroyed. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の高速性パルス発生回路図、第
2,3図はその改良図、第4図はこの考案の原理
的回路図、第5図はこの考案の一実施例の回路
図、第6図は第5図の特性図である。 図において、HVは高圧電源、SWはスイツチ、
Cはコンデンサ、R1,R2,R3は抵抗、Lは負荷
を示す。
Figure 1 is a diagram of a conventional high-speed pulse generation circuit, Figures 2 and 3 are improved diagrams thereof, Figure 4 is a principle circuit diagram of this invention, Figure 5 is a circuit diagram of an embodiment of this invention, and Figure 5 is a circuit diagram of an embodiment of this invention. FIG. 6 is a characteristic diagram of FIG. In the figure, HV is a high voltage power supply, SW is a switch,
C is a capacitor, R 1 , R 2 , R 3 are resistors, and L is a load.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高圧電源と、抵抗と、高圧電源からの高電圧を
電流の減少とともにオフに回復する自己回復性の
高速スイツチとを直列に接続し、上記抵抗と上記
高速スイツチの中間より高速高圧パルスを発生せ
しめる高速高圧パルス発生回路において、電圧を
安定化させるために電圧安定用コンデンサーと、
電流制限用抵抗との直列回路を上記高速スイツチ
に並列に接続したことを特徴とする高速高圧パル
ス発生回路。
A high-voltage power supply, a resistor, and a self-recovery high-speed switch that turns off the high voltage from the high-voltage power supply as the current decreases are connected in series, and a high-speed high-voltage pulse is generated between the resistor and the high-speed switch. In high-speed high-voltage pulse generation circuits, voltage stabilization capacitors and
A high-speed, high-voltage pulse generation circuit characterized in that a series circuit with a current-limiting resistor is connected in parallel to the above-mentioned high-speed switch.
JP17767180U 1980-12-11 1980-12-11 Expired JPH0119472Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17767180U JPH0119472Y2 (en) 1980-12-11 1980-12-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17767180U JPH0119472Y2 (en) 1980-12-11 1980-12-11

Publications (2)

Publication Number Publication Date
JPS57100329U JPS57100329U (en) 1982-06-21
JPH0119472Y2 true JPH0119472Y2 (en) 1989-06-06

Family

ID=29971767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17767180U Expired JPH0119472Y2 (en) 1980-12-11 1980-12-11

Country Status (1)

Country Link
JP (1) JPH0119472Y2 (en)

Also Published As

Publication number Publication date
JPS57100329U (en) 1982-06-21

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