JPH0219651B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level conversion circuit used when driving an ECL circuit with the output of a TTL circuit.

The input circuit is TTL (Transistor
Logic) system, and the internal circuit driven by this is
In circuit systems such as ECL (Emitter Coupled Logic), the TTL level is generally determined from the earth (ground) side, but because the ECL level is determined from the positive side, it is difficult to directly determine the TTL level.
It has become inappropriate to drive the ECL circuit with the output of the circuit, so a level conversion circuit is interposed between the two.

FIG. 1 is a diagram showing an example of this type of level conversion circuit, where 1 is an input circuit (TTL circuit), 2 is a level conversion circuit, and 3 is an internal circuit (ECL circuit). Input circuit 1 shows a part of the output stage and the terminal
A TTL level output signal is supplied to V _IN , and this becomes the input to the level conversion circuit 2. R ₀ is resistance,
C ₀ is the stray capacitance of the external circuit. The level conversion circuit 2 connects a resistor R ₁ and diodes D ₂ to _{D 5} in series between a power supply Vc.c.
_A diode D 1 _is connected between the connection point A of the resistor R ₁ and the diode D ₂ , which is the input point of It has become a thing. The internal circuit 3 mainly includes a pair of emitter-coupled transistors T ₁ and T ₂ , and resistors R ₂ and R ₃ are connected between the collectors of the transistors T ₁ and T ₂ and the power supply Vc.c. is connected, and a resistor _R4 is connected between the commonly connected emitter and the earth.

In the above configuration, when the terminal V _IN is "H" at TTL level, the potential at point A is the forward voltage of diodes D ₂ to _{D 5} because diode D ₁ is off, and at this time, the base of transistor T ₂ Potential (reference potential)
If V _R is set lower than the forward voltage,
Transistor T ₁ is on and transistor T ₂ is off. Conversely, when terminal V _IN is "L" at TTL level, diode D ₁ is turned on and diodes D ₂ to D ₅ are turned off, so the potential at point A is the same as the terminal.
regulated by the potential of V _IN , transistor T ₁
turns off and transistor _T2 turns on, respectively.

A problem with such a level conversion circuit is the response speed when the level of the terminal V _IN is inverted from "L" to "H". In other words, the rate of potential rise at point A is regulated by the charging time constant τ ₀ for the stray capacitance C ₁ through the resistor R ₁ (or the external stray capacitance C ₀ through the diode D ₁ at the stage of switching off). Therefore, the time constant τ ₀ can be reduced by reducing the resistance R ₁ , but the resistance value of the resistance R ₁ is determined by the following equation based on the circuit conditions.

R ₁ = Vc.c. - (V _BE + V _IN )/I _IL In this formula, Vc.c. is the power supply voltage mentioned above, V _IN is the voltage of the terminal V _IN mentioned above, and V _BE is the order of diode D ₁ . The directional voltage I _IL is the current that flows out through the terminal V _IN when the terminal V _IN is at “L” level.
Since I _IL cannot be set too large from a driving point of view, the resistance value of resistor R ₁ should be increased (for example, tens of thousands [K
Ω〕) Must be set.

As a result, in the conventional level conversion circuit shown in FIG. 1, the response speed cannot be increased particularly when the input V _IN is inverted from "L" to "H".

The present invention has been made to improve the above-mentioned problems, and an object of the present invention is to provide a level conversion circuit that can increase the response speed by reducing the resistance _R1 without increasing the current _IL .

Hereinafter, one embodiment of the present invention will be described based on FIG. Note that the same parts in FIG. 2 as in FIG. 1 are given the same reference numerals. The main difference between the level conversion circuit 2' of this embodiment and that of FIG. 1 is that the power supply Vc.c.
In this example, the collector-emitter path of the emitter follower transistor T ₃ is interposed between R ₁ and the emitter follower transistor T ₃ , and the base of the transistor T 3 is higher than the input potential in the ECL circuit 3 and changes high and low levels accordingly. Now, transistor T ₂ of ECL circuit 3
This is the point connected to collector output point B of .

The operation of the level conversion circuit configured as described above will be explained. First, when the terminal V _IN is at the "H" level, the diode _D1 is off and the potential at point A is determined by the forward voltage of the diodes _D2 to _D5 , and the transistor _T1 is turned on as in Figure 1. in transistor
T ₂ is in the off state. In this state, the potential of the collector (point B) of transistor _T2 is high, so
The potential of the emitter (point C) of the emitter follower transistor _T3 is also high (potential at point B _minus transistor V _BE ). On the other hand, when the terminal V _IN is at the “L” level, the diode D ₁ is turned on and the diodes D ₂ to _{D 5} are turned off, so the potential at point A is the _same as the potential at the terminal V _IN . The forward voltage V _BE drops to plus the transistor T ₁
is off and transistor _T2 is on.
In this state, since the potential at point B is low, the potential at point C is also low. Specifically, when the potential at point B in a low potential state is V _BL and the potential at point C at this time is V _CL , V _CL =V _BL -V _BE . Therefore, if we put V _CL in place of Vc.c. in the previous equation, it becomes clear that the same _IL
For that, R ₁ can be small.

Here, the level of terminal V _IN changes from “L” to “H”
Considering that it is reversed to , in its initial state,
First, the stray capacitance C ₀ is charged by the current flowing into V _IN from the TTL circuit. Then diode D ₁
is turned off and the potential at terminal V _IN becomes higher than the potential at point A, current is supplied through transistor T ₃ and resistor R ₁ and charging of stray capacitance C ₁ begins. Therefore, the potential at point A rises, and during this time the transistor
When T ₁ starts to turn on and transistor T ₂ starts to turn off, the potential at point B increases. This results in an emitter follower transistor with its base connected to point B.
The current supplied to _C1 increases due to _T3 , and the potential at point A rises rapidly.Thus, the response speed to the level change from "L" to "H" decreases the resistance value of resistor _R1 . The synergistic effect of reducing the charging time constant τ ₀ and the feedback operation by the transistor T ₃ results in extremely high speed.

In the embodiment, the diodes _D2 to _D5 constitute a constant voltage source at "H" level, but this may also be realized by a Zener diode, a transistor circuit, or the like. Further, the control signal for the base potential of the emitter follower transistor T ₃ may be one that inverts the collector potential of the transistor T ₁ of the ECL circuit 3. Furthermore, the configuration of the ECL circuit 3 is not limited to the basic configuration of the embodiment, and may be any suitable current switch circuit.

In the level conversion circuit of the present invention described above,
When the input TTL level is “L”, the power supply side potential of resistor _R1 is lower than the power supply voltage Vc.c.
Even if the resistance value of R ₁ is decreased, the current _IL flowing out from the terminal V _IN does not increase, and the charging time constant τ ₀ is reduced to allow the input level to change from "L" to "H" quickly. The internal ECL circuit can be driven at high speed in response to

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional level conversion circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1...Input circuit (TTL circuit), 2'...Level conversion circuit, 3...Internal circuit (ECL circuit), D ₁ to D ₅
...Diode, R ₁ to R ₄ ... Resistor, C ₀ , C ₁ ...
Stray capacitance, T ₁ to T ₃ ...transistor, V _R ...reference voltage.

Claims (1)

[Claims] 1 In a level conversion circuit that matches the output level of the TTL circuit to the input level of the ECL circuit, the emitter follower transistor, resistor, and constant voltage source are connected in series between the power supply and the ground, and the input terminal of the ECL circuit is A diode is connected between the connection point between the connected resistor and the constant voltage source and the output end of the TTL circuit, and the base of the transistor is higher than and the same as the input potential in the ECL circuit. A level conversion circuit characterized by being connected to a point where high and low levels change.