JPH01259618A - Window circuit - Google Patents

Abstract

PURPOSE:To narrow a window width by a simple means and to obtain a window circuit capable of extremely low voltage operation by using the emitter area ratios of transistors for the threshold level of each discrimination circuit. CONSTITUTION:As upper limit and lower limit setting circuits 11 and 12 to detect a first set potential in the direction of the increase of an input voltage and a second potential in the direction of its decrease respectively, the transistors whose emitter area ratios are different are combined in parallel in each circuit and the outputs of large-area transistors Q1 and Q3 are given to the output nodes of small-area transistors Q2 and Q4 by a current mirror circuit. Output circuits having a common load circuit are connected respectively to the output nodes of the small-area transistors Q2 and Q4. Thus, the window width can be narrowed by the simple means and the extremely low voltage operation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a window circuit that is effective as a center detection circuit for the detection output (figure 8 curve characteristic) of, for example, an FM tuner.

(Prior Art) For example, there is a circuit as shown in FIG. 3 as a window circuit. In this circuit, the emitters of transistors Q31 and Q32 are connected in series, and a common base has a reference voltage Vref.
Then, the FM detection output voltage Vin is supplied. The FM detection output voltage Vin is a voltage that changes approximately in proportion to the input frequency. The collector of transistor Q31 is the load resistor R.
[connected to the power supply line through the transistor Q32
The collector of is connected to a current mirror circuit CUR made up of transistors Q33 and Q34. The output current of the current mirror circuit CUR is configured to flow through the collector of the transistor Q34 and the load resistor RL.

This circuit functions to cancel muting when the FM detection output voltage Vin falls within a predetermined range and the input frequency of the FM detection circuit (not shown) falls within a predetermined range.

The current voltage Vin is gradually rising from 0 to NPN l~
Base-emitter voltage V at which transistor Q31 turns on
When be(Ql) is turned ON, transistor Q31 causes a collector current Ic(Ql) to flow through load resistor R1, and the voltage Vin gradually decreases, resulting in a base-emitter voltage Vbe (PNP) which turns on transistor Q32. (
Q2) When turned ON, the same current I c (Q4) as the collector current I c (Q2) of the transistor Q32 flows through the load resistor R[ by the operation of the current mirror circuit CUR. Next, V be(Ql)ON< V in< V be[Q2
) ON range, transistors Q31. Q32 is cut off, and no current flows through the load resistor R.

In other words, the window width Vin-w of the above window circuit is V in-w = V be (Ql) ON - V be (
Q2) It turns on.

vbe(Ql)ON=0.7 [V],\7be(Q2
)ON=-0,7 [V], the window width is Vin
-w= 1, 4 [V co.

Next, VCCMIN, which is the minimum operating power supply of the above circuit, is the collector saturation voltage Vce5at (
Q2) =0. 1 [V] Base-emitter voltage of transistor Q33 Vbf3 (Q3) = 0.7 [V] VbefQ1)ON = 0, 7 [V]
VCC) 41N = Vbe(Ql) ON mode v be(Q
3)+Vce5atfQ2)=1.5 [V].

(Issues that the invention aims to solve) As mentioned above, the conventional window circuit has a wide window width (1.4 [V] in the calculation example), and in order to narrow this width, a DC amplifier is installed at the front stage. There is a need.

■Looking at the minimum operating power supply voltage, the calculation example shows V CCMIN
= 1.5[V], very low voltage (e.g. VCCHIN
≦1.0 [V]'') is impossible.

However, recent electronic devices are small and FM
There is a need for a circuit that has the ability to discriminate detection outputs with high precision and that can operate at ultra-low voltages.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a window circuit that can narrow the window width by a simple means and can operate at an extremely low voltage.

[Configuration of the Invention (Means for Solving the Problems) This invention provides a first set potential in the increasing direction of the input voltage;
As upper and lower limit setting circuits that respectively detect the second set potential in the decreasing direction, transistors with different emitter area ratios are combined in parallel in each circuit, and the output of the transistor with a larger area is converted into a current mirror circuit with a smaller area. The configuration is such that it is applied to the output node of the transistor. Therefore, a basic configuration is adopted in which an output circuit having a common load circuit is connected to the output node of the transistor having a smaller area in each discrimination circuit.

(Function) With the above means, the threshold level of each discrimination circuit is determined by the emitter area ratio of the transistor, without using the voltage between the base and emitter of the transistor, and the upper limit of the window width. The difference between the lower limit and the lower limit can be reduced.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. For example, an FM detection output voltage V in (triangle curve characteristic) obtained by detecting the intermediate frequency of a tuner is supplied between terminals 1 and 2. Terminal 1
is an upper limit setting circuit 11 that detects the upper limit voltage of the window width.
A lower limit setting circuit 12 is connected to the bases of the transistors Ql and Q2, and detects the lower limit voltage of the window width.
is connected to the base of transistor Q3. Also terminal 2
is connected to the base of transistor Q4 of lower limit setting circuit 12.

A current source ■1 is connected between the power line 13 and the ground line 14.
Diode-connected transistors Q5 are connected in series.

In the upper limit setting circuit 11, transistors Q1 and Q2 are connected in parallel, and the emitter of transistor Q1 is connected to the emitter of transistor Q2 via resistor R1.
The emitters of transistors Q1 to Q2 are connected to the ground line 14 via a resistor R2. The collector of transistor Q1 is connected to the cathode of diode Q6 and the base of transistor Q7, which constitute a current mirror circuit that acts as an active load. Anode of diode Q6 and 1
~The emitter of transistor Q7 is connected to the power supply line 13, and the collector of transistor Q7, which is the output node of the current mirror circuit, is connected to the collector of transistor Q2, which also constitutes the output circuit.
Connected to the base of 8. The emitter of the transistor Q8 is connected to the power supply line 13, and the collector is connected to the load resistance R[
connected to. Here, the emitter area ratios of the transistors Q1 and Q2 are different, and the emitter area of the transistor Q1 is set to be large.

The lower limit setting circuit 12 has a similar configuration, but the emitter of the transistor Q3 is connected to the emitter of the transistor Q4 via a resistor R3, and is also connected to the ground line 14 via a resistor R4. Therefore, the biases of transistors Q1 and Q2 of upper limit setting port B11 are different. On the other hand, the configurations of a current mirror circuit as an active load connected to the collector side of transistors Q3 and Q4 and an output circuit (consisting of a diode Q9 and transistors QIO and Q11) are the same as those of the upper limit setting circuit 11.

This embodiment is configured as described above.

In the upper limit setting circuit 11, when the collector current I C (Q2) of the transistor Q2 is larger than the collector voltage aIC (Ql) of the transistor Q1, that is, when I c (Q2) > I c (Ql), the transistor Q8 flows, this transistor Q8 turns on, and a collector current ICfQ8) flows through the load resistance R. Conversely, if Ic(Q2)≦IC(Ql
)(7), the transistor Q8 is in a cut-off state.

On the other hand, in the lower limit setting circuit 12, the transistor Q4
The collector voltage i 1 c (Q4) of transistor Q3
When the collector current A I C (03) is larger than I c (03), that is, I c (Q4) > I cfQ3), the base ti of the transistor Qll flows, this transistor Qll is turned on, and the collector current I c ( Qll), conversely, Ic(Q4)≦I
c(Q3), transistors 1 to Q11 are in the cutoff state.

Here, the upper limit V in of the window width (old and lower limit V 1n
fL) is determined as follows.

However, each collector current at the threshold point is expressed as I c (Ql) = I c (Q2) = I c (Q
3) = I c [Q4), and the transistor Q2. Q
4. Assuming that the emitter areas of Q5 are equal, the transistor Q
l, the emitter area of Q2 is the ratio N1, the transistor Q3.
Let the emitter area ratio of Q4 be N2. Also, △Vbe is ■
1 is the current value of the current source 1, VT is the thermal voltage of electrons, k: Boltzmann constant, T: absolute temperature, and q: electric charge of electrons.

For example, 11 = 50 μA, Ic(Ql) = 2 μA,
R1 = 18 kΩ, R2 = 33Ω, R3 = 7Ω,
If R4=18, Ω, N1-4, N2=4, (1)
From equation (2), Vin (H) = 50 mV, Vin (L) = -50 mV. Further, the window width Vin-w is V 1n-v=
V 1niH) −V 1n(L)=100rrtV.

Furthermore, the collector saturation regions of each transistor are all equal.
Assuming Vce5at, the lowest operating type a voltage ■CC old N is VCCHIN -Vbe(Q6)+Vce5at -V
befQl) 10V 1n(H) + V be(Q5)
Here, Vbe(Qf3)=0, 62 [V], Vbe(Q
l)=0, 58[V], Vbe(Q5)=0,
70 [V], VCeSat =0, 10 [V],
If Vinf old = 0.05 [V], then VCCMIN = 0.89 [V].

This invention is not limited to the above circuit configuration,
The polarity of the transistor may be the opposite of that of the one in FIG. are given the same reference numerals. However, in this embodiment, the circuit 11 detects the lower limit of the window width, and the circuit 12 detects the upper limit of the window width.

[Effects of the Invention] As described above, according to the present invention, the window width can be narrowed by a simple means, and ultra-low voltage operation is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional window circuit. Q1-Q5, Ql, Q8, QIOlQll...transistor, Q6, Q9...diode, R1-R4...
·resistance. 1. Indication of the case Japanese Patent Application No. 63-86620 2. Title of the invention Window circuit 3. Person making the amendment Relationship with the case Patent applicant (307) Toshiba Corporation 4, Agent Chiyoda-ku, Tokyo Kasumigaseki 3-7-2-6, Figure 3 subject to correction

Claims (1)

[Claims] It has first and second setting circuits that detect one limit voltage and the other limit voltage in the direction of change of the input voltage, and the input voltage has a value between the limit voltages of the first and second setting circuits. In the window circuit for detection, transistors with different emitter areas are combined in parallel in each of the first and second determination circuits, and the output of the transistor with a larger emitter area is transferred to the one with a smaller emitter area via a current mirror circuit. , and the output nodes of the transistors with smaller emitter areas of each setting circuit are connected to a common load via the respective output circuits, while the input voltage is supplied. The input terminal of is connected to the base of the parallel transistor of one judgment circuit and the transistor having a larger emitter area of the other judgment circuit, and the other input terminal to which the input voltage is supplied is connected to the base of the transistor connected in parallel with each other. A window circuit characterized in that a determination circuit is connected to the base of a transistor having a smaller emitter area.