JPH06216722A - Triangular wave oscillating circuit - Google Patents

Triangular wave oscillating circuit

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Publication number
JPH06216722A
JPH06216722A JP50A JP364593A JPH06216722A JP H06216722 A JPH06216722 A JP H06216722A JP 50 A JP50 A JP 50A JP 364593 A JP364593 A JP 364593A JP H06216722 A JPH06216722 A JP H06216722A
Authority
JP
Japan
Prior art keywords
circuit
voltage
current
resistor
limit voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50A
Other languages
Japanese (ja)
Inventor
Ichiro Nomura
一郎 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP50A priority Critical patent/JPH06216722A/en
Publication of JPH06216722A publication Critical patent/JPH06216722A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce a variance in an oscillation frequency due to the variance in a resistance value of each resistor for constituting the circuit, in the triangular wave oscillating circuit, especially, the triangular wave oscillating circuit formed as a semiconductor integrated circuit. CONSTITUTION:Charging and discharging currents of a capacitor 13 are set to a current value being proportional to a current I0 of a reference current circuit consisting of a transistor 2 and a resistance 5 of a current mirror circuit provided in a control circuit 12. Also, an oscillation voltage setting circuit 20 for executing control so that a difference voltage of the upper limit voltage and the lower limit voltage of an oscillation voltage is varied in accordance with a variation in the current value of the current I0 of this reference current circuit is provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、スイッチング電源装置
など電子装置の制御用などとして用いられる三角波発振
回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a triangular wave oscillator circuit used for controlling an electronic device such as a switching power supply device.

【0002】[0002]

【従来の技術】図2は従来の三角波発振回路の一例を示
す回路図である。図2において、三角波発振回路はその
エミッタが電源端子1にそのコレクタが抵抗5を介し接
地端子に接続され、そのベースとコレクタとが短絡され
たトランジスタ2と、このトランジスタ2のエミッタお
よびベースにそれぞれそのエミッタおよびベースが接続
されたトランジスタ3および4と、そのコレクタがそれ
ぞれトランジスタ3のコレクタに、そのエミッタがそれ
ぞれ接地端子に、そのベースが互に接続されたトランジ
スタ6および7と、そのコレクタがトランジスタ4のコ
レクタに、そのエミッタが接地端子に、そのベースがト
ランジスタ7のベースに接続され、そのベースとコレク
タとが短絡されたトランジスタ8と、電源端子1と接地
端子間に直列に接続された抵抗14,15および16
と、その出力端子がトランジスタ4のコレクタに、その
+入力端子がトランジスタ3のコレクタに、その−入力
端子が抵抗14と15との接続点に接続されたオペアン
プ9と、そのコレクタが抵抗15と16の接続点に、そ
のエミッタが接地端子に、そのベースがオペアンプ9の
出力端子に接続されたトランジスタ11と、トランジス
タ3のコレクタと接地端子の間に接続されたコンデンサ
13とからなり、2〜11で制御回路12を14〜16
で発振電圧設定回路17を構成している。
2. Description of the Related Art FIG. 2 is a circuit diagram showing an example of a conventional triangular wave oscillator circuit. In FIG. 2, a triangular wave oscillator circuit has a transistor 2 whose emitter is connected to a power supply terminal 1 and whose collector is connected to a ground terminal through a resistor 5 and whose base and collector are short-circuited, and to the emitter and base of this transistor 2, respectively. Transistors 3 and 4 having their emitters and bases connected, transistors 6 and 7 having their collectors connected to the collector of transistor 3, their emitters connected to the ground terminal, and their bases connected to each other, and their collectors being transistors 4, the emitter of which is connected to the ground terminal, the base of which is connected to the base of the transistor 7, and the base of which is shorted to the collector of the transistor 8 and the resistor which is connected in series between the power supply terminal 1 and the ground terminal. 14, 15 and 16
An operational amplifier 9 having its output terminal connected to the collector of the transistor 4, its + input terminal connected to the collector of the transistor 3, and its-input terminal connected to the connection point between the resistors 14 and 15, and its collector connected to the resistor 15. At the connection point of 16, a transistor 11 having its emitter connected to the ground terminal and its base connected to the output terminal of the operational amplifier 9, and a capacitor 13 connected between the collector of the transistor 3 and the ground terminal are provided. 11 to control circuit 12 14-16
Constitutes the oscillation voltage setting circuit 17.

【0003】この三角波発振回路の動作は次の通りであ
る。トランジスタ2,3および4は電流ミラー回路を構
成し、トランジスタ2および抵抗5で構成される基準電
流回路の電流I0 に等しい電流I0 がトランジスタ3お
よび4のコレクタに流れる(トランジスタ2,3および
4は同じ容量として)。また、トランジスタ8,7およ
び6は電流ミラー回路を構成しトランジスタ8に電流I
0 が流れたとき(この電流はトランジスタ4のコレクタ
から供給される)、トランジスタ6および7にそれぞれ
電流I0 が流れる。ここで電源端子1に電圧Vが印加さ
れると、オペアンプ9の−入力端子には、発振電圧設定
回路17の抵抗14,15および16によって分圧され
た電源電圧Vの分電圧V1 が入力される。式1はこの分
電圧V1の電圧値を示す。
The operation of this triangular wave oscillator circuit is as follows. Transistors 2, 3 and 4 constitute a current mirror circuit, equal currents I 0 to the current I 0 of the reference current circuit constituted by the transistors 2 and resistor 5 flows through the collectors of the transistors 3 and 4 (transistors 2, 3 and 4 as the same capacity). Further, the transistors 8, 7 and 6 form a current mirror circuit, and a current I is supplied to the transistor 8.
When 0 flows (this current is supplied from the collector of transistor 4), current I 0 flows through transistors 6 and 7, respectively. Here, when the voltage V is applied to the power supply terminal 1, the negative voltage V 1 of the power supply voltage V divided by the resistors 14, 15 and 16 of the oscillation voltage setting circuit 17 is input to the negative input terminal of the operational amplifier 9. To be done. Equation 1 shows the voltage value of the divided voltage V 1.

【0004】[0004]

【数1】 V1 =(R15+R16/R14+R15+R16)・V────
───(1) 但し、R14,R15およびR16はそれぞれ抵抗14,15
および16の抵抗値を示す。また、オペアンプ9の+入
力端子はコンデンサ13(このときはまだ充電されてい
ないのでその両端子間電圧は0)を介して接地端子に接
続されているので入力電圧は0であり、オペアンプ9の
出力端子は「L」の信号を出力する。この「L」の出力
信号によってトランジスタ8,7,6および12はオフ
となる。一方トランジスタ2,3および4からなる電流
ミラー回路のトランジスタ2および抵抗5で構成される
基準電流回路に電流I0 が流れ、この電流I0 に等しい
電流I 0 がトランジスタ3のコレクタからコンデンサ1
3に流れコンデンサ13を充電する。このコンデンサ1
3の両端子間電圧はオペアンプ9の+入力端子に入力さ
れるので、充電によりこの両端子間電圧が式(1)に示
すオペアンプ9の−入力端子に入力されている分電圧V
1 を越えると、オペアンプ9の出力信号「L」から
「H」に切り換わる。オペアンプ9の出力信号が「H」
に切り換わると、トランジスタ8,7,6および11が
オンする。トランジスタ11のオンによってオペアンプ
9の−入力端子の電圧は式(2)に示す抵抗14および
15による電源電圧Vの分電圧V2 に切り換わる。
[Formula 1] V1= (R15+ R16/ R14+ R15+ R16) ・ V────
─── (1) However, R14, R15And R16Are resistors 14 and 15 respectively
And 16 resistance values are shown. In addition, the operational amplifier 9 + input
The output terminal is capacitor 13 (at this time it is still charged)
Therefore, the voltage between both terminals is connected to the ground terminal via 0).
Since the input voltage is 0, the operational amplifier 9
The output terminal outputs a signal of "L". Output of this "L"
Signals turn off transistors 8, 7, 6 and 12
Becomes On the other hand, the current composed of transistors 2, 3 and 4
It is composed of the transistor 2 and the resistor 5 of the mirror circuit.
Current I in the reference current circuit0Flows, this current I0be equivalent to
Current I 0From the collector of transistor 3 to capacitor 1
3 to charge the capacitor 13. This capacitor 1
The voltage between both terminals of 3 is input to the + input terminal of operational amplifier 9.
As a result of charging, the voltage between both terminals is shown in equation (1).
Voltage V input to the minus input terminal of the operational amplifier 9
1When it exceeds, from the output signal “L” of the operational amplifier 9,
Switch to "H". Output signal of operational amplifier 9 is "H"
Switching to transistors 8, 7, 6 and 11
Turn on. The operational amplifier is turned on by turning on the transistor 11.
The voltage at the-input terminal of 9 is
Power source voltage V divided by 15 V2Switch to.

【0005】[0005]

【数2】V2 =(R15/R14+R15)・V──────
───────(2) 同時にトランジスタ8,7,6のオンによって、トラン
ジスタ8にはトランジスタ8のコレクタから供給される
電流I0 が、トランジスタ7,6のコレクタにはこの電
流I0 に等しい電流I0 がそれぞれ流れる。従ってコン
デンサ13はこの電流I0 で放電する(コンデンサ13
への流入電流はトランジスタ3のコレクタ電流I0 であ
り、コンデンサ13からの流出電流はトランジスタ6お
よび7の電流の和2I0 であり、差し引きI0 の電流で
コンデンサ13は放電する)。そしてコンデンサ13の
両端子間電圧が式(2)に示す分電圧V2 まで低下する
と、オペアンプ9の出力信号は「H」から「L」に切り
換わる。この動作は繰り返されて発振が継続する。ま
た、分電圧V1 およびV2 はそれぞれ発振の上限電圧お
よび下限電圧を定める。
[Formula 2] V 2 = (R 15 / R 14 + R 15 ) ・ V ───────
(2) At the same time, when the transistors 8, 7 and 6 are turned on, the current I 0 supplied from the collector of the transistor 8 is supplied to the transistor 8 and this current I 0 is supplied to the collectors of the transistors 7 and 6. A current I 0 equal to the current flows. Therefore, the capacitor 13 is discharged with this current I 0 (capacitor 13
The inflow current into the transistor 3 is the collector current I 0 of the transistor 3, the outflow current from the capacitor 13 is the sum of the currents of the transistors 6 and 7 2I 0 , and the current of the subtraction I 0 discharges the capacitor 13). Then, when the voltage between both terminals of the capacitor 13 decreases to the voltage V 2 corresponding to the expression (2), the output signal of the operational amplifier 9 switches from “H” to “L”. This operation is repeated and oscillation continues. Further, the divided voltages V 1 and V 2 define the upper limit voltage and the lower limit voltage of oscillation, respectively.

【0006】ここでコンデンサ13の容量をCとし、そ
の両端子間電圧が発振電圧の上限電圧V1 に上昇するま
での充電時間をt1 、上限電圧V1 から下限電圧V2
低下するまでの放電時間をt2 とすると、発振周波数f
は式(3)で求められる。
Here, the capacitance of the capacitor 13 is C, the charging time until the voltage between both terminals thereof rises to the upper limit voltage V 1 of the oscillation voltage is t 1 , and until the upper limit voltage V 1 drops to the lower limit voltage V 2. When the discharge time of is t 2 , the oscillation frequency f
Is calculated by the equation (3).

【0007】[0007]

【数3】 I0 ・t1 =C(V1 −V2 ) I0 ・t2 =C(V1 −V2 ) ∴f=1/t1 +t2 =I0 /2C(V1 −V2 )──
────(3) なお、発振動作を安定化するために、トランジスタ11
のオン後にトランジスタ8,7および6がオンし、トラ
ンジスタ11のオフ後にトランジスタ8,7,6がオフ
するように、これらトランジスタの動作時間に若干の差
を持たせるようにする。
I 0 · t 1 = C (V 1 −V 2 ) I 0 · t 2 = C (V 1 −V 2 ) ∴f = 1 / t 1 + t 2 = I 0 / 2C (V 1 − V 2 ) ──
──── (3) In order to stabilize the oscillation operation, the transistor 11
The transistors 8, 7 and 6 are turned on after turning on, and the transistors 8, 7 and 6 are turned off after turning off the transistor 11, so that the operating times of these transistors have a slight difference.

【0008】[0008]

【発明が解決しようとする課題】前述の三角波発振回路
は、通常半導体集積回路として形成されるので回路を構
成する各抵抗の抵抗値に比較的大きなばらつきが発生す
る(しかしこれら各抵抗間の抵抗値の相対的ばらつき
は、同一集積回路内にあるので殆んど0である)。この
ように、抵抗値にばらつきがあると、発振周波数に比較
的大きなばらつきを生じるようになる。すなわち、式
(3)に示すように発振周波数は基準電流回路の電流I
0 に比例し、発振電圧の上限電圧V1 と下限電圧V2
差に逆比例する。そして、抵抗値にばらつきがあると図
2において基準電流回路の電流I0 は抵抗5の抵抗値の
ばらつきに対応してばらつくが、発振電圧の上限電圧V
1 と下限電圧V2 は抵抗14,15および16の抵抗値
の相対的ばらつきは0であるので一定となり、発振周波
数は抵抗5の抵抗値のばらつきによりばらつく基準電流
回路の電流I0 のばらつきに等しいばらつきを生じる。
Since the above-mentioned triangular wave oscillator circuit is usually formed as a semiconductor integrated circuit, there is a relatively large variation in the resistance values of the resistors forming the circuit (however, the resistance between these resistors is large). The relative variation of the values is almost 0 because they are in the same integrated circuit). As described above, when the resistance value varies, the oscillation frequency relatively varies. That is, as shown in equation (3), the oscillation frequency is the current I of the reference current circuit.
It is proportional to 0 and inversely proportional to the difference between the upper limit voltage V 1 and the lower limit voltage V 2 of the oscillation voltage. When the resistance value varies, the current I 0 of the reference current circuit varies in accordance with the variation in the resistance value of the resistor 5 in FIG. 2, but the upper limit voltage V of the oscillation voltage V
1 and the lower limit voltage V 2 are constant because the relative variations of the resistance values of the resistors 14, 15 and 16 are 0, and the oscillation frequency varies due to the variation of the resistance value of the resistor 5 and thus the variation of the current I 0 of the reference current circuit. Produce equal variations.

【0009】本発明の目的は回路を構成する各抵抗のば
らつき(但しこれら各抵抗間の相対的ばらつきは殆んど
0である)による発振周波数のばらつきを低減すること
にある。
An object of the present invention is to reduce the variation in the oscillation frequency due to the variation in the resistors constituting the circuit (however, the relative variation between these resistors is almost zero).

【0010】[0010]

【課題を解決するための手段】前述の目的を達成するた
めに本発明は、発振電圧の上限電圧と下限電圧を定める
発振電圧設定回路と、コンデンサと、このコンデンサを
所定の電流値の充電電流で前記発振電圧の下限電圧から
上限電圧まで充電し、充電後は所定の電流値の放電電流
で上限電圧から下限電圧まで放電し、以後これを繰り返
す制御回路とからなる三角波発振回路において、前記コ
ンデンサの充電および放電電流を制御回路に設けた電流
ミラー回路の電源と接地間に接続されたトランジスタと
抵抗(以下第1の抵抗と称する)とからなる基準電流回
路の電流に比例した電流値に設定し、前記発振電圧設定
回路によって定められる発振電圧の上限電圧と下限電圧
の差電圧をこの基準電流回路の電流の電流値の変化に対
応して変化するように制御する。そしてこの発振電圧設
定回路は制御回路の電流ミラー回路の基準電流回路の電
流値に比例した電流が通電される第2の抵抗,ダイオー
ドおよび第3の抵抗を備え、この第2の抵抗の電圧降下
が発振電圧の下限電圧を定め、第2の抵抗,ダイオード
および第3の抵抗の電圧降下の和が上限電圧を定めるよ
うにする。また、この三角波発振回路は半導体集積回路
として形成する。
In order to achieve the above object, the present invention provides an oscillation voltage setting circuit for determining an upper limit voltage and a lower limit voltage of an oscillation voltage, a capacitor, and a charging current of a predetermined current value for the capacitor. In the triangular wave oscillating circuit consisting of a control circuit for charging from the lower limit voltage to the upper limit voltage of the oscillating voltage, discharging from the upper limit voltage to the lower limit voltage with a discharge current of a predetermined current value after charging, and repeating the hereafter. The charging and discharging currents of the above are set to current values proportional to the current of the reference current circuit including the transistor and the resistor (hereinafter referred to as the first resistor) connected between the power supply and the ground of the current mirror circuit provided in the control circuit. However, the difference voltage between the upper limit voltage and the lower limit voltage of the oscillation voltage determined by the oscillation voltage setting circuit is changed according to the change of the current value of the current of the reference current circuit. To control to. The oscillation voltage setting circuit includes a second resistor, a diode and a third resistor through which a current proportional to the current value of the reference current circuit of the current mirror circuit of the control circuit is passed, and the voltage drop of the second resistor is caused. Determines the lower limit voltage of the oscillation voltage, and the sum of the voltage drops of the second resistor, the diode and the third resistor determines the upper limit voltage. The triangular wave oscillator circuit is formed as a semiconductor integrated circuit.

【0011】[0011]

【作用】本発明の三角波発振回路は、コンデンサの充電
および放電電流を制御回路に設けた電流ミラー回路の電
源と接地との間に接続されたトランジスタと第1の抵抗
とからなる基準電流回路の電流に比例した電流値を設定
し、発振電圧の上限電圧と下限電圧の差電圧をこの基準
電流回路の電流の電流値の変化に対応して変化するよう
に制御したので、電流ミラー回路の基準電流回路の第1
の抵抗の抵抗値がばらつきにより、例えば増加したと
き、基準電流回路の電流の電流値が低下し、これによっ
てコンデンサの充電および放電電流が低下するとともに
発振電圧の上限電圧と下限電圧の差電圧が低下するの
で、コンデンサの充電および放電時間の変化を抑えるよ
うに動作する。このようにして抵抗値のばらつきによる
発振周波数のばらつきは低減される。そして発振電圧設
定回路は制御回路の電流ミラー回路の基準電流回路の電
流値に比例した電流が通電される第2の抵抗,ダイオー
ドおよび第3の抵抗を備え、この第2の抵抗の電圧降下
が発振電圧の下限電圧を定め、第2の抵抗,ダイオード
および第3の抵抗の電圧降下の和が上限電圧を定めるよ
うにしたので、この第2の抵抗および第3の抵抗の抵抗
値は電流ミラー回路の基準電流回路の第1の抵抗の抵抗
値に比例してばらつくので(回路を半導体集積回路とし
て形成したとき各抵抗間の抵抗値の相対的ばらつきは殆
んど0であるので)、第2および第3の抵抗は、例えば
その抵抗値が増加した分通電する電流が低下するのでそ
れらの電圧降下は一定であり、一方ダイオードは通電電
流が低下するとその電圧降下は低下する。従って、第2
の抵抗の電圧降下で定められる発振の下限電圧は一定で
あり、ダイオードと第3の抵抗で定められる上限電圧は
低下するので発振電圧の上限電圧と下限電圧の差電圧は
低下する。このようにして発振電圧の上限電圧と下限電
圧の差電圧を電流ミラー回路の基準電流回路の電流値に
対応して変化させることができる。
The triangular wave oscillating circuit of the present invention is a reference current circuit comprising a transistor and a first resistor connected between the power supply and the ground of a current mirror circuit provided with a charging and discharging current of a capacitor in a control circuit. Since the current value proportional to the current is set and the difference voltage between the upper limit voltage and the lower limit voltage of the oscillation voltage is controlled to change in accordance with the change in the current value of the reference current circuit, the reference value of the current mirror circuit is set. First of current circuit
When the resistance value of the resistor is varied, for example, when it increases, the current value of the current of the reference current circuit decreases, which decreases the charging and discharging currents of the capacitor and reduces the difference voltage between the upper limit voltage and the lower limit voltage of the oscillation voltage. Therefore, it operates so as to suppress changes in the charging and discharging times of the capacitor. In this way, variations in oscillation frequency due to variations in resistance value are reduced. The oscillation voltage setting circuit is provided with a second resistor, a diode and a third resistor through which a current proportional to the current value of the reference current circuit of the current mirror circuit of the control circuit is passed, and the voltage drop of this second resistor is Since the lower limit voltage of the oscillation voltage is determined and the sum of the voltage drops of the second resistor, the diode and the third resistor determines the upper limit voltage, the resistance values of the second resistor and the third resistor are set to the current mirror. Since the reference current of the circuit varies in proportion to the resistance value of the first resistor of the circuit (since the resistance value of each resistor is almost zero when the circuit is formed as a semiconductor integrated circuit), The second and third resistors have a constant voltage drop because, for example, the amount of current flowing through them decreases as the resistance value increases. On the other hand, the voltage drop of the diode decreases as the conduction current decreases. Therefore, the second
The lower limit voltage of oscillation determined by the voltage drop of the resistor is constant, and the upper limit voltage determined by the diode and the third resistor decreases, so that the difference voltage between the upper limit voltage and the lower limit voltage of the oscillation voltage decreases. In this way, the difference voltage between the upper limit voltage and the lower limit voltage of the oscillation voltage can be changed according to the current value of the reference current circuit of the current mirror circuit.

【0012】[0012]

【実施例】図1は本発明の三角波発振回路の一実施例を
示す回路図である。図1に示す本発明の三角波発振回路
は図2に示す従来の三角波発振回路において、抵抗1
4,15および16からなる発振電圧設定回路17に代
えて、発振電圧設定回路20を設けたものである。この
発振電圧設定回路20は、制御回路12のトランジスタ
2のエミッタおよびベースにそのエミッタおよびベース
が接続され、そのコレクタは直列に接続された抵抗2
2,ダイオード23および抵抗24を介して接地端子に
接続されたトランジスタ21と、その+入力端子がトラ
ンジスタ21のコレクタに、その−入力端子が抵抗26
と基準電源24を介して接地端子にそれぞれ接続され、
その出力端子と−入力端子の間に抵抗27が接続された
オペアンプ25とからなり、このオペアンプ25の出力
端子をオペアンプ9の−入力端子に接続し、抵抗22と
ダイオード23の接続点をトランジスタ12のコレクタ
に接続したものである。
1 is a circuit diagram showing an embodiment of a triangular wave oscillator circuit of the present invention. The triangular wave oscillator circuit of the present invention shown in FIG. 1 corresponds to the conventional triangular wave oscillator circuit shown in FIG.
An oscillation voltage setting circuit 20 is provided instead of the oscillation voltage setting circuit 17 composed of 4, 15 and 16. In this oscillation voltage setting circuit 20, the emitter and the base of the transistor 2 of the control circuit 12 are connected to the emitter and the base, and the collector is connected in series to the resistor 2.
2, the transistor 21 connected to the ground terminal via the diode 23 and the resistor 24, its + input terminal is the collector of the transistor 21, and its − input terminal is the resistor 26
And the ground terminal via the reference power source 24,
The output terminal of the operational amplifier 25 is connected to the-input terminal of the operational amplifier 9, and the connecting point of the resistor 22 and the diode 23 is connected to the transistor 12. It is connected to the collector of.

【0013】この三角波発振回路の動作は次の通りであ
る。トランジスタ2とトランジスタ21とは電流ミラー
回路を構成し、トランジスタ21のコレクタにはトラン
ジスタ2および抵抗5で構成される基準電流回路の電流
0 に等しい電流I0 が流れる(トランジスタ2と21
は同じ容量として)。ここで抵抗5,22および24は
その抵抗値にばらつきがあっても、同じ集積回路内に形
成されているのでそれらの相対的ばらつきは0であるの
で、抵抗22および24の電圧降下は一定となる(例え
ば、抵抗5の抵抗値がx%増加したとすると、電流I0
はx%低減する。しかし抵抗22あるいは24の抵抗値
は同様x%増加しているので、電流I0による抵抗22
あるいは24の電圧降下は相殺されて一定となる)。一
方ダイオード23の電圧降下は、例えば通電電流が2倍
になると18mV電圧降下が増大するように電流の大きさ
に依存して増大する。従ってオペアンプ25の+入力端
子にはトランジスタ12のオフ時は抵抗22,ダイオー
ド23および抵抗24の電圧降下の和E1 が入力され、
トランジスタ12のオン時は抵抗22の電圧降下E 2
入力される。オペアンプ25,抵抗26および26,基
準電圧24はリニア増幅回路を構成しているので、オペ
アンプ25の出力端子にはこの入力電圧E1あるいはE
2 に比例した出力電圧V1 あるいはV2 を出力する。こ
の出力電圧V 1 あるいはV2 はオペアンプ9の−入力端
子に入力される。この出力電圧V1 およびV2 は図2に
おける分電圧V1 およびV2 と同様発振の上限電圧およ
び下限電圧を与える。ここでオペアンプ25の出力電圧
2 は抵抗22の電圧降下で定まる一定値であり、出力
電圧V1 は抵抗22の一定の電圧降下と通電電流の大き
さによって、例えば通電電流が低下したときその電圧降
下が低下するダイオード23の電圧降下の和で定まるの
で、例えば抵抗値のばらつきによって基準電流回路の抵
抗5の抵抗値が増大し、この電流I0 が低下したとき低
下する。従って発振電圧の上限電圧と下限電圧の差電圧
は低下するように変化し、式(3)に示すように発振周
波数fの変化を抑えるように動作する。このようにして
抵抗値のばらつきによる発振周波数のばらつきを低減で
きる。なおその他の動作については図2と同様である。
The operation of this triangular wave oscillator circuit is as follows.
It Transistor 2 and transistor 21 are current mirrors
The circuit is configured and the collector of the transistor 21 is
Current of reference current circuit composed of resistor 2 and resistor 5
I0Current equal to0Flows (transistors 2 and 21
As the same capacity). Here the resistors 5, 22 and 24 are
Even if there are variations in the resistance value,
Because they are made, their relative variation is 0
, The voltage drop across resistors 22 and 24 is constant (eg
For example, if the resistance value of the resistor 5 increases by x%, the current I0
Is reduced by x%. However, the resistance value of the resistor 22 or 24
Also increases by x%, the current I0Resistance by 22
Or the voltage drop of 24 is canceled and becomes constant). one
The voltage drop of the rectangular diode 23 is,
The current magnitude so that the voltage drop will increase by 18mV
Increase depending on. Therefore, the + input terminal of the operational amplifier 25
When the transistor 12 is off, the child has a resistor 22 and a diode.
Sum E of the voltage drops of the resistor 23 and the resistor 241Is entered,
When the transistor 12 is on, the voltage drop E of the resistor 22 2But
Is entered. Operational amplifier 25, resistors 26 and 26, a group
Since the quasi-voltage 24 constitutes a linear amplifier circuit,
This input voltage E is applied to the output terminal of the amplifier 25.1Or E
2Output voltage V proportional to1Or V2Is output. This
Output voltage V 1Or V2Is the-input terminal of the operational amplifier 9.
Input to child. This output voltage V1And V2In Figure 2
Voltage V1And V2Same as the upper limit voltage of oscillation and
And lower limit voltage. Here, the output voltage of the operational amplifier 25
V2Is a constant value determined by the voltage drop of the resistor 22, and the output
Voltage V1Is the constant voltage drop across the resistor 22 and the magnitude of the current
Depending on the level, for example, when the energizing current drops, the voltage drop
It is determined by the sum of the voltage drops of the diode 23
Therefore, for example, the resistance of the reference current circuit may vary due to variations in resistance.
The resistance value of the anti-5 increases and this current I0Low when drops
Down. Therefore, the difference between the upper limit voltage and the lower limit voltage of the oscillation voltage
Changes so as to decrease, and the oscillation frequency changes as shown in equation (3).
It operates so as to suppress the change in the wave number f. In this way
It is possible to reduce variations in oscillation frequency due to variations in resistance value.
Wear. The other operations are the same as in FIG.

【0014】[0014]

【発明の効果】本発明の三角波発振回路は回路を構成す
る各抵抗の抵抗値のばらつき(但し各抵抗の相対的ばら
つきは殆んど0である)による発振周波数のばらつきを
低減したので、安定した発振周波数が必要とされるスイ
ッチング電源装置など電子装置の制御用などとして有効
である。特に回路を構成する各抵抗の抵抗値のばらつき
が比較的大きく、かつ各抵抗の相対的ばらつきが殆んど
ない半導体集積回路の場合特に有効である。
The triangular wave oscillating circuit of the present invention is stable because the variation of the oscillation frequency due to the variation of the resistance value of each resistor forming the circuit (however, the relative variation of each resistor is almost 0) is reduced. This is effective for controlling electronic devices such as switching power supply devices that require the above oscillation frequency. In particular, it is particularly effective in the case of a semiconductor integrated circuit in which the resistance values of the resistors forming the circuit have a relatively large variation and the resistors have almost no relative variation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の三角波発振回路の一実施例を示す回路
FIG. 1 is a circuit diagram showing an embodiment of a triangular wave oscillator circuit of the present invention.

【図2】従来の三角波発振回路の一例を示す回路図FIG. 2 is a circuit diagram showing an example of a conventional triangular wave oscillator circuit.

【符号の説明】[Explanation of symbols]

2 トランジスタ 5 第1の抵抗 12 制御回路 13 コンデンサ 20 発振電圧設定回路 22 第2の抵抗 23 ダイオード 24 第3の抵抗 2 Transistor 5 1st resistance 12 Control circuit 13 Capacitor 20 Oscillation voltage setting circuit 22 2nd resistance 23 Diode 24 3rd resistance

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】発振電圧の上限電圧と下限電圧を定める発
振電圧設定回路と、コンデンサと、このコンデンサを所
定の電流値の充電電流で前記発振電圧の下限電圧から上
限電圧まで充電し、充電後は所定の電流値の放電電流で
上限電圧から下限電圧まで放電し、以後これを繰り返す
制御回路とからなる三角波発振回路において、前記コン
デンサの充電および放電電流を制御回路に設けた電流ミ
ラー回路の電源と接地間に接続されたトランジスタと抵
抗(以下第1の抵抗と称する)とからなる基準電流回路
の電流に比例した電流値に設定し、前記発振電圧設定回
路によって定められる発振電圧の上限電圧と下限電圧の
差電圧をこの基準電流回路の電流の電流値の変化に対応
して変化するように制御することを特徴とする三角波発
振回路。
1. An oscillation voltage setting circuit that determines an upper limit voltage and a lower limit voltage of an oscillation voltage, a capacitor, and a capacitor, the capacitor is charged with a charging current having a predetermined current value from the lower limit voltage to the upper limit voltage of the oscillation voltage, and after charging. Is a triangular wave oscillating circuit consisting of a control circuit that discharges from an upper limit voltage to a lower limit voltage with a discharge current of a predetermined current value, and then repeats this. And an upper limit voltage of the oscillation voltage determined by the oscillation voltage setting circuit, which is set to a current value proportional to the current of a reference current circuit including a transistor and a resistor (hereinafter referred to as a first resistor) connected between the ground and the ground. A triangular wave oscillating circuit characterized in that the difference voltage of the lower limit voltage is controlled so as to change in accordance with the change of the current value of the current of the reference current circuit.
【請求項2】請求項1記載の三角波発振回路において、
発振電圧設定回路は制御回路の電流ミラー回路の基準電
流回路の電流値に比例した電流が通電される第2の抵
抗,ダイオードおよび第3の抵抗を備え、この第2の抵
抗の電圧降下が発振電圧の下限電圧を定め、第2の抵
抗,ダイオードおよび第3の抵抗の電圧降下の和が上限
電圧を定めることを特徴とする三角波発振回路。
2. The triangular wave oscillator circuit according to claim 1,
The oscillation voltage setting circuit includes a second resistor, a diode and a third resistor through which a current proportional to the current value of the reference current circuit of the current mirror circuit of the control circuit is passed, and the voltage drop of the second resistor oscillates. A triangular wave oscillating circuit characterized in that a lower limit voltage is determined, and a sum of voltage drops of the second resistor, the diode and the third resistor determines an upper limit voltage.
【請求項3】半導体集積回路として形成されることを特
徴とする請求項1あるいは2記載の三角波発振回路。
3. The triangular wave oscillator circuit according to claim 1, wherein the triangular wave oscillator circuit is formed as a semiconductor integrated circuit.
JP50A 1993-01-13 1993-01-13 Triangular wave oscillating circuit Pending JPH06216722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50A JPH06216722A (en) 1993-01-13 1993-01-13 Triangular wave oscillating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50A JPH06216722A (en) 1993-01-13 1993-01-13 Triangular wave oscillating circuit

Publications (1)

Publication Number Publication Date
JPH06216722A true JPH06216722A (en) 1994-08-05

Family

ID=11563224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50A Pending JPH06216722A (en) 1993-01-13 1993-01-13 Triangular wave oscillating circuit

Country Status (1)

Country Link
JP (1) JPH06216722A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010058125A (en) * 1999-12-24 2001-07-05 이형도 Oscillation circuit for digital dimming of inverter
JP2006180666A (en) * 2004-12-24 2006-07-06 Sanyo Electric Co Ltd Pwm signal generating circuit
KR101147355B1 (en) * 2004-07-16 2012-05-22 매그나칩 반도체 유한회사 Oscillator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010058125A (en) * 1999-12-24 2001-07-05 이형도 Oscillation circuit for digital dimming of inverter
KR101147355B1 (en) * 2004-07-16 2012-05-22 매그나칩 반도체 유한회사 Oscillator
JP2006180666A (en) * 2004-12-24 2006-07-06 Sanyo Electric Co Ltd Pwm signal generating circuit

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