JP3284340B2 - Oscillator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit.

[0002]

2. Description of the Related Art Conventionally, a configuration as shown in FIG. 12 has been adopted as an oscillation circuit for realizing low current consumption. Referring specifically to FIG. 1, the CMOS inverter 101 is connected to a high-potential power supply 103 and a low-potential power supply 104 via a current limiting element 102 for realizing low current consumption. Load capacity 105
Has one electrode connected to the input side of the CMOS inverter 101 and the other electrode connected to the low potential side power supply 104. The load capacitor 106 has one electrode of a CMOS
The other electrode is connected to the output side of the inverter 101 and the other electrode is connected to the low potential side power supply 104. Note that, in the figure, reference numeral 107 denotes a quartz oscillator, and reference numeral 108 denotes a feedback resistor.

[0003]

However, since the load capacitors 105 and 106 are directly connected to the power supply in the above-mentioned configuration, there is a problem that the power supply voltage fluctuates greatly in synchronization with the oscillation. Was. Therefore, there is a disadvantage that the operation of the circuit that shares the power supply with the oscillation circuit becomes unstable. Conversely, when the power supply voltage fluctuates due to some action irrespective of the oscillation, the fluctuation adversely affects the oscillation circuit.

[0004]

According to the present invention, a first load capacitance is connected between an input side of a CMOS inverter and one power supply potential, and a first load capacitance is connected between the input side of the CMOS inverter and the other power supply potential. , A third load capacitance between the output side of the CMOS inverter and one power supply potential, and a fourth load capacitance between the output side of the CMOS inverter and the other power supply potential. By doing so, it is possible to reduce fluctuations in the power supply voltage synchronized with oscillation while realizing low current consumption.

The first and third load capacitances and the CM
One power supply side of the OS inverter is connected to the one power supply voltage via a first current limiting element, and the second and fourth load capacitors and the other power supply side of the CMOS inverter are connected to a second current limiter. Since the power supply voltage is connected to the other power supply voltage via the element, the first and second current limiting elements that can further reduce the fluctuation of the power supply voltage synchronized with the oscillation while realizing low current consumption may be resistance.

[0006] The first and second current limiting elements may be transistors.

The first and second current limiting elements may be constant current circuits.

The first and second current limiting elements are formed by connecting a plurality of switching elements in parallel, and these switching elements are controlled by a control circuit according to the output of the CMOS inverter, so that the current limiting elements can be adjusted. , Optimal adjustment becomes possible. Also, for example, when the oscillation starts, the switching element is controlled so that a large amount of current flows through these switching elements, and when the oscillation becomes stable, the switching element is controlled so that a current of a predetermined value flows. The time required for the oscillation to stabilize can be shortened, and the responsiveness can be improved.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present application is
A MOS inverter, a piezoelectric element and a feedback resistor respectively connected between input and output terminals of the CMOS inverter, a first load capacitance connected between an input side of the CMOS inverter and one power supply potential, A second terminal connected between the input side of the inverter and the other power supply potential
A third load capacitance connected between the output side of the CMOS inverter and the one power supply potential, and a fourth load capacitance connected between the output side of the CMOS inverter and the other power supply potential. And load capacity.

[0010] The invention according to claim 2 of the present application is the first,
A third load capacitance and one power supply side of the CMOS inverter are connected to the one power supply voltage via a first current limiting element, and the second and fourth load capacitances and the CM are connected.
The other power supply side of the OS inverter is connected to the other power supply voltage via the second current limiting element.

In the invention according to claim 3 of the present application, the first and second current limiting elements are resistors.

In the invention according to claim 4 of the present application, the first and second current limiting elements are transistors.

In the invention according to claim 5 of the present application, the first and second current limiting elements are constant current circuits.

According to a sixth aspect of the present invention, the first and second current limiting elements are obtained by connecting a plurality of switching elements in parallel, and the control for controlling the switching elements in accordance with the output of the CMOS inverter. It has a circuit.

In the invention according to claim 7 of the present application, the switching element is a transistor.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments shown in the drawings.

(Embodiment 1) In FIG.
Inverter, 2 is a crystal oscillator constituting a piezoelectric element, 3 is a feedback resistor, and crystal oscillator 2 and feedback resistor 3 are CMOS
It is connected between the input and output terminals of the inverter 1.
One power supply terminal of the CMOS inverter 1 is connected to the high potential side 5 of the power supply via a P-channel MOS transistor 4 constituting a current limiting element, and the other power supply terminal is
It is connected to the low potential side 7 of the power supply via an N-channel MOS transistor 6 constituting a current limiting element. The gate of the transistor 4 is connected to the low potential side 7 of the power supply,
Are connected to the high potential side 5 of the power supply, and the transistors 4 and 6 each constitute a current limiting element. The first load capacitance 8 has one electrode connected to the input side of the CMOS inverter 1 and the other electrode connected to the high potential side 5.
The second load capacitor 9 has one electrode connected to the input side of the CMOS inverter 1 and the other electrode connected to the low potential side 7. The third load capacitor 10 has one electrode connected to the output side of the CMOS inverter 1 and the other electrode connected to the high potential side 5. The fourth load capacitor 11 has one electrode connected to the output side of the CMOS inverter 1 and the other electrode connected to the low potential side 7. In this example, the load capacities 8 and 9 are used.
And the load capacitors 10 and 11 have the same capacitance.

FIG. 2 shows an oscillation (30 MHz) in the configuration of FIG.
FIG. 7 is a power supply voltage waveform simulation diagram in the case of performing.
Note that a to c in the figure show voltage waveforms at the terminals a to c shown in FIG. FIG. 3 is a comparative example of FIG.
Oscillation (30 MHz) similar to that of FIG. 2 with the conventional configuration shown in FIG.
Is a voltage waveform simulation in the case of performing. In addition,
In the figure, a to c show voltage waveforms at the terminals a to c shown in FIG. 12, and the capacitances of the load capacitors 105 and 106 are each set to 10 pF. Further, in the case of FIG. 2, the magnitudes of the capacitances of the load capacitances 8 to 11 are each set to 5 pF. That is, the configuration is such that the capacitance of the load capacitance 105 in FIG. 12 is covered by the load capacitances 8 and 9, and the capacitance of the load capacitance 106 is covered by the load capacitances 10 and 11.

As is clear from the comparison of FIGS.
When the output (b) of the S inverter 1 is at substantially the same level, the magnitude of the fluctuation of the power supply voltage (a, c) is smaller in FIG.

More specifically, in FIG. 3A (the high potential side of the power supply) of the conventional example, the magnitude of the fluctuation is 0.0004 V at the maximum, whereas FIG. 2A (the high potential side of the power supply) of the present embodiment. In this case, the maximum is 0.00007 V, and the magnitude of the fluctuation is small. FIG. 3C of the conventional example (low potential side of the power supply)
In FIG. 2f (low-potential side of the power supply) in the present embodiment, the maximum amplitude is 0.45 mV.
1 mV, and the magnitude of the fluctuation is small.

As described above, the first load capacitance 8 is connected between the input side of the CMOS inverter 1 and the high potential side 5,
The second between the input side of the MOS inverter 1 and the low potential side 7
, A third load capacitor 10 between the output side of the CMOS inverter 1 and the high potential side 5, and a fourth load capacitor 1 between the output side of the CMOS inverter 1 and the low potential side 7.
1 are connected, the fluctuation of the power supply voltage synchronized with the oscillation can be reduced.

In general, when the oscillation circuit is connected to an external circuit, a bypass capacitor is connected to the high potential side 5 and the low potential side 7 thereof. Therefore, the first load capacitance 8 and the second load capacitance 9 and the third load capacitance 1
If the capacitances of 0 and the fourth load capacitance 11 are made equal, voltage fluctuations on the high potential side and the low potential side connected via the respective load capacitances can be offset by the function of the bypass capacitor, Further stabilization of the power supply voltage can be achieved.

Although a transistor is used as the current limiting element in the above description, the present invention is not limited to this, and the same effect can be obtained by using a resistor, a constant current circuit, or the like.

(Embodiment 2) In the embodiment 1 shown in FIG. 1, the other electrodes of the load capacitors 8 to 11 are connected directly to the power supply voltage. However, as shown in FIG. 6 may be connected to the power supply voltage. In the figure, the same components as those in FIG. 1 are the same.

FIG. 4 is specifically explained.
The other electrode 10 is connected to the high potential side 5 via the transistor 4 constituting the current limiting element, and the other electrodes of the load capacitors 9 and 11 are connected to the low potential side 7 via the transistor 6 constituting the current limiting element. Connected to

FIG. 5 shows an actual oscillation (30M) in the configuration of FIG.
(Hz) is an explanatory diagram showing a power supply voltage waveform when performing the above. Note that a to c in the figure show voltage waveforms at the terminals a to c shown in FIG.

Compared with FIG. 2, which is the waveform diagram of the first embodiment, when the output (c) of the CMOS inverter 1 is set to substantially the same level, the magnitude of the fluctuation of the power supply voltage is larger in FIG. It is getting smaller.

More specifically, in FIG. 2A (the high potential side of the power supply) in the first embodiment, the magnitude of the fluctuation is 0.00007 V at the maximum.
On the other hand, in FIG. 5A (the high potential side of the power supply) in the second embodiment, the maximum is 0.00004V, and the magnitude of the fluctuation is small. FIG. 2C of the first embodiment.
(Low potential side of the power supply) The magnitude of the swing is 0.1 mV at maximum.
On the other hand, in FIG. 5C (the low potential side of the power supply) of the second embodiment, the maximum is 0.05 mV, and the magnitude of the fluctuation is small.

As described above, the other electrodes of the load capacitors 8 and 10 are connected to the high potential side 5 via the transistor 4, and the other electrodes of the load capacitors 9 and 11 are connected to the low potential side 7 via the transistor 6. Since it is connected, that is, the load capacitance is not directly connected to the power supply voltage, the fluctuation of the power supply voltage synchronized with the oscillation can be reduced as compared with the case of the first embodiment. In addition, when connecting the load capacitors 8 to 11 to the power supply voltage, the noise generated from the power supply side adversely affects the oscillation because the load capacitors 8 to 11 are connected via only the current limiting element without using a new capacitive element. Can be reduced.

Although a transistor is used as a current limiting element in the above description, the present invention is not limited to this, and similar effects can be obtained by using a resistor or a constant current circuit as in the first embodiment.

(Embodiment 3) Next, an example in which a plurality of switching elements are connected in parallel to a current limiting element and these switching elements are controlled in accordance with the output of the CMOS inverter 1 will be described with reference to FIG. explain.

Referring to FIG. 1, reference numerals 12 and 13 denote current limiting elements, each comprising a plurality of transistors 14 to 14 connected in parallel. Note that the transistors 14 to 14 constitute a switching element. A control circuit 15 is a detection circuit 16 described later.
On / off of the transistors 14 to 14 is controlled in accordance with the output of the CMOS inverter 1 detected by the inverter. Reference numeral 16 denotes a detection circuit for detecting the amplitude of the oscillation output from the CMOS inverter 1. The output value differs between when an amplitude equal to or larger than a specified value is obtained and when it is not.

According to the above configuration, the current supplied to the CMOS inverter 1 can be appropriately adjusted according to the number of the transistors 14 to 14 to be turned on, and the optimal current adjustment can be performed. For example, when oscillation starts, that is, when the CMOS inverter 1
When the amplitude of the oscillation output of the
4 to 14 are turned on so that a large amount of current flows to the oscillation circuit. When the detection circuit 16 detects that oscillation has become stable and a certain magnitude of amplitude has been maintained, a current of a predetermined value flows. By setting the on / off states of the transistors 14 to 14 in a predetermined state as described above, the time required from the start of oscillation to the stabilization of oscillation can be shortened, and the responsiveness can be improved.

In the above description, a plurality of transistors connected in parallel are used as switching elements constituting a current limiting element. However, the present invention is not limited to this. For example, a plurality of constant current circuits each including a plurality of transistors may be connected in parallel. You may. In this case, if the gate voltage of the transistor constituting the constant current circuit is controlled by the control circuit 15, the same effect as described above can be obtained. Further, in the case where the current is limited by a plurality of resistors connected in parallel, a switching element is provided in series with each of the resistors, and the on / off of the switching element is controlled by the control circuit 15, thereby producing the same effect as described above.

In the above description, a plurality of switching elements are connected in parallel, and the switching elements are appropriately controlled by the output of the detection circuit 16. However, depending on design requirements and the like, one current limiting element may be used, and The same effect can be obtained even if control is performed by continuously changing, for example, the gate voltage value of this one element by the output.

As the detection circuit 16, for example, those shown in FIGS. 7 and 8 may be used. FIG. 7 shows the terminal X
The input of the output of the CMOS inverter 1 is input from the terminal Y, and a detection signal is output to the control circuit 15 from the terminal Y. More specifically, a voltage level to be detected is set based on the inversion potential (threshold) of the inverter 17, and its operation is described in detail in Japanese Patent Application Laid-Open No. 7-193428, and a description thereof will be omitted. In the figure, 18 is a P-channel MOS transistor, 19 is a resistor, 20 is a capacitor, and 21 is an inverter.

In FIG. 7, the CM input from the terminal X is used.
When the oscillation output voltage of the OS inverter 1 has a large amplitude,
The time during which a through current flows through the inverter 17 is short. However, when the oscillation output voltage of the CMOS inverter 1 input from the terminal X has a small amplitude, the time required for the through current to flow through the inverter 17 becomes long, which causes a problem when low current consumption is required in design.

Further, since the threshold value of the inverter 17 is generally determined by the size of the transistor constituting the same, when changing the threshold value, the size of the transistor must be changed.

FIG. 8 shows an example in which a differential amplifier circuit is used in place of the inverter 17 and current limiting means is connected to the inverter 17 in order to solve the above-mentioned problem of the inverter 17 shown in FIG. That is, by inputting the oscillation output to one input of the differential amplifier circuit and inputting the comparison reference voltage used for determining the oscillation level to the other input, and connecting to the power supply via the current control means, Oscillation outputs of different levels can be detected with the same configuration, and current consumption can be reduced.

FIG. 8A shows an example of a differential amplifier circuit used in place of the inverter 17 in FIG.

In FIG. 8A, reference numeral 22 denotes a current mirror circuit, which includes a pair of P-channel MOS transistors 23;
24. The sources of the transistors 23 and 24 are connected to the high potential side 5 respectively. The drain of the transistor 23 is connected to the gates of the transistors 23 and 24,
Further, it is connected to the drain of the N-channel MOS transistor 25. To the gate of the transistor 25, a comparison reference voltage for setting a threshold value for judging a voltage level inputted via the terminal A is inputted. The source of the transistor 25 is connected to the source of the N-channel MOS transistor 26 and to the low potential side 7 via current limiting means 27 as a constant current source composed of a transistor or the like.
The drain of the transistor 26 is connected to the drain of the transistor 24 and to the gate of the transistor 18 shown in FIG. 7 via the terminal Z. The output of the CMOS inverter 1 is input to the gate of the transistor 26 from the terminal X.

The operation of FIG. 8A will be briefly described. When a comparison reference voltage supplied to the gate of the transistor 25 is input via the terminal A, a threshold value according to the voltage is set, and the voltage level of the oscillation output input via the terminal X is compared. If the voltage exceeds the threshold, the voltage at terminal Z drops. If the voltage level of the oscillation output input via the terminal X does not exceed the threshold value, the terminal Z is kept at a high potential.

Therefore, when the inverter 17 is replaced with the differential amplifier circuit shown in FIG. 8A in the detection circuit shown in FIG. 7, the voltage level of the oscillation output input via the terminal X is lower than the threshold value. When it repeatedly exceeds, the capacitor 20 is gradually charged, the output of the inverter 21 is inverted, and the detection output “0” is generated. Conversely, if the voltage level of the oscillation output input via terminal X does not exceed its threshold, terminal Z is held at a high potential and transistor 18 is turned off,
The capacitor 20 is not charged, and the inverter 21 does not output the detection output “0”.

FIG. 8B shows another example of the detection circuit 16 using the differential amplifier circuit shown in FIG. 8A. In this example, the signal input to the terminal B controls the current flowing through the differential amplifier circuit shown in FIG. 8A to control ON / OFF of the differential amplifier circuit, and the capacitor 20 is charged. It also controls the discharge of charges. In the figure, those having the same numbers as those in the previous figure are the same.

In the figure, reference numeral 28 denotes a voltage source, which outputs a comparison reference voltage to the gate of the transistor 25. 29 is an inverter, 30 is a P-channel MOS transistor, 3
Reference numerals 1 and 32 are N-channel MOS transistors.

In brief, the operation is as follows. At the time of standby, a signal "1" is input to the terminal B, whereby the voltage source 28
The P-channel MOS transistor 28a is turned off, and the transistor 32 is turned on, thereby discharging the charge stored in the capacitor 20 to initialize the capacitor 20. Therefore, at this time, that is, during standby,
Since the input of the inverter 21 becomes "0", the output terminal Y outputs "1". At this time, the inverted output “0” from the inverter 29 causes the transistor 27
Is turned off, and no current flows through the differential amplifier circuit shown in FIG. Therefore, at the time of standby, unnecessary current does not flow through the circuit shown in FIG. 8A, so that current consumption can be reduced. Further, the transistor 30 is turned on by the inverted output “0” from the inverter 29, and accordingly, the transistor 1
8 turns off. Further, since the voltage source 28 is off, the transistor 31 is also off. Therefore, the capacitor 20
The charging operation to is stopped. Therefore, the disadvantage that the capacitor 20 is unnecessarily charged at the time of standby can be solved, and the current consumption can be reduced.

When a signal "0" is inputted to the terminal B in the operating state, the transistor 32 is turned off, the initialization of the capacitor 20 is stopped, and the voltage source 28 is turned on to apply the comparison reference voltage to the gate of the transistor 25. At the same time, the transistor 31 is turned on. The transistor 27 is operated by the inverted output “1” from the inverter 29 and the transistor 30 is turned off, so that the circuit shown in FIG. When the output of the CMOS inverter 1 is input from the terminal X in this state, the same operation as described above is performed.

As described above, when the differential amplifier circuit shown in FIG. 8A is employed, the threshold value can be easily changed by changing the comparison reference voltage input to the gate of the transistor 25. Further, the comparison reference voltage can be adjusted by a signal from another circuit block of the IC,
The voltage may be adjusted by applying a voltage directly from outside the IC. For example, as shown in FIG. 9, a plurality of resistors 33 to 33 are connected in series between the power supplies, and one of the connection points of the resistors 33 is connected to the gate of the transistor 25 shown in FIG. In this way, the other connection points are connected to a power supply via the transistors 34 to 34, respectively, and the gate of the transistor 34 is controlled by a binary signal from another circuit block in the IC or a binary signal from outside the IC. May be adjusted digitally. FIG.
0, a resistor 35 and a transistor 36 are connected between the power sources, and the connection point is connected to the transistor 25 shown in FIG.
By controlling the gate of the transistor 36 with an analog signal from another circuit block in the IC or an analog signal from outside the IC,
The comparison reference voltage may be adjusted in an analog manner.

In the above description, the differential amplifier circuit shown in FIG.
Although the circuit shown in FIG. 1A was used, the differential amplifier circuit is not limited to this. For example, those shown in FIGS. 11A, 11B, and 11C may be used. In the figure, 37 is an active load, 38 and 39 are resistors, 40 and 41 are P-channel MOS transistors, and 42 and 43 are N-channel MOS transistors. I do.

In the second and third embodiments, the current limiting elements are provided on both the high potential side and the low potential side, but they may be provided on only one of them according to design requirements.

[0051]

According to the present invention, the fluctuation of the power supply voltage synchronized with the oscillation can be reduced while realizing low current consumption.

One electrode has a first load capacitance connected to the input side of the CMOS inverter and one electrode has a CMOS
A third load capacitance connected to the output side of the inverter and one power supply side of the CMOS inverter are connected to one power supply voltage via the first current limiting element, and one electrode is connected to C
The second load capacitance connected to the input side of the MOS inverter, the fourth load capacitance whose one electrode is connected to the output side of the CMOS inverter, and the other power supply side of the CMOS inverter are connected to a second current limiting element. Is connected to the other power supply voltage via the first and second current limiting elements which can further reduce fluctuations of the power supply voltage synchronized with oscillation while realizing low current consumption. These switching elements are controlled by a control circuit in accordance with the output of the CMOS inverter.
The adjustment of the current limiting element becomes possible, and the optimum adjustment becomes possible. Also, for example, when the oscillation starts, the switching element is controlled so that a large amount of current flows through these switching elements, and when the oscillation becomes stable, the switching element is controlled so that a current of a predetermined value flows. The time required for the oscillation to stabilize can be shortened, and the responsiveness can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing voltage waveforms when the circuit of FIG. 1 is operated.

FIG. 3 is an explanatory diagram showing voltage waveforms when the circuit of FIG. 12 is operated.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is an explanatory diagram showing voltage waveforms when the circuit of FIG. 4 is operated.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

FIG. 7 is a circuit diagram showing the detection circuit of FIG. 6;

FIG. 8 is a circuit diagram showing a main part of another detection circuit in FIG. 6;

FIG. 9 is a circuit diagram showing another example of the voltage sources of FIGS.

FIG. 10 is a circuit diagram showing another example of the voltage sources of FIGS.

FIG. 11 is a circuit diagram showing a main part of another detection circuit in FIG. 6;

FIG. 12 is a circuit diagram showing a configuration of a conventional oscillation circuit.

[Explanation of symbols]

 Reference Signs List 1 CMOS inverter 2 Piezoelectric element 3 Feedback resistor 4 First current control element 5 One power supply voltage 6 Second current control element 7 The other power supply voltage 8 First load capacitance 9 Second load capacitance 10 Third load Capacitance 11 Fourth load capacitance 12 Current limiting element 13 Current limiting element 14 Switching element 15 Control circuit

Continuation of the front page (56) References JP-A-7-193428 (JP, A) JP-A-57-55601 (JP, A) JP-A-2-107008 (JP, A) JP-A-1-94704 (JP) , A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03B 5/32 H03B 5/04

Claims (7)

(57) [Claims] 1. A CMOS inverter, a piezoelectric element and a feedback resistor respectively connected between input and output terminals of the CMOS inverter, and a first load connected between an input side of the CMOS inverter and one power supply potential. Capacitance, a second load capacitance connected between the input side of the CMOS inverter and the other power supply potential, and a third load capacitance connected between the output side of the CMOS inverter and the one power supply potential And a fourth load capacitor connected between the output side of the CMOS inverter and the other power supply potential. 2. The power supply according to claim 1, wherein the first and third load capacitors and one power supply side of the CMOS inverter are connected to the one power supply voltage via a first current limiting element. An oscillator circuit, wherein the fourth load capacitance and the other power supply side of the CMOS inverter are connected to the other power supply voltage via a second current limiting element. 3. The method of claim 2, wherein the first and second
Wherein the current limiting element is a resistor. 4. The method according to claim 2, wherein the first and second
The current limiting element is a transistor. 5. The method according to claim 2, wherein
Wherein the current limiting element is a constant current circuit. 6. The method according to claim 2, wherein
Wherein the current limiting element comprises a plurality of switching elements connected in parallel, and further comprises a control circuit for controlling the switching elements according to the output of the CMOS inverter. 7. The oscillation circuit according to claim 6, wherein the switching element is a transistor.