JPH09212247A - Referrence voltage generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit capable of preventing the oscillation of output voltage and reducing power consumption. SOLUTION: This reference voltage generation circuit is constituted of comparators 1, 2, 5, a PMOS transistor(TR) 3, NMOS TR 4, and a bias current adjusting circuit 6 for receiving a comparison output from the comparator 5 and controlling the bias currents of the comparators 1, 2. Voltage inputs V1 , V2 from input terminals 7, 8 are respectively inputted to the positive phase input terminals of the comparators 1, 2 and output voltage V0 is fed back and inputted to the reverse phase input terminals of the comparators 1, 2. Voltage outputs from the comparators 1, 2 are respectively inputted to the gates of the TRs 4, 3, voltage V3 from an input terminal 9 is inputted to the positive phase input terminal of the comparator 5, the output voltage V0 is inputted to the reverse phase input therminal of the comparator 5, and the circuit 6 executes current control action based upon the comparison output from the comparator 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit.

[0002]

2. Description of the Related Art One example of a conventional reference voltage generating circuit is shown in FIG. As shown in FIG. 4, in this conventional example, the comparators 1 and 2 and the PMOSs corresponding to these comparators are used.
The voltage V ₁ and V ₂ input from the input terminals 7 and 8 are input to the positive-phase input terminals of the comparators 1 and 2, respectively, and these transistors 3 and the NMOS transistor 4 are input. The output voltage V ₀ is fed back to the negative-phase input terminals of the comparators 1 and 2. The output voltages of the comparators 1 and 2 are input to the gate of the NMOS transistor 4 and the gate of the PMOS transistor 3, which form an output circuit, respectively. With such a circuit configuration, the output voltage V ₀ of the reference voltage generating circuit at the output terminal 12 becomes an intermediate potential between the voltages V ₁ and V ₂ input to the input terminals 7 and 8. 5 and 6 are characteristic diagrams showing an operation example of this conventional example. In the following, FIG. 4, FIG. 5 and FIG.
The operation of this conventional example will be described with reference to FIG.

In FIG. 4, when a capacitive load is connected as the load of the output terminal 12 and the capacitive load is externally charged, the output voltage V ₀ of the output terminal 12 is input. A state is reached in which the level of the voltage V ₁ is about to be exceeded. Now, let this time be t ₁ (see FIG. 5). Further, when the output voltage V _O rises to the potential of V ₁ + ΔV ₁ (time t ₂ : see FIG. 5), the feedback voltage V ₀ is input to the negative-phase input terminal and the potential of the output voltage V _O is received. The output of the comparator 1 is output as a high level signal and is input to the gate of the NMOS transistor 4 in an attempt to reduce the voltage to V ₁ or less. As a result, the NMOS transistor 4 is turned on, and the potential of the output voltage V _O is lowered with time as shown in FIG. Then, the potential level of the output voltage V _O is equal to the input voltage V _O
At time t ₃ when the potential has fallen to an intermediate potential between ₁ and V ₂ , the output level of the comparator 1 is output as a low level signal, whereby the NMOS transistor 4 is turned off and the output voltage V _O is Settle to an intermediate potential between the voltages V ₁ and V ₂ .

Next, when the electric charge accumulated in the capacitive load connected as the load of the output terminal 12 is discharged, the potential of the output voltage V _O lowers to the voltage V ₂
Approach potential. This time is t ₃ (see FIG. 5).
Furthermore, decreases the output voltage V _O is, V ₂ - △ drops to the potential of V ₂ (time t _4: see FIG. 5), the output voltage V _O to V
The output of the comparator 2 is output as a low level signal and is input to the gate of the PMOS transistor 3 in an attempt to raise the potential to ₂ or more. As a result, the PMOS transistor 3 is turned on, and the potential of the output voltage V _O is raised with time as shown in FIG. Then, the potential level of the output voltage V _O is equal to the input voltage V _O
At time t ₅ when the potential has fallen to an intermediate potential between ₁ and V ₂ , the output level of the comparator 2 is output as a high level signal, whereby the PMOS transistor 3 is turned off and the output voltage V _O , Settle at an intermediate potential between the voltages V ₁ and V ₂ .

As an example in which the capacitive load is connected to the reference voltage output terminal as described above and the output voltage V _O fluctuates under the influence of this, the reference voltage used in the drive power source of the liquid crystal driver is shown. Found in generator circuits. An example of the reference voltage generating circuit used in the LCD driving power source is proposed in Japanese Patent Application Laid-Open No. 4-255008, and the reference voltage generating circuit shown in FIG. This is a reference according to Japanese Patent Publication No. 255008.

[0006]

In the above-mentioned conventional reference voltage generating circuit, the comparison response speed is determined by the steady currents flowing in the comparators 1 and 2 shown in FIG.
Therefore, the steady current itself also varies due to variations in processes and the like. In FIG. 4, the output terminal 12
When the charge is externally charged against the connected load, at a time t ₁₁ (see FIG. 6), the potential V _O of the output terminal 12 exceeds the potential level of V _1, the potential V _O and V
_It continues to rise until it reaches the potential of ₁ + ΔV ₁ (time t ₁₂ ). Then, at time t ₁₂ , the operation of the comparator 1 is started so that the potential of V _O becomes equal to or lower than the potential of V _{1 for} the first time, and a high level signal is output and applied to the gate of the NMOS transistor 4. In response to this, the NMOS transistor 4 is turned on, and the level of the potential V _O of the output terminal 12 is lowered. After that, the level of the potential V _O continues to decrease, and decreases to the potential of V ₁ at time t _13.
In, the level of the output signal of the comparator 1 shifts to the low level and is input to the gate of the NMOS transistor 4. As a result, the operating state of the NMOS transistor 4 tries to shift to the off state, but since the comparison response speed of the comparator 1 is slow, the time t at which the potential of V _O drops to a potential lower than that of V _{2. At 14} , for the first time, the level of the output signal of the comparator 2 shifts to the low level and is input to the gate of the PMOS transistor 3, the level of the output signal of the comparator 2 becomes the low level, and the NMOS transistor 4
Is turned off.

Then, the output voltage V _O falls below the level of the potential V ₂ , and the comparator 2 tries to shift to a state in which a low level is output.
P is due to a slow comparison response speed, up to the time t ₁₅
The MOS transistor 3 is not turned on. Then at time t _15, is output first time as a level low level output signal of the comparator 2, PMOS transistor 3 are turned on, thereby the potential of the output voltage V _O rises, V is at time t ₁₆ The potential reaches ₁ + ΔV ₁ . Then, at the time t ₁₇ , the potential of V _O decreases with the ON state of the NMOS transistor 4 as in the case described above. This operating state is as shown in FIG.

As described above, when the potential of the output voltage V _O once becomes the potential higher than the level of V ₁ or the potential lower than the level of V ₂ , if the operating current of the comparator is not optimum, the comparison operation delays. As shown in FIG. 6, the potential of the output voltage V _O does not fall between the potentials of V ₁ and V ₂ and is in an oscillating state, and the PMOS transistor 3 and the NMOS transistor 4 are turned on for a long time. Then, there is a drawback that the current consumption increases.

Further, the output of the reference power supply voltage is in a state where a ripple voltage is superimposed on the direct current voltage due to oscillation, and when used as a power supply for a liquid crystal driver, there is a drawback that "flicker" occurs on the liquid crystal screen.

[0010]

In the reference voltage generating circuit of the present invention, the first set voltage is input to the positive phase input terminal and the predetermined reference output voltage is fed back to the negative phase input terminal. The voltage connecting means, the second voltage comparing means to which the second set voltage is input to the positive phase input terminal and the reference output voltage to the negative phase input terminal are fed back, and the source are connected to a predetermined high potential power source. A voltage comparison output from the second voltage comparison means is input to the gate, a drain is connected to the output terminal of the reference output voltage, and a drain is connected to the drain of the PMOS transistor;
The voltage comparison output by the first voltage comparison means is input to the gate, and the source is connected to a predetermined low potential power supply N.
A MOS transistor, a third voltage comparison means in which the third set voltage is input to the positive phase input terminal, and the reference output voltage is input to the negative phase input terminal, and a voltage comparison output by the third voltage comparison means. And a bias current adjusting means for generating and outputting a signal for controlling and adjusting the bias currents in the first and second voltage comparing means, the reference output voltage being a desired reference voltage. It is characterized by outputting as.

The first, second and third set voltages may be generated by resistance division of a predetermined DC voltage.

The bias current adjusting means inputs the D flip-flop for holding the voltage level of the voltage comparison output by the third voltage comparing means, the voltage comparison output by the third voltage comparing means and the clock signal. An up-counter for counting and counting, a down-counter set by the level signal held in the D flip-flop and counting by inputting a voltage comparison output by the third voltage comparing means and a clock signal, and the up-counter A first OR gate that outputs a logical sum of the first and second level signals output from the first and a second AND that outputs a logical product of the first and second level signals output from the up counter. A second AND for outputting a logical product of the gate and the first and second level signals output from the down counter Gate, a second OR gate for outputting a logical sum of the first and second level signals output from the down counter, and a drain connected to a predetermined high potential power source, and the gate has the first OR gate. A first NMOS transistor to which an output signal of the gate is input; and a drain connected to a source of the first NMOS transistor,
A second NMOS transistor having a gate to which the second level signal output from the up counter is input, a drain connected to a source of the second NMOS transistor, and a gate having an output signal from the first AND gate Is input to the third NMOS transistor, the source is connected to the source of the third NMOS transistor, and the gate is connected to the output signal of the second AND gate. First P
A second PMOS transistor connected to the drain of the MOS transistor, the gate of which receives the second level signal output from the down counter, and the source of which is connected to the drain of the second PMOS transistor, and the gate of which is A third PMOS transistor to which the output signal of the second OR gate is input, drain-source of the first, second and third NMOS transistors, and the first, second and third PMOS transistors And a voltage dividing resistor connected between the drain and the source of the third PMOS transistor, respectively, and a voltage dividing resistor connected between the drain of the third PMOS transistor and a predetermined low potential power source. And the third NMO
A connection point between the source of the S transistor and the source of the first PMOS transistor may be connected to the signal output terminal for controlling the bias current.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG.
The comparators 1, 2 and 5, the PMOS transistor 3 and the NMOS transistor 4 corresponding to the comparison outputs of the comparators 1 and 2, and the comparison output of the comparator 5 receive the comparator 1
And a bias current adjusting circuit 6 for controlling and adjusting the bias currents of 2 and 2, and the voltages V ₁ and V ₂ input from the input terminals 7 and 8 are positive phase inputs of the comparators 1 and 2, respectively. The output voltage V ₀ is input to the terminals, and the negative-phase input terminals of these comparators 1 and 2 have an output voltage V _0.
Has been input as feedback. The output voltages of the comparators 1 and 2 are input to the gate of the NMOS transistor 4 and the gate of the PMOS transistor 3, which form an output circuit, respectively. Furthermore, the voltage V ₃ input from the input terminal 9 is input to the positive phase input terminal of the comparator 5, and the output voltage V ₀ is input to the negative phase input terminal.

FIG. 3 is a circuit diagram showing the configuration of one embodiment of the bias current adjusting circuit 6 in this embodiment, which is connected to the comparison input terminal 40 to which the comparison output signal from the comparator 5 is input. D flip-flop 19, 2-bit up counter 20 and 2-bit down counter 2
1, OR gates 22 and 25, and AND gate 23
And 24, resistors 32 to 39 connected in series between power supply terminals 43 and 44, NMOS transistors 26, 27 and 28 connected in parallel to resistors 32, 33 and 34, and a resistor 35, respectively. 36 and 37, and PMOS transistors 29, 30 and 31 connected in parallel. A power supply voltage having a higher potential than the power supply voltage supplied to the power supply terminal 44 is supplied to the power supply terminal 43, and the 2-bit up counter 20 and the 2-bit down counter 21 are supplied from the clock input terminal 41. Is supplied with a control clock for count timing, and the clock cycle is set to a value approximately equal to the response speed of the comparator 5 in FIG. Further, the set signal for the D flip-flop 19 and the 2-bit down counter 21 is supplied to the set terminal 42.

Next, the operation of this embodiment will be described with reference to FIG. Note that, in the present embodiment, the operation when the output voltage V _O does not oscillate is the same as in the case of the above-described conventional example, so in the following description of the operation, the output of the reference voltage generation circuit oscillates. The operation of the case will be described.

In FIG. 1, when the output of the reference voltage generating circuit oscillates, the output voltage V _O is
A potential higher than the potential level of the input voltage V ₁ ,
Alternatively, since the potential is lower than the potential level of the voltage V ₂ input from the input terminal 8, the potential of the positive-phase input terminal of the comparator 5 is higher than the potential level of the voltage V ₁ or higher than the potential level of the voltage V ₂ . One of the potentials lower than the potential level is
The voltage V ₃ is supplied from the input terminal 9. Note that, here, for convenience of explanation, the potential of the voltage V ₃ is the voltage V _3.
It is assumed that the voltage has a potential higher than ₁ . Output terminal 1
2 causes the output voltage V _O to oscillate, and the output voltage V _O
When the potential level of V exceeds the potential level of the voltage V ₁ and further exceeds the potential level of the voltage V ₃ , the comparator 5
Outputs a high level signal as a comparison output from the input terminal to the bias current adjusting circuit 6. The bias current adjusting circuit 6 receives the high level signal, generates and outputs a bias current control signal for the comparators 1 and 2, and inputs the bias current control signal to the respective comparators.
In the comparators 1 and 2, controlled by this bias current control signal, the bias current in each of them is increased, and thereby the comparison operation speed in these comparators 1 and 2 is improved, so that the reference voltage concerned is increased. The oscillating condition of the generation circuit is avoided, and the oscillating operation at the output terminal 12 is suppressed.

Next, a method of adjusting the bias currents supplied to the comparators 1 and 2 by the bias current adjusting circuit 6 will be described with reference to FIG. In FIG. 3, when a high-level comparison output signal is input from the comparator 5 to the comparison input terminal 40, the 2-bit up counter 20 counts up, and the output terminals A and B thereof , A high-level signal and a low-level signal are output and input to the corresponding OR gate 22 and AND gate 23, respectively. As a result, a high level signal is output from the OR gate 22 and input to the gate of the NMOS transistor 26, and the AND gate 23
Outputs a low level signal to the gate of the NMOS transistor 27. In this state,
A high-level signal is input only to the gate of the NMOS transistor 26, and the other NMOS transistor 27
A low level signal is input to the gates of 28 and 28. Therefore, only the NMOS transistor 26 is turned on and the resistor 32 is short-circuited. On the other hand, when a high-level comparison output signal is input from the comparator 5 to the comparison input terminal 40, the 2-bit down counter 21 does not count down, and the output terminal A and the output terminal B thereof do not count down. , A high level signal is output, and is input to the corresponding AND gate 24 and OR gate 25. As a result, the PMOS transistor 29,
High level signals are input to the gates of 30 and 31, respectively, and all of these PMOS transistors are turned off. As a result, the potential level of the bias current control signal output from the control output terminal 45 rises.
This bias current control signal is input to the gates of NMOS transistors (not shown) included in the comparators 1 and 2. In the comparators 1 and 2, the NMO
As the gate input voltage of the S transistor increases, the current of these NMOS transistors increases, and the bias current increases, which improves the comparison response speed in the comparators 1 and 2 and increases the output terminal 1
The oscillation state in 2 is suppressed. Due to this oscillation suppression, when the comparator 5 outputs the low-level comparison output signal and the comparison input signal is input to the comparison input terminal 40,
A high level signal is input to the gate of the MOS transistor 26, and the MOS transistor 26 is held in the ON state. In addition, the NM included in the above comparators 1 and 2
When the oscillation state is not suppressed in response to the increase in the current in the OS transistor and the high-level comparison output signal is input again from the comparator 5, the 2-bit up counter 20 performs counting up again. By N
Both the MOS transistors 26 and 27 are turned on, the potential level of the bias current control signal output from the control output terminal 45 is further increased and input to the comparators 1 and 2, and the bias current in these comparators is increased. As a result, the oscillation at the output terminal 12 is suppressed.

Next, when the comparator 5 is not in the oscillation state,
The operation in which the consumption current is optimized by suppressing the bias current in the comparators 1 and 2 will be described. First, a low-level comparison output signal is output from the comparator 5, and the comparison input terminal 40 of the bias current adjusting circuit 6 is output.
Is input to the NOR gate 22 and the AND gate 23, the 2-bit up counter 20 does not count up, and low-level signals are output from the output terminals A and B of the 2-bit up counter 20.
To the NMOS transistor 26,
27 and 28 are all turned off. On the one hand,
In the 2-bit down counter 21, a countdown is performed in response to the input of the low-level comparison output signal from the comparator 5, the low-level signal is output from the output terminal A of the 2-bit down counter 21, and the output terminal B is output. Outputs a high level signal from the AND gate 24 and the NOR gate 25, respectively. As a result, only the PMOS transistor 29 is turned on,
The other PMOS transistors 30 and 31 are turned off. Due to the operating states of the NMOS transistors 26 to 28 and the PMOS transistors 29 to 31,
The potential at the control output terminal 45 falls, and upon receipt of this bias current control signal, the bias current flowing in the comparators 1 and 2 is reduced,
The current value is suppressed.

As described above, when the bias current is reduced, the comparison output signal of the comparator 5 which is in an oscillating state is again output as a high level signal in response to the comparison output by the comparators 1 and 2. , Is input to the comparison input terminal 40 of the bias current adjusting circuit 6. At that time, the high-level signal latched by the D flip-flop 19 is input to the set terminal 42 of the 2-bit down counter 21, and the output of the 2-bit down counter 21 is held. Even if the low-level comparison input signal is input from the comparator 5, the countdown is not performed. On the other hand, the 2-bit up counter 20 receives the high-level comparison output signal and performs counter up, and as described above, the potential of the control output terminal 45 of the bias current adjusting circuit 6 rises,
Due to the level increase of the bias current control signal, the oscillation state at the output end of the comparator 5 is stopped.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the second embodiment. As shown in FIG. 2, this embodiment is
The comparators 1, 2 and 5, the PMOS transistor 3 and the NMOS transistor 4 corresponding to the comparison outputs of the comparators 1 and 2, and the comparison output of the comparator 5 receive the comparator 1
And a bias current adjusting circuit 6 for controlling and adjusting the bias currents 2 and 2, and resistors 13, 14, 15 and 16 for setting the potentials of the positive-phase input terminals of the comparators 1, 2 and 5, respectively. The voltages V ₁ and V ₂ generated by dividing the power supply voltage supplied to the power supply terminals 17 and 18 are input to the positive-phase input terminals of the comparators 1 and 2, respectively. Then, as in the case of the first embodiment,
The output voltage V ₀ is fed back and input to the negative-phase input terminals of the comparators 1 and 2, and the output voltages of the comparators 1 and 2 are respectively the gate of the NMOS transistor 4 forming the output circuit and the PMOS. It is input to the gate of the transistor 3. Furthermore, the divided voltage V ₃ is input to the positive phase input terminal of the comparator 5, and the output voltage V ₀ is input to the negative phase input terminal. Further, the internal configuration and function of the bias current adjusting circuit are similar to those in the above-described first embodiment.

That is, the difference from the first embodiment is the difference in the method of setting the input voltages V ₁ , V ₂ and V ₃ with respect to the positive phase input terminals of the comparators 1, 2 and 5, and the other operation. The contents are exactly the same as in the case of the first embodiment. The description of the operation of this embodiment will be omitted because it overlaps with that of the first embodiment.

[0023]

As described above, according to the present invention, the level comparing means for comparing the level of the predetermined set voltage with the level of the reference output voltage, and the bias current adjusting means for receiving the comparison output of the comparing means as an input. Is added, and the bias current in the first and second level comparing means for comparing the feedback input of the reference output voltage with a predetermined set voltage is controlled and adjusted, thereby effectively activating the oscillation state at the reference voltage output terminal. In addition to being able to stop the operation, it is possible to constantly optimize the bias currents in the first and second level comparing means, and it is possible to suppress the consumption current.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a bias current adjusting circuit in the first and second embodiments.

FIG. 4 is a configuration diagram showing a conventional example.

FIG. 5 is a characteristic diagram (1) showing an operation state of a conventional example.

FIG. 6 is a characteristic diagram (2) showing an operation state of a conventional example.

[Explanation of symbols]

 1, 2, 5 Comparator 3, 29-31 PMOS transistor 4, 26-28 NMOS transistor 6 Bias current adjusting circuit 7-9 Input terminal 10, 11, 17, 18, 43, 44 Power supply terminal 12 Output terminal 13-16 , 32-39 resistors 19 D flip-flops 20 2-bit up counters 21 2-bit down counters 22, 25 OR gates 23, 24 AND gates 40 comparison input terminals 41 clock input terminals 42 set terminals 45 control output terminals

Claims (3)

[Claims] 1. A first voltage comparison means for inputting a first set voltage to a positive phase input terminal and a predetermined reference output voltage for feedback input to a negative phase input terminal, and a second voltage comparison means for a positive phase input terminal. Second voltage comparison means to which a set voltage is input and the reference output voltage is fed back to the negative phase input terminal, and a source is connected to a predetermined high-potential power supply and a gate to which the voltage by the second voltage comparison means is applied. PM to which the comparison output is input and whose drain is connected to the output terminal of the reference output voltage
An OS transistor, an NMOS transistor having a drain connected to the drain of the PMOS transistor, a gate to which a voltage comparison output from the first voltage comparison means is input, and a source connected to a predetermined low-potential power supply; The third setting voltage is input to the input terminal and the reference output voltage is input to the anti-phase input terminal, and the voltage comparison output by the third voltage comparison means is input, Bias current adjusting means for generating and outputting a signal for controlling and adjusting the bias current in the first and second voltage comparing means, and outputting the reference output voltage as a desired reference voltage. Reference voltage generating circuit. 2. The reference voltage generating circuit according to claim 1, wherein the first, second and third set voltages are generated by resistance division of a predetermined DC voltage. 3. The bias current adjusting means comprises:
D flip-flop for holding the voltage level of the voltage comparison output by the voltage comparison means, an up-counter for inputting and counting the voltage comparison output by the third voltage comparison means and a clock signal, and the D flip-flop A level counter which is set by the level signal of the third voltage comparator and which receives and counts the voltage comparison output by the third voltage comparator and the clock signal, and a logical sum of the first and second level signals output from the up counter. A first AND gate that outputs a logical product of the first and second level signals that are output from the up counter, and a first and second output that is output from the down counter. Second AND gate that outputs the logical product of the level signals of the A second OR gate for outputting a logical sum of the second-level signal, a drain connected to a predetermined high potential power source, a first NMO output signal of the first OR gate is input to the gate
An S transistor, a second NMOS transistor having a drain connected to the source of the first NMOS transistor, and having a gate to which the second level signal output from the up counter is input; and a drain having the second NMOS transistor A third NMOS transistor connected to the source of the transistor, the gate of which receives the output signal of the first AND gate; and the source of which is connected to the source of the third NMOS transistor and the gate of which is the second AND transistor. A first PMOS transistor to which an output signal of the gate is input; and a source connected to a drain of the first PMOS transistor,
A second PMOS transistor having a gate to which the second level signal output from the down counter is input, a source connected to the drain of the second PMOS transistor, and a gate having an output signal from the second OR gate A third PMOS transistor to which is input, between the drain and source of the first, second and third NMOS transistors, and the first, second and third
A voltage dividing resistor individually connected between the drain and source of the PMOS transistor, and a voltage dividing resistor connected between the drain of the third PMOS transistor and a predetermined low potential power source, And a connection point between the source of the third NMOS transistor and the source of the first PMOS transistor is connected to the signal output terminal for controlling the bias current. Reference voltage generation circuit.