JPH11330475A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the i/f noise of a semiconductor device which is equipped with a MOSFET formed on an insulating substrate, such as an SOS or the like. SOLUTION: A source 20 (n<+> or n-type semiconductor) and a drain (n<+> or n-type semiconductor) 30 which are constituted of single-crystal silicon provided on a sapphire substrate 10 are made, and furthermore a gate oxide film 50, a p<+> -type polycrystalline silicon 60 which functions as an electrode, and an SiO2 layer 70 functioning as a protective film are stacked on the top of this single-crystalline silicon, and spacers 40a and 40b consisting of SiO2 are provided at both sides of the stack. This device is provided with a p<-> -type single- crystalline silicon 100, between the source 20 and the drain 30, and an n<-> -type single-crystalline silicon 110 hereon, and also a bias voltage 80 is applied so that the source side 20 is on the low potential side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for reducing noise in a semiconductor device having, for example, an SOS structure.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional MOSFET having an SOS structure.
FIG. 3 is a schematic explanatory view showing a cross-sectional structure of the MOSFE.
In T, a source 2 (n ⁺ , n-type semiconductor) and a drain (n ⁺ , n-type semiconductor) 3 composed of single-crystal silicon provided on the sapphire substrate 1 are formed.
A gate oxide film 5, n ⁺ -type polycrystalline silicon 6 functioning as an electrode, and a SiO ₂ layer 7
Are laminated, and spacers 4a and 4b are provided on both side surfaces of the laminated portion.

When a voltage is applied to the polycrystalline silicon 6, 1 p is applied to the p-type semiconductor region between the source 2 and the drain 3.
A channel 8 having a thickness of about 00 (Å) is formed, and a current flows between the source 2 and the drain 3 to perform a conduction operation. At this time, electrons are scattered at the interface between the gate oxide film 5 and the single-crystal silicon, and a large number of electrons drifting without remaining in the channel 8 are generated, and the interface between the sapphire substrate 1 and the single-crystal silicon is generated. Many drift electrons were trapped and detrapped.

[0004]

However, the fact that the scattering of electrons increases and the drift electrons are trapped and detrapped at the interface means that the fluctuation of the electrons increases, and this fluctuation is a noise source. Was.

In the prior art, the 1 / f noise was about 100 times as large as that of the bulk type. The present invention has been made to solve such a conventional problem, and an object of the present invention is to suppress 1 / f noise of a semiconductor device including a MOSFET formed on an insulating substrate such as an SOS. .

[0006]

In order to achieve the above-mentioned object, the invention according to claim 1 is directed to an M-type semiconductor device formed on an insulating substrate.
A semiconductor device including an OSFET, comprising: a source / drain region formed of a semiconductor of a first conductivity type; a gate region formed of a semiconductor of a second conductivity type different from the first conductivity type; And a channel-formable region formed of a semiconductor of a first conductivity type having an impurity concentration lower than that of the source / drain region and capable of forming a channel.

According to a second aspect of the present invention, in the first aspect, a region made of the second conductivity type semiconductor is formed below the channel formable region. I do.

According to the first and second aspects of the present invention, the channel layer formed in the channel-formable region becomes thicker, and a large amount of electrons flow deep in the channel-formable region. As a result of reducing noise generated by the fluctuation of electrons, 1 / f noise is reduced.

Further, the invention according to claim 3 is based on claim 2
Wherein a bias voltage is applied to a region formed of the second conductivity type semiconductor.

According to the present invention, by applying the bias voltage, for example, electrons drifted from the channel hardly reach the interface of the insulating substrate, and traps and detraps at the interface of the insulating substrate hardly occur.
Noise will be further reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. FIG. 1 is a cross-sectional view taken along a cutting line AA in FIG. Become. Note that, in the plan view, constituent elements (spacers and SiO ₂ layers described later) appearing in the cross-sectional views are omitted in the plan view for ease of understanding.

This semiconductor device is mounted on a sapphire substrate 10.
Composed of single-crystal silicon provided in
20 (n⁺, N-type semiconductor) and drain (n⁺, N-type semiconductive
Is formed, and the single crystal silicon
On the upper part, a gate oxide film 50, p functioning as an electrode⁺Type
Polycrystalline silicon 60, SiO functioning as protective film _Two
Layer 70 is laminated on both sides of the laminated portion._TwoFrom
Spacers 40a and 40b are provided.

Between the source 20 and the drain 30, there are provided a p ⁻ type single crystal silicon 100 and an n ⁻ type single crystal silicon 110 formed thereon, and a bias voltage 80. Are applied so that the source 20 side is on the low potential side.

As shown in FIG. 2, a contact hole 90 is provided in the polycrystalline silicon 60, and a body which is a p ⁺ -type region having a body contact electrode 94 serving as a bias voltage application electrode. The contact portion 93 is formed between the body contact portion 93 and the drain 30.
Depletion layer 92 for electrical insulation from (source 20)
And body contact portion 93 is located opposite to p ⁻ -type region 100.
Is electrically connected to

Next, a method of manufacturing a semiconductor device having such a structure will be described with reference to FIG. First, on the sapphire substrate 1, a thickness of 2000 is formed by epitaxial growth.
The single crystal silicon of (Å) is formed (FIG. 3A).

Next, an oxide film (SiO ₂ ) of 100 (１００) is formed on the single crystal, a desired pattern is masked with a mask member, and ion implantation is performed. 70 × 5 × 10 ¹² concentrations of ionized boron (B ⁺ ) per cm ²
(KeV) energy and 1c
1 × 10 ¹³ concentrations of ionized phosphorus (P ⁺ ) per m ²
Is implanted at an energy of 40 (keV). As a result, an n ⁻ region and ap ⁻ region below the n ⁻ region are formed (FIG. 3B). Note that ionized boron is implanted to adjust the threshold voltage, and ionized phosphorus is implanted to reduce the resistance of the sapphire-single-crystal silicon interface.

Next, the oxide film and the mask member formed in the previous step are removed, and the silicon surface is oxidized at 850 ° C. in an atmosphere of a mixed gas of hydrogen and oxygen to form a gate oxide film 50 having a thickness of 100 (Å). Is formed, and polycrystalline silicon 60 having a thickness of 3000 (Å) is formed thereon by CVD. Further, 5 × 10 ¹⁴ boron fluoride ions (BF ₂ ⁺ ) are implanted at an energy of 30 (keV) per cm ² (FIG. 3C).

Next, a thickness of 3000 (Å) is formed by CVD.
SiO_TwoTo deposit SiO_TwoA layer 70 is formed
After the electrode pattern is formed, 900 ° C. and nitrogen gas
Anneal in the atmosphere for 1 hour to obtain polycrystalline silicon
Activation of n60 and n ^-Region 110 and p^-Area 1
00 are mutually diffused. The diffusion coefficient of phosphorus and boron
Are almost the same and the concentration is higher for phosphorus as described above.
Region boundary is 300 from the sapphire-silicon interface
It is provided at a position of (Å) (FIG. 3D).

Next, ionized phosphorus (P ⁺ ) at a concentration of 1 × 10 ¹³ per 1 cm ² is ion-implanted at an energy of 60 (keV) to form n-type regions on both sides of the regions 100 and 110. (FIG. 3 (e)).

Next, SiO ₂ is deposited in the spacer (FIG. 3 (f)), the spacer 40 which is anisotropically etched
a and 40b are formed. And 2 × 1 per cm ²
0 ¹⁵ arsenic ions (As ⁺ ) are added to 150 (ke)
The source 20 and the drain 30 are formed by ion-implanting with the energy V) to form an n ⁺ region (FIG. 3).
(G)). The body contact portion 93 is ion-implanted with boron fluoride ions (BF ₂ ⁺ ) at a concentration of 2 × 10 ¹⁵ / cm ^{2 at} an energy of 60 (keV) to form a p ⁺ -type region. It is good. The semiconductor device shown in FIG. 1 can be manufactured by the above manufacturing steps.

When a voltage is applied to the polycrystalline silicon 60 of the semiconductor device shown in FIG. 1, a channel 150 is formed and a conduction state is established. At this time, the threshold voltage of the polycrystalline silicon 60 is p-type. In addition, since the n ⁻ region 110 is formed, it is about 0.6 (V) as in the related art. Since the single crystal silicon on the silicon substrate has the same conductivity type (n type) and a small barrier in the depth direction, the channel 150
Has a thickness of about 500 (Å) as compared with the prior art, and a large amount of electrons flow from the interface between the n ⁻ region 110 and the gate oxide film 50 toward the substrate toward the substrate. Can be suppressed.

Further, since a bias voltage with the source side at the low potential side is applied to the p ⁻ region 100, drift electrons do not reach the sapphire interface and are discharged outside by the body contact electrode 94, and This makes it difficult for traps and detraps to occur, thereby further reducing 1 / f noise.

FIG. 4 is a sectional view of the semiconductor device according to the second embodiment.
FIG. The semiconductor device of this embodiment is a P-type MOS
The feature is that it is an FET. This semiconductor device is
With single crystal silicon provided on the fire substrate 10
Source 21 (p⁺, P-type semiconductor) and drain
(P⁺, P-type semiconductor) 31 are formed.
A gate oxide film 50 and an electrode are formed on the upper part of the single crystal silicon.
Function⁺Type polycrystalline silicon 60, as protective film
Functional SiO _TwoLayer 70 is laminated on both sides of the laminated portion
Is SiO_TwoSpacers 40a and 40b made of
ing.

Between the source 21 and the drain 31, there are provided an n ⁻ type single crystal silicon 101 and ap ⁻ type single crystal silicon 111 formed thereon, and a bias voltage 81. (Eg, -0.5 (v)) is applied so that the source 21 side is on the high voltage side.
Such an apparatus can be manufactured by the same manufacturing process as that of FIG. 3 if the ion implantation is changed so that the single crystal and the polycrystalline silicon have the conductivity types as illustrated.

When a voltage is applied to the polycrystalline silicon 61, a channel 151 is formed to be in a conductive state. At this time, the threshold voltage is such that the polycrystalline silicon 61 is made n-type and the p ⁻ region 111 is formed. 0.6
(V). Then, the single crystal silicon on the silicon substrate becomes the same conductivity type (p type) and the barrier in the depth direction becomes smaller, so that the thickness of the channel 151 becomes about 500 (従 来) thicker than before, and the p ⁻ region 111 and the gate Since a large amount of electrons flow from the interface with the oxide film 50 toward the substrate in a deep region in the substrate direction, the scattering of electrons at the interface is reduced, and 1 / f noise can be suppressed.

Furthermore, since a bias voltage is applied to the n ⁻ region 101 with the source side on the high potential side, the drift electrons do not reach the sapphire interface but are discharged outside by the body contact electrode 94, and This makes it difficult for traps and detraps to occur, thereby further reducing 1 / f noise.

FIG. 5 is a sectional view of a semiconductor device according to the third embodiment. The semiconductor device of this embodiment is characterized in that only a channel thickness is increased without applying a bias voltage. In this semiconductor device, a source 22 (n ⁺ , n-type semiconductor) and a drain (n ⁺ , n-type semiconductor) 32 formed on a sapphire substrate 10 and made of relatively thin single crystal silicon of about 700 ° are formed. Further, a gate oxide film 50, p ⁺ -type polycrystalline silicon 60 functioning as an electrode, and an SiO ₂ layer 70 functioning as a protective film are stacked on the single crystal silicon. Are provided with spacers 40a and 40b made of SiO ₂ .

Then, between the source 22 and the drain 32
Has a relatively thin n of about 700 ° ^-Single crystal silicon
１１２112 is provided. Such a device is illustrated in FIG.
P^-Change the process so that the area 100 is not formed.
For example, it is possible to manufacture in the same manufacturing process as FIG.
You.

When a voltage is applied to the polycrystalline silicon 60, a channel 152 is formed to be in a conductive state. At this time, the threshold voltage is such that the polycrystalline silicon 60 is p-type and the n ⁻ region 112 is formed. 0.6
(V). Since the single crystal silicon on the silicon substrate has the same conductivity type (n type) and a small barrier in the depth direction, the thickness of the channel 152 is increased to about 500 (よ り), and the n ⁻ region 112 and the gate Since a large amount of electrons flow from the interface with the oxide film 50 toward the substrate in a deep region in the substrate direction, the scattering of electrons at the interface is reduced, and 1 / f noise can be suppressed. According to this embodiment, since only the channel thickness is increased without applying a bias voltage, 1 / f noise can be suppressed with a simpler configuration. For example, since the buddy contact portion 93 is not required, the manufacturing process can be further simplified and the cost can be reduced.

According to the embodiment of the present invention described above, by making the channel thickness thicker than before and preventing the drift electrons from reaching the sapphire substrate by the bias voltage, the interface scattering of the electrons and the electron are prevented. It is possible to realize a MOSFET having an SOS structure in which 1 / f noise is suppressed by suppressing interface traps and detraps.

[0031]

As described above, according to the first and second aspects of the present invention, since many electrons flow in a deep part of the channel-formable region, interface scattering of electrons is reduced, and 1 /
f Noise is reduced.

According to the third aspect of the present invention, by applying a bias voltage, traps and detraps at the interface of the insulating substrate are less likely to occur, and 1 / f noise is further reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating a manufacturing process of the semiconductor device.

FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

10 sapphire substrate 20 Source 21 Source 22 Source 30 drain 31 drain 32 drain 40a spacers 40b spacers 50 gate oxide film 60 of polycrystalline silicon 61 polycrystalline silicon 70 SiO ₂ layer 80 a bias voltage 81 bias voltage 90 contact hole 92 depletion layer 93 body contact Part 94 body contact electrode 100 p ^- region 101 n ^- region 110 n ^- region 111 p ^- region 112 n ^- region 150 channel 151 channel 152 channel

Claims (3)

[Claims] 1. A semiconductor device including a MOSFET formed on an insulating substrate, comprising: a source / drain region formed of a semiconductor of a first conductivity type; and a second region different from the first conductivity type. A gate region formed of a semiconductor of a conductivity type and a channel-formable region formed of a semiconductor of a first conductivity type having an impurity concentration lower than that of the source / drain regions and capable of forming a channel are formed. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a region made of the semiconductor of the second conductivity type is formed below the channel-formable region. 3. The semiconductor device according to claim 2, wherein a bias voltage is applied to a region formed of the semiconductor of the second conductivity type.