JP3628513B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for reducing noise in a semiconductor device having, for example, an SOS structure.
[0002]
[Prior art]
FIG. 6 is a schematic explanatory view showing a cross-sectional structure of a conventional SOS structure MOSFET. This MOSFET is a source 2 (n ⁺ , n-type semiconductor) composed of single crystal silicon provided on a sapphire substrate 1. And a drain (n ⁺ , n-type semiconductor) 3 are formed, and a gate oxide film 5, an n ⁺ -type polycrystalline silicon 6 functioning as an electrode, and a SiO ₂ layer 7 are formed on the single crystal silicon. Spacers 4a and 4b are provided on both side surfaces of the laminated portion.
[0003]
When a voltage is applied to the polycrystalline silicon 6, a channel 8 having a thickness of about 100 (Å) is formed in the p-type semiconductor region between the source 2 and the drain 3, and a current flows between the source 2 and the drain 3. Thus, the conduction operation is performed. At this time, electrons are scattered at the interface between the gate oxide film 5 and the single crystal silicon, and a large number of drifting electrons are generated without staying in the channel 8, and the interface between the sapphire substrate 1 and the single crystal silicon is generated. Many drift electrons were trapped and detrapped.
[0004]
[Problems to be solved by the invention]
However, the scattering of electrons increases and a large number of drift electrons are trapped and detrapped at the interface, which means that the fluctuation of electrons increases, and this fluctuation becomes a noise source.
[0005]
In the conventional one, the 1 / f noise is increased to about 100 times that of the bulk type.
The present invention has been made to solve such a conventional problem, and an object thereof is to suppress 1 / f noise of a semiconductor device including a MOSFET formed on an insulating substrate such as an SOS. .
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is a semiconductor device including a MOSFET formed on an insulating substrate, and includes a source region and a drain region made of a semiconductor of a first conductivity type , A gate region made of a semiconductor of a second conductivity type different from the first conductivity type is formed between the source region and the drain region, and has an impurity concentration lower than that of the source region and the drain region . A channel-formable region formed of a semiconductor of the first conductivity type and capable of forming a channel; and formed between the source region and the drain region and below the channel-formable region; and a channel bottom area composed of a semiconductor, between the source region and the channel lower region, especially the forward bias voltage is applied It is a semiconductor device that.
[0007]
According to a second aspect of the present invention , there is provided a semiconductor device comprising a MOSFET formed on an insulating substrate, wherein the source region and the drain region are made of an n-type semiconductor, and the gate is made of a p-type semiconductor. A channel-formable region formed between the source region and the source region and the n-type semiconductor having an impurity concentration lower than that of the source region and the drain region and capable of forming a channel; and the source region And a channel lower region formed of a p-type semiconductor between the source region and the channel lower region, and between the source region and the channel lower region. A semiconductor device is characterized in that a bias voltage is applied so that the region is on a low potential side.
Furthermore, the invention according to claim 3 is a semiconductor device including a MOSFET formed on an insulating substrate, wherein the source region and the drain region are made of a p-type semiconductor, and the gate is made of an n-type semiconductor. A channel-formable region formed between the source region and the source region and the drain region, formed of a p-type semiconductor having an impurity concentration lower than that of the source region and the drain region, and capable of forming a channel; and the source region A channel lower region formed between the source region and the channel lower region, and formed between the source region and the channel lower region. A semiconductor device is characterized in that a bias voltage is applied so that a source region is on a high potential side.
[0008]
According to the first to third aspects of the present invention, the channel layer formed in the channel formable region is thick, and a large amount of electrons flow in a deep location in the channel formable region, so that the interface scattering of electrons is reduced, and the electrons As a result of reducing the noise generated by the fluctuation of 1 / f, 1 / f noise is reduced.
[0010]
In addition, by applying a forward bias voltage between the source region and the channel lower region , for example, electrons drifted from the channel are less likely to reach the insulating substrate interface, and trapping and detrapping are caused by the insulating substrate interface. 1 / f noise is further reduced.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view thereof, and a cross-sectional view taken along a cutting line AA in FIG. Become. In addition, in order to facilitate understanding, components (spacers and SiO ₂ layers, which will be described later) appearing in cross-sectional views as appropriate are omitted in the plan view.
[0012]
In this semiconductor device, a source 20 (n ⁺ , n-type semiconductor) and a drain (n ⁺ , n-type semiconductor) 30 made of single crystal silicon provided on a sapphire substrate 10 are formed. A gate oxide film 50, a p ⁺ type polycrystalline silicon 60 functioning as an electrode, and a SiO ₂ layer 70 functioning as a protective film are stacked on top of the crystalline silicon, and spacers 40a made of SiO ₂ are formed on both sides of the stacked portion. , 40b are provided.
[0013]
A p ⁻ type single crystal silicon 100 and an n ⁻ type single crystal silicon 110 formed thereon are provided between the source 20 and the drain 30, and a bias voltage 80 is applied to the source 20. It is applied so that the side becomes the low potential side.
[0014]
Further, as shown in FIG. 2, a contact hole 90 is provided in the polycrystalline silicon 60, and a body contact portion 93 which is a p ⁺ type region including a body contact electrode 94 which is a bias voltage applying electrode. However, the body contact portion 93 and the drain 30 (source 20) are disposed so as to face the single crystal silicon layer with a depletion layer 92 for electrical insulation therebetween. ^- it is -type region 100 and electrically connected.
[0015]
Next, a method for manufacturing a semiconductor device having such a structure will be described with reference to FIG.
First, single crystal silicon having a thickness of 2000 (Å) is formed on the sapphire substrate 1 by epitaxial growth (FIG. 3A).
[0016]
Next, a 100 (（) oxide film (SiO ₂ ) is formed on the single crystal, masking a desired pattern with a mask member, and ion implantation is performed. An ionized boron (B ⁺ ) concentration of 5 × 10 ¹² per cm ² is ion-implanted with an energy of 70 (keV), and 40 × 1 × 10 ¹³ concentrations of ionized phosphorus (P ⁺ ) per cm ² ( The ion implantation is performed with the energy of keV). As a result, an n ⁻ region and a p ⁻ region below the n ⁻ region are formed (FIG. 3B). Note that ionized boron is implanted to adjust the threshold voltage, and ionized phosphorus is implanted to reduce the resistance of the sapphire / single crystal silicon interface.
[0017]
Next, the oxide film and mask member formed in the previous process are removed, and the silicon surface is oxidized in an atmosphere of a mixed gas of hydrogen and oxygen at 850 ° C. to form a gate oxide film 50 having a thickness of 100 (Å). Then, a polycrystalline silicon 60 having a thickness of 3000 (Å) is formed thereon by CVD. Further, 5 × 10 ¹⁴ boron fluoride ions (BF ₂ ⁺ ) per 1 cm ² are ion-implanted with an energy of 30 (keV) (FIG. 3C).
[0018]
Next, SiO ₂ having a thickness of 3000 (３) is deposited by CVD to form a SiO ₂ layer 70, and after forming a gate electrode pattern, annealing is performed in an atmosphere of 900 ° C. and nitrogen gas for 1 hour. Then, activation of the polycrystalline silicon 60 and mutual diffusion of the n ⁻ region 110 and the p ⁻ region 100 are performed. Since the diffusion coefficients of phosphorus and boron are substantially the same and the concentration of phosphorus is higher as described above, the boundary between both regions is provided at a position of about 300 (Å) from the sapphire-silicon interface (FIG. 3 (d) )).
[0019]
Next, 1 × 10 ¹³ concentrations of ionized phosphorus (P ⁺ ) per cm ² are ion-implanted with an energy of 60 (keV) to form n-type regions on both sides of the regions 100 and 110 (FIG. 3). (E)).
[0020]
Next, spacer SiO ₂ is deposited (FIG. 3F), and anisotropically etched to form spacers 40a and 40b. Then, arsenic ions (As ⁺ ) at a concentration of 2 × 10 ¹⁵ per cm ² are ion-implanted with an energy of 150 (keV) to form an n ⁺ region to form a source 20 and a drain 30 (FIG. 3 (g)). It should be noted that boron fluoride ions (BF ₂ ⁺ ) having a concentration of 2 × 10 ¹⁵ per cm ² are ion-implanted with energy of 60 (keV) into the body contact portion 93 described above to form a p ⁺ type region. It ’s fine. The semiconductor device shown in FIG. 1 can be manufactured by the manufacturing process as described above.
[0021]
When a voltage is applied to the polycrystalline silicon 60 of the semiconductor device shown in FIG. 1, a channel 150 is formed and becomes conductive. The threshold voltage at this time is such that the polycrystalline silicon 60 is p-type and n ^−. Since the region 110 is formed, it is about 0.6 (V) as usual. Since the single crystal silicon on a silicon substrate a barrier of the same conductivity type (n-type) and the depth direction is reduced, the thickness of the channel 150 is thicker than 500 (Å) to that of the prior art, n ^- region 110 and the gate Since many electrons flow in a deep region from the interface with the oxide film 50 toward the substrate, the interface scattering of the electrons is reduced, and 1 / f noise can be suppressed.
[0022]
Further, since a bias voltage with the source side being a low potential side is applied to the p ⁻ region 100, drift electrons do not reach the sapphire interface but are discharged to the outside by the body contact electrode 94, and trapped by the interface, Detrapping is less likely to occur and 1 / f noise can be further suppressed.
[0023]
FIG. 4 is a sectional view of the semiconductor device according to the second embodiment. The semiconductor device of this embodiment is characterized in that it is a P-type MOSFET.
In this semiconductor device, a source 21 (p ⁺ , p-type semiconductor) and a drain (p ⁺ , p-type semiconductor) 31 made of single crystal silicon provided on a sapphire substrate 10 are formed. A gate oxide film 50, an n ⁺ -type polycrystalline silicon 60 functioning as an electrode, and an SiO ₂ layer 70 functioning as a protective film are stacked on top of the crystalline silicon, and spacers 40a made of SiO ₂ are formed on both sides of the stacked portion. , 40b are provided.
[0024]
An n ⁻ type single crystal silicon 101 and a p ⁻ type single crystal silicon 111 formed thereon are provided between the source 21 and the drain 31, and a bias voltage 81 (for example, − 0.5 (v)) is applied so that the source 21 side is on the high voltage side. Such an apparatus can be manufactured by the same manufacturing process as that shown in FIG. 3 if the ion implantation is changed so that the single crystal and polycrystalline silicon have the conductivity type as shown.
[0025]
When a voltage is applied to the polycrystalline silicon 61, the channel 151 is formed and becomes conductive. The threshold voltage at this time is that the polycrystalline silicon 61 is n-type and the p ⁻ region 111 is formed. It is about 0.6 (V) as usual. Since the single crystal silicon on a silicon substrate a barrier of the same conductivity type (p-type) and the depth direction is reduced, the thickness of the channel 151 is thicker than 500 (Å) to that of the prior art, p ^- region 111 and the gate Since many electrons flow in a deep region from the interface with the oxide film 50 toward the substrate, the interface scattering of the electrons is reduced, and 1 / f noise can be suppressed.
[0026]
Furthermore, since a bias voltage with the source side as the high potential side is applied to the n ⁻ region 101, the drift electrons do not reach the sapphire interface but are discharged to the outside by the body contact electrode 94, and trapped by the interface, Detrapping is less likely to occur and 1 / f noise can be further suppressed.
[0027]
FIG. 5 shows a cross-sectional view of the semiconductor device of the third embodiment. The semiconductor device of this embodiment is characterized in that only a channel thickness is increased without applying a bias voltage. This semiconductor device includes a source 22 (n ⁺ , n-type semiconductor) and a drain (n ⁺ , n-type semiconductor) 32 that are formed on a sapphire substrate 10 and are made of relatively thin single crystal silicon of about 700 mm. Further, a gate oxide film 50, a p ⁺ type polycrystalline silicon 60 functioning as an electrode, and an SiO ₂ layer 70 functioning as a protective film are stacked on the single crystal silicon, and are formed on both side surfaces of the stacked portion. Are provided with spacers 40a and 40b made of SiO ₂ .
[0028]
Between the source 22 and the drain 32, a relatively thin n ⁻ type single crystal silicon 112 of about 700 mm is provided. Such a device can be manufactured in the same manufacturing process as that in FIG. 3 if the process is changed so as not to form the p ⁻ region 100 in FIG.
[0029]
When a voltage is applied to the polycrystalline silicon 60, the channel 152 is formed and becomes conductive. The threshold voltage at this time is that the polycrystalline silicon 60 is made p-type and the n ⁻ region 112 is formed. It is about 0.6 (V) as usual. Since the single crystal silicon on a silicon substrate a barrier of the same conductivity type (n-type) and the depth direction is reduced, the thickness of the channel 152 is thicker than 500 (Å) to that of the prior art, n ^- region 112 and the gate Since many electrons flow in a deep region from the interface with the oxide film 50 toward the substrate, the interface scattering of the electrons is reduced, and 1 / f noise can be suppressed. According to this embodiment, since only the channel thickness is increased without applying a bias voltage, 1 / f noise can be suppressed with a simpler configuration. For example, since the buddy contact portion 93 is not necessary, the manufacturing process is further simplified and the cost can be reduced.
[0030]
According to the embodiment of the present invention that has been described above, the electron interface scattering and the electron interface trap are achieved by making the channel thickness thicker than before or by preventing drift electrons from reaching the sapphire substrate by the bias voltage. Therefore, it is possible to realize a MOSFET having an SOS structure in which detrapping is suppressed and 1 / f noise is suppressed.
[0031]
【The invention's effect】
As described above, according to the first to third aspects of the invention, a large amount of electrons flow in a deep region of the channel formable region, so that interface scattering of the electrons is reduced and 1 / f noise is reduced.
[0032]
Also, between the source region and the channel bottom region, by applying a forward bias voltage, insulation substrate interface trap by, detrapping is 1 / f noise hardly occurs can be further reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view of the semiconductor device according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating a manufacturing process of a semiconductor device.
FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is an explanatory diagram of a conventional technique.
[Explanation of symbols]
10 Sapphire substrate 20 Source 21 Source 22 Source 30 Drain 31 Drain 32 Drain 40a Spacer 40b Spacer 50 Gate oxide film 60 Polycrystalline silicon 61 Polycrystalline silicon 70 SiO ₂ layer 80 Bias voltage 81 Bias voltage 90 Contact hole 92 Depletion layer 93 Body contact Part 94 Body contact electrode 100 p ⁻ region 101 n ⁻ region 110 n ⁻ region 111 p ⁻ region 112 n ⁻ region 150 channel 151 channel 152 channel

Claims (3)

A semiconductor device comprising a MOSFET formed on an insulating substrate,
A source region and a drain region made of a semiconductor of a first conductivity type;
A gate region made of a semiconductor of a second conductivity type different from the first conductivity type;
A channel-formable region formed between the source region and the drain region , made of a semiconductor of a first conductivity type having an impurity concentration lower than that of the source region and the drain region, and capable of forming a channel;
A channel lower region formed between the source region and the drain region and below the channel-formable region and made of the semiconductor of the second conductivity type,
A semiconductor device , wherein a forward bias voltage is applied between the source region and the channel lower region . A semiconductor device comprising a MOSFET formed on an insulating substrate,
  a source region and a drain region made of an n-type semiconductor;
  a gate region composed of a p-type semiconductor;
  A channel-formable region formed between the source region and the drain region, made of an n-type semiconductor having an impurity concentration lower than that of the source region and the drain region, and capable of forming a channel;
  A channel lower region formed between the source region and the drain region and below the channel-formable region and made of a p-type semiconductor,
  A semiconductor device, wherein a bias voltage is applied between the source region and the channel lower region so that the source region is on a low potential side. A semiconductor device comprising a MOSFET formed on an insulating substrate,
  a source region and a drain region made of a p-type semiconductor;
  a gate region composed of an n-type semiconductor;
  A channel-formable region formed between the source region and the drain region, made of a p-type semiconductor having an impurity concentration lower than the impurity concentration of the source region and the drain region, and capable of forming a channel;
  A channel lower region formed between the source region and the drain region and below the channel-formable region and made of the n-type semiconductor,
  A semiconductor device, wherein a bias voltage is applied between the source region and the channel lower region so that the source region is on a high potential side.

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