JP2004200335A - Semiconductor device including insulated gate field-effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a MISFET having higher current driving capability in a device structure using an Si<SB>1-x</SB>Ge<SB>x</SB>layer on a silicon substrate, and further provide its manufacturing method. <P>SOLUTION: The Si<SB>1-x</SB>Ge<SB>x</SB>layer 103 is formed on the silicon substrate 101, and the MISFET is formed on the Si<SB>1-x</SB>Ge<SB>x</SB>layer 103. The junction depth between a source layer and drain regions 106, 107 is set not to exceed the face where the Si<SB>1-x</SB>Ge<SB>x</SB>layer 103 and a silicon layer are brought into contact with each other. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including an insulated gate field effect transistor and a method for manufacturing the same.
[0002]
[Prior art]
In response to a demand for higher performance of an integrated circuit using a silicon substrate, a higher speed of an insulated gate field effect transistor (hereinafter, referred to as a MISFET) constituting the circuit is required. Heretofore, a method of shortening the channel length of a MISFET by a miniaturization technique has been used. Further, in recent years, in order to increase the electric conductivity of the channel region, a mixed crystal semiconductor (hereinafter, Si) made of silicon and germanium has been used._1-xGe_xIs formed on a silicon substrate, and the Si_1-xGe_xA device in which a MISFET is formed in a layer is known.
[0003]
For example, Patent Document 1 discloses that Si is formed on a silicon substrate by selective epitaxy._1-xGe_xDiscloses a semiconductor device in which a layer and a silicon layer are stacked and the stacked region is used as a MISFET, and a method of manufacturing the same. Si_1-xGe_xWhen the layer and the silicon layer are stacked, (1) an increase in carrier mobility due to a strain effect, and (2) an increase in a carrier concentration due to a quantum well effect caused by a difference in band structure and interference between bands occur. It becomes possible to make the electric conductivity of the region larger than that of the MISFET formed on the silicon substrate. That is, even in a MISFET using a silicon layer for electric conduction, Si_1-xGe_xThe above effect can be obtained also in the MISFET using the layer for electric conduction. Patent Document 2 discloses that Si_1-xGe_xA semiconductor device using only layers and increasing the electrical conductivity of the MISFET channel region is shown.
[0004]
The channel regions of the MISFETs disclosed in Patent Documents 1 and 2 described above are made of Si formed by an epitaxy method._1-xGe_xLayer, or in a silicon layer formed thereon, while the drain region is_1-xGe_xThe layer is formed not only in the layer or the silicon layer formed thereon, but also in the silicon region existing thereunder. Therefore, the Si constituting the channel region as the MISFET_1-xGe_xThere is a current path from the layer to the silicon layer that constitutes the drain region.
[0005]
[Patent Document 1]
JP-A-10-321733 (page 1, FIG. 1)
[0006]
[Patent Document 2]
JP 2001-119026 A (Page 1, FIG. 1)
[0007]
[Problems to be solved by the invention]
The performance of the MISFET largely depends not only on the electrical characteristics of the channel region but also on the existence of barrier height when current flows from the channel to the drain side, and electrical characteristics such as a resistance component at the drain side electrode.
[0008]
In the above-described conventional semiconductor device, Si_1-xGe_xLayer and silicon layer or Si_1-xGe_xThe use of the layer makes it possible to increase the electrical conductivity of the MISFET channel region. However, Si_1-xGe_xThe current path from the channel region of the layer to the silicon region constituting the drain region is viewed from the viewpoint of the energy band structure, as shown in the schematic diagram of the energy band structure in FIG.
[0009]
In other words, the conduction band of the channel region is lower than the conduction band of the drain region, and serves as a potential barrier for electrons. Also, the valence band of the channel region is higher than the valence band of the drain region, and Becomes a potential barrier. Therefore, the current driving capability of the MISFET is hindered. Therefore, from the structure of the channel region, Si_1-xGe_xAlthough the electrical conductivity of the channel can be increased by using the layer, the performance of the MISFET as a whole cannot be sufficiently improved.
[0010]
The present invention has been made in view of such circumstances, and its object is to provide a Si_1-xGe_xIt is an object of the present invention to provide a semiconductor device including a MISFET having a high current driving capability using a layer and a method of manufacturing the same.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention provides a semiconductor substrate having a surface region made of silicon, a mixed crystal semiconductor layer formed of silicon and germanium formed on the semiconductor substrate, A gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film, and a mixed crystal semiconductor layer under the gate insulating film interposed therebetween; And a source and drain region formed in the mixed crystal semiconductor layer so as not to exceed.
[0012]
According to a second aspect of the present invention, a step of forming an element isolation region in a semiconductor substrate having a surface region made of silicon and forming an element region surrounded by the element isolation region includes: A step of forming a mixed crystal semiconductor layer made of germanium, a step of stacking a gate insulating film and a gate electrode on the mixed crystal semiconductor layer, and, in the mixed crystal semiconductor layer, a mixed crystal semiconductor region below the gate insulating film. And forming source and drain regions in the mixed crystal semiconductor layer such that the junction depth does not exceed the mixed crystal semiconductor layer.
[0013]
According to the present invention, the junction depth of the source and drain regions does not exceed the mixed crystal semiconductor layer made of silicon and germanium. Therefore, in the energy band structure between the channel region and the drain region, there is no potential barrier between the channel region and the drain region, thereby effectively suppressing the electric resistance when electric charge flows from the channel region to the drain region. it can.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0015]
(First Embodiment)
FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps. FIG. 1C shows a first embodiment of the semiconductor device according to the present invention.
[0016]
First, as shown in FIG. 1A, a P-type silicon substrate 101 is prepared as a semiconductor substrate, and an oxide film is selectively buried in a surface region thereof by a selective oxidation method or a shallow trench isolation method. Form 102. Subsequently, if necessary, As, P, sb or the like in the case of the N-type and B, Ga, In or the like in the case of the P-type are diffused into the surface region surrounded by the element isolation region 102 as impurities. Alternatively, a well region may be formed.
[0017]
Next, the surface region made of silicon of the silicon substrate 101 is selectively etched, and further, as shown in FIG. 1B, Si is formed on the silicon substrate 101 other than the element isolation region 102 by the selective epitaxy method._1-xGe_xThe layer 103 is formed. Specifically, first, from the viewpoint of cleaning the surface of the silicon substrate 101 and flattening the step with the element isolation region 102, the silicon substrate 101 is heated to 900 to 1,150 ° C. Etch the exposed silicon. Subsequently, the silicon substrate 101 is heated to 550 to 750 ° C.₄Or SiH₂Cl₂And GeH₄Si in a gas containing_1-xGe_xA layer 103 having a thickness of 100 to 200 nm is selectively epitaxially grown on the silicon substrate 101. Si_1-xGe_xThe composition ratio x of the layer 103 is about 0.10 to 0.50, and is determined in consideration of desired electric characteristics.
[0018]
Next, an impurity is doped into the silicon substrate 101 by ion implantation for channel control. For example, in the case of an N-channel MISFET, a P-type impurity such as B, Ga, or In is used, and in the case of a P-channel MISFET, an N-type impurity such as As, P, or sb is used.^-2~ 5E13cm^-2About to inject. Subsequently, a hafnium oxide film is formed as a gate insulating film on the entire surface of the silicon substrate 101 with a thickness of, for example, about 20 nm by a CVD method. Further, a polycrystalline silicon film having a thickness of, for example, about 100 nm is formed on the hafnium oxide film.
[0019]
Next, as shown in FIG. 1C, the polycrystalline silicon film and the hafnium oxide film are selectively patterned by using a lithography method, a dry etching method, or the like to form a gate electrode 105 made of a polycrystalline silicon film. , And a gate insulating film 104 made of a hafnium oxide film. Subsequently, using the gate electrode 105 and the gate insulating film 104 as a mask, the silicon substrate 101 is doped with an impurity in a self-aligning manner by ion implantation to form source and drain regions 106 and 107. For example, in the case of an N-channel MISFET, an N-type impurity such as As, P, and In is used. In the case of a P-channel MISFET, a P-type impurity such as B, Ga, and sb is used.^-2~ 1E16cm^-2About to inject.
[0020]
Further, for example, RTA, spike annealing, or the like is used to perform rapid heating for about several seconds to activate the doped impurities. Including the heat treatment in the subsequent steps, the junction depth of the source and drain regions 106 and 107 is_1-xGe_xIt does not exceed the surface where the layer 103 and the underlying silicon are in contact.
[0021]
Next, an unillustrated SiO_TwoIs deposited on the entire surface of the silicon substrate 101. A contact hole is opened in this interlayer insulating film, and a W contact and a metal wiring such as Al and Cu are formed on the gate electrode 105 and the source and drain regions 106 and 107. Further, if necessary, deposition of an interlayer insulating film and formation of metal wiring are repeated to form a multilayer wiring structure. After that, the entire surface of the silicon substrate 101 is covered with a surface protection film (not shown), and a pad portion is opened to form a MISFET. Complete the semiconductor device including.
[0022]
In the semiconductor device described in this embodiment, Si has higher electrical conductivity than silicon._1-xGe_xNot only does layer 103 become a channel region, but source and drain regions 106 and 107 also_1-xGe_xFormed in layer 103. For this reason, the energy band structure of the channel and the drain is different from the conventional example shown in FIG. 7A, and there is no potential barrier as shown in FIG. 7B. That is, the resistance when the charge flows from the channel to the drain can be suppressed, and the operation of the MISFET can be sped up.
[0023]
(Second embodiment)
FIG. 2 is a sectional view showing a second embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps. FIG. 2C shows a second embodiment of the semiconductor device according to the present invention. In the present embodiment, Si_1-xGe_xAn example of a MISFET in which a silicon layer is further formed on a layer is shown.
[0024]
First, as shown in FIG. 2A, a P-type silicon substrate 201 is prepared as a semiconductor substrate, and an oxide film is selectively buried in a surface region thereof by a selective oxidation method or a shallow trench isolation method. 202 is formed. Subsequently, if necessary, As, P, sb or the like in the case of the N-type and B, Ga, In or the like in the case of the P-type are diffused as impurities in the surface region surrounded by the element isolation region 202. Alternatively, a well region may be formed.
[0025]
Next, the surface region made of silicon of the silicon substrate 201 is selectively etched, and then, as shown in FIG. 2B, Si is formed on the silicon substrate 201 other than the element isolation region 202 by the selective epitaxial growth method._1-xGe_xA layer 203 and a silicon layer 204 are formed. Specifically, first, from the viewpoint of cleaning the surface of the silicon substrate 201 and flattening the step with the element isolation region 202, the silicon substrate 201 is heated to 900 to 1,150 ° C., and the surface is coated with a gas containing HCl. Etch the exposed silicon. Subsequently, the silicon substrate 201 is heated to 550 to 750 ° C.₄Or SiH₂Cl₂And GeH₄In a gas containing_1-xGe_xA layer 203 is selectively epitaxially grown on the silicon substrate 201 to a thickness of 100 to 200 nm. Si_1-xGe_xThe composition ratio x of the layer 203 is about 0.10 to 0.50, and is determined in consideration of desired electric characteristics. Further, the silicon substrate 201 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂In a gas containing 20 to 40 nm of silicon layer 204,_1-xGe_xSelective epitaxial growth is performed on the layer 203.
[0026]
Next, SiO 2 is formed on the silicon layer 204 by a thermal oxidation method._TwoThe film is formed with a thickness of, for example, about 10 nm. Subsequently, an impurity for channel control is doped into the silicon substrate 201 by an ion implantation method. For example, in the case of an N-channel MISFET, a P-type impurity such as B, Ga, or In is used, and in the case of a P-channel MISFET, an N-type impurity such as As, P, or sb is used.^-2~ 5E13cm^-2About to inject. Furthermore, SiO_TwoA polycrystalline silicon film is laminated on the film, for example, to about 100 nm.
[0027]
Next, as shown in FIG. 2C, the above-described polycrystalline silicon film and SiO 2 are formed by using a lithography method, a dry etching method, or the like._TwoThe film is selectively patterned to form a gate electrode 206 made of a polycrystalline silicon film, and SiO 2_TwoA gate insulating film 205 made of a film is formed so as to be stacked. Subsequently, using the gate electrode 206 and the gate insulating film 205 as a mask, the silicon substrate 101 is doped with impurities by ion implantation in a self-aligned manner to form source and drain regions 207 and 208. For example, in the case of an N-channel MISFET, an N-type impurity such as As, P, and sb is used, and in the case of a P-channel MISFET, a P-type impurity such as B, Ga, and In is used.^-2~ 1E16cm^-2About to inject.
[0028]
Further, for example, RTA, spike annealing, or the like is used to perform rapid heating for about several seconds to activate the doped impurities. Including the heat treatment in the subsequent steps, the junction depth of the source and drain regions 207 and 208 is_1-xGe_xIt does not exceed the surface where the layer 203 and the underlying silicon are in contact.
[0029]
After that, an unillustrated SiO_TwoIs deposited on the entire surface of the silicon substrate 201. A contact hole is opened in this interlayer insulating film, and a W contact and a metal wiring such as Al and Cu are formed on the gate electrode 206 and the source and drain regions 207 and 208. Further, if necessary, a multilayer wiring structure is formed by repeating the deposition of an interlayer insulating film and the formation of metal wiring, and then the entire surface of the silicon substrate 201 is covered with a surface protection film (not shown), and the pad portion is opened to form the MISFET. Complete the semiconductor device including.
[0030]
In the semiconductor device described in this embodiment, the silicon layer 204 formed in the surface region of the silicon substrate 201 has high electric conductivity due to a strain effect, a quantum well effect, and the like,_1-xGe_xIt can be used as a channel region together with the layer 203. Further, the source and drain regions 207 and 208 are made of Si._1-xGe_xFormed in the layer 203, resistance when electric charge flows from the channel to the drain can be suppressed, and the operation of the MISFET can be sped up.
[0031]
(Third embodiment)
FIG. 3 is a sectional view showing a third embodiment of the method of manufacturing a semiconductor manufacturing apparatus according to the present invention in the order of steps. FIG. 3C shows a semiconductor device according to a third embodiment of the present invention. The third embodiment employs a structure in which an extension region is provided adjacent to a source and drain region and a metal silicide is attached to the source and drain regions and a gate electrode, and is applied to a MISFET suitable for miniaturization. Here is an example.
[0032]
First, as shown in FIG. 3A, a P-type silicon substrate 301 is prepared as a semiconductor substrate, and an oxide film is selectively buried in a surface region thereof by a selective oxidation method or a shallow trench isolation method. Form 302. Subsequently, if necessary, As, P, sb or the like in the case of the N-type and B, Ga, In or the like in the case of the P-type are diffused into the surface region surrounded by the element isolation region 302 as impurities. Alternatively, a well region may be formed.
[0033]
Next, from the viewpoint of cleaning the surface of the silicon substrate 301 and flattening the step with the element isolation region 302, the silicon substrate 301 is heated to 900 to 1,150 ° C., and the silicon exposed on the surface is etched with a gas containing HCl. I do. Subsequently, the silicon substrate 301 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂Is selectively epitaxially grown on the silicon substrate 301 to a thickness of 100 to 200 nm in a gas containing. When a lattice defect or the like is formed near the surface of the silicon substrate 301 by interposing the silicon buffer layer 303, the lattice defect can be removed and converted to high-quality silicon.
[0034]
Next, the silicon substrate 301 is heated to 550 to 750 ° C.₄Or SiH₂Cl₂And GeH₄In a gas containing_1-xGe_xA layer 304 is selectively epitaxially grown to a thickness of 100 to 200 nm on the silicon buffer layer 303. Si_1-xGe_xThe composition ratio x of the layer is about 0.10 to 0.50, and is determined in consideration of desired electric characteristics. Further, the silicon substrate 301 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂In a gas containing 20 to 40 nm of silicon_1-xGe_xSelective epitaxial growth on layer 304.
[0035]
Next, SiO 2 is formed on the silicon layer 305 by a thermal oxidation method._TwoThe film is formed with a thickness of, for example, about 10 nm. Subsequently, an impurity for channel control is doped into the silicon substrate 301 by an ion implantation method. For example, in the case of an N-channel MISFET, a P-type impurity such as B, Ga, or In is used, and in the case of a P-channel MISFET, an N-type impurity such as As, P, or sb is used.^-2~ 5E13cm^-2About to inject. Furthermore, SiO_TwoA polycrystalline silicon film is laminated on the film, for example, to about 100 nm.
[0036]
Next, as shown in FIG. 3B, the polycrystalline silicon film and the SiO_TwoThe film is selectively patterned, and a gate electrode 307 made of a polycrystalline silicon film and SiO_TwoA gate insulating film 306 made of a film is formed so as to be stacked. Subsequently, using the gate electrode 307 and the gate insulating film 306 as masks, the silicon substrate 301 is doped with impurities in a self-aligning manner by ion implantation to form extension regions 308 and 309. For example, in the case of an N-channel MISFET, an N-type impurity such as As, P, and sb is used, and in the case of a P-channel MISFET, a P-type impurity such as B, Ga, and In is used.^-2~ 3E15cm^-2About to inject.
[0037]
Then, for example, rapid heating is performed for several seconds by RTA, spike annealing, or the like, to activate the doped impurities. Including the heat treatment in the subsequent steps, the junction depth of the extension regions 308 and 309 is_1-xGe_xIt does not exceed the surface where the layer 304 and the silicon buffer layer 303 are in contact.
[0038]
Next, an insulating film such as a silicon nitride film is deposited on the entire surface of the silicon substrate 301 by a CVD method, and subsequently, is etched back using a dry etching method to select the side surfaces of the gate electrode 307 and the gate insulating film 306. And a sidewall insulating film 310 is formed. Again, by ion implantation, for example, in the case of an N-channel MISFET, N-type impurities such as As, P, and sb are used, and in the case of a P-channel MISFET, P-type impurities such as B, Ga, and In are used.^-2~ 3E15cm^-2About to inject. Thereafter, for example, rapid heating is performed for several seconds by RTA, spike annealing, or the like to activate the doped impurities, thereby forming source and drain regions 311 and 312.
[0039]
Next, for example, nickel is deposited to a thickness of 10 nm by a sputtering method, and thereafter, rapid heating is performed at 500 ° C. for 30 seconds. Nickel formed on the source and drain regions 311, 312 and the gate electrode 307 reacts with silicon to form nickel silicide. Thereafter, the remaining nickel including nickel on the insulating film is removed by selective wet etching, and nickel silicide layers 313, 314, and 315 are formed only on the source and drain regions 311, 312 and the gate electrode 307. At this time, germanium may be included in part of the nickel silicide layers 313, 314, 315 depending on the heat treatment conditions and the like.
[0040]
Nickel silicide and Si_1-xGe_xIs very low, and the resistance of nickel silicide is also lower than that of polycrystalline silicon. Therefore, the operation speed of the MISFET is improved by using nickel silicide as an electrode. Note that, as the metal silicide, a remarkable effect is shown in nickel silicide. However, the metal silicide is not limited to this, and in consideration of the entire process of the MISFET and desired characteristics, W, Co, Ti, Ta, Pt, Pd, etc. It may be selected from metals and silicides thereof.
[0041]
After that, an unillustrated SiO_TwoIs deposited on the entire surface of the silicon substrate 301. A contact hole is opened in this interlayer insulating film, and a W contact and a metal wiring such as Al and Cu are formed on the nickel silicide layers 313, 314 and 315. Further, if necessary, a multi-layer wiring structure is formed by repeating the deposition of an interlayer insulating film and the formation of a metal wiring, and then the entire surface of the silicon substrate 301 is covered with a surface protection film (not shown). Complete the semiconductor device including.
[0042]
In the semiconductor device described in this embodiment, the silicon layer 305 formed in the surface region of the silicon substrate 301 has high electrical conductivity due to a strain effect, a quantum well effect, and the like,_1-xGe_xIt can be used as a channel region together with the layer 304. Further, the extension regions 308 and 309 are Si_1-xGe_xFormed in the layer 304, resistance when electric charge flows from the channel to the drain can be suppressed, and the operation of the MISFET can be sped up.
[0043]
In addition, the extension region improves the drain withstand voltage and provides a structure more suitable for miniaturization of the MISFET. Furthermore, since metal silicide is used as an electrode, the resistance of the electrode is reduced and Si_1-xGe_xThe contact resistance with the layer can be reduced, and the operation of the MISFET can be sped up.
[0044]
(Fourth embodiment)
FIG. 4 is a sectional view showing a fourth embodiment of the method of manufacturing a semiconductor manufacturing apparatus according to the present invention in the order of steps. FIG. 4C shows a semiconductor device according to a fourth embodiment of the present invention. This fourth embodiment is based on Si_1-xGe_xAn example of an element structure in which the quantum well effect and the like are more remarkably linked to MISFET characteristics improvement by forming a multilayer of a silicon layer and a silicon layer will be described.
[0045]
First, as shown in FIG. 4A, a P-type silicon substrate 401 is prepared as a semiconductor substrate, and an oxide film is selectively buried in a surface region thereof by a selective oxidation method or a shallow trench element isolation method. Form 402. Subsequently, if necessary, As, P, sb, etc. for N-type and B, Ga, In, etc. for P-type are diffused into the surface region surrounded by the element isolation region 402 as impurities. Alternatively, a well region may be formed.
[0046]
Next, from the viewpoint of cleaning the surface of the silicon substrate 401 and flattening the step with the element isolation region 402, the silicon substrate 401 is heated to 900 to 1,150 ° C., and silicon exposed on the surface with a gas containing HCl is removed. Etch. Subsequently, the silicon substrate 401 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂Is selectively epitaxially grown on the silicon substrate 401 to a thickness of 100 to 200 nm in a gas containing
[0047]
Next, the temperature of the silicon substrate 401 is set to 550 to 750 ° C., and SiH 4 or SiH₂Cl₂And GeH₄First Si in a gas containing_1-xGe_xThe layer 404 is selectively epitaxially grown on the silicon buffer layer 403 by 30 to 50 nm. Si_1-xGe_xThe composition ratio x of the layer is about 0.25 to 0.75, and is determined in consideration of desired electric characteristics. Further, the silicon substrate 401 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂In a gas containing Si, the first silicon layer 405 is formed to a thickness of 30 to 50 nm,_1-xGe_xSelective epitaxial growth on layer 404.
[0048]
Next, the first Si_1-xGe_xThe second Si layer is formed in the same manner as the layer forming conditions._{1- x}Ge_xA layer 406 is selectively epitaxially grown to a thickness of 30 to 50 nm on the first silicon layer 405. Further, the second silicon layer 407 is formed to a thickness of 10 to 20 nm in the same manner as the conditions for forming the first silicon layer._1-xGe_xSelective epitaxial growth on layer 406. At this time, impurity doping may be appropriately performed during growth so that desired electric characteristics can be obtained.
[0049]
Next, SiO 2 is formed on the second silicon layer 407 by a thermal oxidation method._TwoThe film is formed with a thickness of, for example, about 10 nm. Subsequently, an impurity for channel control is doped into the silicon substrate 401 by an ion implantation method. For example, in the case of an N-channel MISFET, a P-type impurity such as B, Ga, or In is used, and in the case of a P-channel MISFET, an N-type impurity such as As, P, or sb is used.^-2~ 5E13cm^-2About to inject. Furthermore, SiO_TwoA polycrystalline silicon film is laminated on the film, for example, to about 100 nm.
[0050]
Next, as shown in FIG. 4B, the above-mentioned polycrystalline silicon film and SiO_TwoThe film is selectively patterned, and a gate electrode 409 made of a polycrystalline silicon film and SiO_TwoA gate insulating film 408 made of a film is formed so as to be stacked. Subsequently, using the gate electrode 409 and the gate insulating film 408 as a mask, the silicon substrate 401 is doped with impurities in a self-aligning manner by ion implantation to form extension regions 410 and 411. For example, in the case of an N-channel MISFET, an N-type impurity such as As or P is used, and in the case of a P-channel MISFET, a P-type impurity such as B is used.^-2~ 3E15cm^-2About to inject. Then, for example, rapid heating is performed for several seconds by RTA, spike annealing, or the like, to activate the doped impurities. The junction depth of the extension regions 410 and 411 including the first Si_1-xGe_xIt does not exceed the surface where the layer 404 and the silicon buffer layer 403 are in contact with each other.
[0051]
Next, an insulating film such as a silicon nitride film is deposited on the entire surface of the silicon substrate 401 by a CVD method, and subsequently, is etched back using a dry etching method to select the side surfaces of the gate electrode 409 and the gate insulating film 408. And a sidewall insulating film 412 is formed. Again, by ion implantation, for example, an N-channel MISFET uses an N-type impurity such as As or P, and a P-channel MISFET uses a P-type impurity such as B, and has a dose of 1E15 cm.^-2~ 1E16cm^-2About to inject. After that, for example, rapid heating is performed for several seconds by RTA, spike annealing, or the like to activate the doped impurities to form source and drain regions 413 and 414.
[0052]
Next, a nickel film is deposited to a thickness of, for example, 10 nm by a sputtering method, and thereafter, rapid heating is performed at 500 ° C. for 30 seconds. Nickel formed on the source and drain regions 413 and 414 and the gate electrode 409 reacts with silicon to form nickel silicide. After that, the remaining nickel including nickel on the insulating film is removed by selective wet etching, and nickel silicide layers 415, 416, and 417 are formed only on the source and drain regions 413 and 414 and the gate electrode 409. At this time, germanium may be included in part of the nickel silicide layers 415, 416, and 417 depending on the heat treatment conditions and the like.
[0053]
Thereafter, a SiO 2 not shown_TwoIs deposited on the entire surface of the silicon substrate 401. A contact hole is opened in this interlayer insulating film, and a W contact and a metal wiring such as Al and Cu are formed in the nickel silicide layers 415, 416, and 417. Further, if necessary, a multilayer wiring structure is formed by repeating the deposition of an interlayer insulating film and the formation of a metal wiring, and then the entire surface of the silicon substrate 401 is covered with a surface protective film, the pad portion is opened, and a semiconductor including a MISFET is formed. Complete the device.
[0054]
In the semiconductor device described in this embodiment, the potential barrier between the channel and the drain is eliminated, the resistance when electric charge flows from the channel to the drain is suppressed, and the operation of the MISFET can be performed at high speed. The carrier induced at 405 is transferred to the second Si_1-xGe_xFor example, the MISFET can be confined in the layer 406 to contribute to electric conduction, and the MISFET can be further speeded up.
[0055]
(Fifth embodiment)
FIG. 5 is a sectional view showing a fifth embodiment of the method of manufacturing a semiconductor manufacturing apparatus according to the present invention in the order of steps. FIG. 5C shows a semiconductor device according to a fifth embodiment of the present invention. In the fifth embodiment, all the source and drain regions are made of Si._1-xGe_xAn example of a MISFET in which the resistance of the drain region is further reduced by forming a layer will be described.
[0056]
First, as shown in FIG. 5A, a P-type silicon substrate 401 is prepared as a semiconductor substrate, and an oxide film is selectively buried in a surface region thereof by a selective oxidation method or a shallow trench isolation method. Form 402. Subsequently, if necessary, As, P, sb, etc. for N-type and B, Ga, In, etc. for P-type are diffused into the surface region surrounded by the element isolation region 402 as impurities. Alternatively, a well region may be formed.
[0057]
Next, from the viewpoint of cleaning the surface of the silicon substrate 501 and flattening a step with the element isolation region 502, the silicon substrate 501 is heated to 900 to 1,150 ° C., and silicon exposed on the surface with a gas containing HCl is removed. Etch. Subsequently, the silicon substrate 501 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂Is selectively epitaxially grown on the silicon substrate 501 to a thickness of 100 to 200 nm in a gas containing.
[0058]
Next, the silicon substrate 501 is heated to 550 to 750 ° C.₄Or SiH₂Cl₂And GeH₄In a gas containing_1-xGe_xA layer 504 is selectively epitaxially grown on the silicon buffer layer 503 to a thickness of 100 to 200 nm. Si_1-xGe_xThe composition ratio x of the layer is about 0.25 to 0.75, and is determined in consideration of desired electric characteristics. Further, the silicon substrate 501 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂In a gas containing 20 to 40 nm of silicon layer 505,_1-xGe_xSelective epitaxial growth on layer 504.
[0059]
Next, SiO 2 is formed on the silicon layer 505 by a thermal oxidation method._TwoThe film is formed with a thickness of, for example, about 15 nm. Subsequently, an impurity for channel control is doped into the silicon substrate 501 by an ion implantation method. For example, in the case of an N-channel MISFET, a P-type impurity such as B, Ga, or In is used, and in the case of a P-channel MISFET, an N-type impurity such as As, P, or sb is used.^-2~ 5E13cm^-2About to inject. Furthermore, SiO_TwoA polycrystalline silicon film is laminated on the film, for example, to a thickness of about 200 nm. Subsequently, a silicon nitride film is stacked, for example, to about 100 nm.
[0060]
Next, the silicon nitride film, the polycrystalline silicon film, and the SiO_TwoThe film is selectively patterned, and a silicon nitride film 508 as an etching mask, a gate electrode 507 made of a polycrystalline silicon film, and SiO 2_TwoA gate insulating film 506 made of a film is formed so as to be stacked. Subsequently, a silicon nitride film 508, a polycrystalline silicon film 507, and SiO 2_TwoUsing the film 506 as a mask, the silicon substrate 501 is doped with impurities in a self-aligning manner by ion implantation to form extension regions 509 and 510. For example, in the case of an N-channel MISFET, an N-type impurity such as As or P is used, and in the case of a P-channel MISFET, a P-type impurity such as B is used.^-2~ 3E15cm^-2About to inject. Thereafter, for example, rapid heating of about several seconds is performed by RTA or spike annealing to activate the doped impurities. Including the heat treatment in the subsequent steps, the junction depth of the extension regions 509 and 510 is_1-xGe_xIt does not exceed the surface where the layer 504 and the silicon buffer layer 503 are in contact with each other.
[0061]
Next, an insulating film such as a silicon nitride film is deposited on the entire surface of the silicon substrate 501 by a CVD method, and then etched back using a dry etching method to select the gate electrode 507 and the side surfaces of the gate insulating film 506. The sidewall insulating film 511 is formed. Next, as shown in FIG. 5B, using the silicon nitride film 508 as a mask, the silicon substrate 501 is heated to 700 to 850 ° C. in a gas atmosphere containing HCl, and the silicon layer 505 exposed on the silicon substrate 501 is removed. Si_1-xGe_xThe layer 504 and part of the silicon buffer layer 503 are removed.
[0062]
Further, as shown in FIG. 5C, the temperature of the silicon substrate 501 is set to 550 to 750 ° C., and SiH 4 or SiH₂Cl₂And GeH₄In a gas containing_1-xGe_xThe layers 512, 513 are selectively embedded in the etched areas. Si_1-xGe_xThe composition ratio of the layer is Si_1-xGe_xThe composition is the same as that of the layer. Next, the nitride film used as a mask is selectively removed, and again, for example, N-type impurities such as As and P for an N-channel MISFET and B and the like for a P-channel MISFET by ion implantation. Using a P-type impurity, a dose amount of 1E15 cm^-2~ 1E16cm^-2About to inject. Thereafter, for example, rapid heating for several seconds is performed by RTA, spike annealing, or the like to activate the doped impurities, thereby forming source and drain regions 514 and 515.
[0063]
Thereafter, a SiO 2 not shown_TwoIs deposited on the entire surface of the silicon substrate 501. A contact hole is opened in the interlayer insulating film, and a W contact and a metal wiring such as Al and Cu are formed on the gate electrode 507 and the source and drain regions 514 and 515. Further, if necessary, a multilayer wiring structure is formed by repeating the deposition of an interlayer insulating film and the formation of a metal wiring, and then the entire surface of the silicon substrate 501 is covered with a surface protection film (not shown). Complete the semiconductor device including.
[0064]
In the semiconductor device described in this embodiment, the potential barrier between the channel and the drain is eliminated, the resistance when electric charge flows from the channel to the drain is suppressed, and the operation of the MISFET can be sped up. Also, the drain side Si_1-xGe_xLayer the channel Si_1-xGe_xIt can be formed thicker than the layer, and the control of the junction depth of the drain layer becomes easy. Further, the contact resistance between the drain and the metal or the metal silicide can be reduced.
[0065]
(Sixth embodiment)
FIG. 6 is a sectional view showing a sixth embodiment of the method of manufacturing a semiconductor manufacturing apparatus according to the present invention in the order of steps. FIG. 6C shows a sixth embodiment of the semiconductor device according to the present invention. The sixth embodiment shows an example of a MISFET on an SOI structure substrate.
[0066]
First, as shown in FIG. 6A, an SOI substrate 601 formed by a SiMOX method (oxygen ion implantation method) is prepared. The SOI substrate 601 is obtained by implanting oxygen ions into a silicon substrate and then forming a buried oxide layer by heat treatment to form an insulating separation layer 602. The active silicon layer 603 is on the main surface side of the insulating isolation layer 602 where oxygen ions are implanted in the SOI substrate 601. As the SOI forming method, a bonding method, a beam annealing method, or the like may be used in addition to the above-described SiMOX method.
[0067]
Next, as shown in FIG. 6B, an oxide film is selectively formed on the surface region of the active silicon layer 603 of the SOI substrate 601 by a selective oxidation method or a shallow trench element isolation method to form an element isolation region 604. . Subsequently, if necessary, As, P, sb, etc. for N-type and B, Ga, In, etc. for P-type are diffused into the surface region surrounded by the element isolation region 402 as impurities. Alternatively, a well region may be formed.
[0068]
Next, from the viewpoint of cleaning the surface of the silicon active layer 603 and flattening the step with the element isolation region 604, the SOI substrate 601 is heated to 900 to 1,150 ° C., and silicon exposed on the surface with a gas containing HCl. Is etched. Next, the SOI substrate 601 is heated to 700 to 850 ° C.₄Or SiH₂Cl₂Is selectively grown epitaxially on the active silicon layer 603 with a thickness of 30 to 70 nm in a gas containing.
[0069]
Subsequently, the SOI substrate 601 is heated to 550 to 750 ° C.₄Or SiH₂Cl₂And GeH₄Si in a gas containing_1-xGe_xA layer 606 is selectively epitaxially grown on the silicon buffer layer 605 to a thickness of 100 to 200 nm. Si_1-xGe_xThe layer composition ratio x is about 0.25 to 0.75, and is determined in consideration of desired electric characteristics.
[0070]
Next, an impurity for channel control is doped into the SOI substrate 601 by an ion implantation method. For example, in the case of an N-channel MISFET, a P-type impurity such as B is used, and in the case of a P-channel MISFET, an N-type impurity such as As or P is used.^-2~ 5E13cm^-2About to inject. Subsequently, a hafnium oxide film is formed with a thickness of about 20 nm on the entire surface of the SOI substrate 601 by a CVD method. Further, a polycrystalline silicon film is stacked on the hafnium oxide film, for example, in a thickness of about 100 nm.
[0071]
Next, as shown in FIG. 6C, the polycrystalline silicon film and the hafnium oxide film are selectively patterned by using a lithography method, a dry etching method or the like to form a gate electrode 608 made of a polycrystalline silicon film. And a gate insulating film 607 made of a hafnium oxide film. Subsequently, using the gate electrode 608 and the gate insulating film 607 as a mask, the SOI substrate 601 is doped with an impurity in a self-aligning manner by ion implantation to form source and drain regions 609 and 610. For example, in the case of an N-channel MISFET, an N-type impurity such as As or P is used, and in the case of a P-channel MISFET, a P-type impurity such as B is used.^-2~ 3E15cm^-2About to inject.
[0072]
Further, for example, rapid heating of about several seconds is performed by using a lamp heating method or the like to activate the doped impurities. Including the heat treatment in the subsequent steps, the junction depth of the source and drain regions 690 and 610 is_1-xGe_xDo not exceed the surface where the layer and the underlying silicon contact.
[0073]
After that, an unillustrated SiO_TwoIs deposited on the entire surface of the SOI substrate 601. A contact hole is opened in the interlayer insulating film, and a W contact and a metal wiring such as Al and Cu are formed on the gate electrode 608 and the source and drain regions 609 and 610. Further, if necessary, deposition of an interlayer insulating film and formation of a metal wiring are repeated to form a multilayer wiring structure. Then, the entire surface of the SOI substrate 601 is covered with a surface protection film (not shown), and a pad portion is opened to form a MISFET. Complete the semiconductor device including.
[0074]
In the semiconductor device described in this embodiment, the potential barrier between the channel and the drain is eliminated, the resistance when electric charge flows from the channel to the drain is suppressed, and the operation of the MISFET can be sped up. In the SOI structure, the parasitic capacitance of the drain region is smaller than that of the silicon substrate, so that the speed of the MISFET can be further increased.
[0075]
Further, the present invention is not limited to the above-described embodiment at all. For example, as a gate insulating film, a hafnium oxide film, SiO 2_TwoBesides, it may be SiOxNy, SiNx, HfOxNy, AlOx, ZrOx, ZrOxNy, or the like. The gate electrode may be a mixed crystal of polycrystalline silicon and polycrystalline germanium, a metal, or a metal silicide other than polycrystalline silicon. Further, the gate side wall, extension region, salicide, and the like in the source and drain regions may be selected as needed, and the materials and elements used at that time are not limited to the embodiment. In addition, various modifications can be made without departing from the gist of the present invention.
[0076]
【The invention's effect】
As described above in detail, according to the semiconductor device including the insulated gate field effect transistor of the present invention and the method of manufacturing the same,_1-xGe_xIn a MISFET using a layer, the source and drain regions are_1-xGe_xBy forming in the layer, a potential barrier between the channel and the drain can be eliminated, and the resistance between the channel and the drain can be reduced.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 2 is a cross-sectional view showing the order of steps of a second embodiment of a method of manufacturing a semiconductor device according to the present invention.
FIG. 3 is a sectional view showing a third embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 4 is a cross-sectional view showing a fourth embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 5 is a sectional view showing a fifth embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 6 is a sectional view showing a sixth embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIG. 7 shows a conventional and present invention._1-xGe_xFIG. 4 is a schematic view of an energy band structure of a junction between a channel and a drain of a semiconductor device using a layer.
[Explanation of symbols]
101, 201, 301, 401, 501 Silicon substrate
102, 202, 302, 402, 502, 604 Element isolation region
103, 203, 304, 504, 606 Si_1-xGe_xlayer
104, 205, 306, 408, 506, 607 Gate insulating film
105, 206, 307, 409, 507, 608 Gate electrode
106, 107, 207, 208, 311, 312 Source and drain regions
413, 414, 514, 515, 609, 610 Source and drain regions
204, 305, 505 Silicon layer
303, 303, 403, 503, 605 Silicon buffer layer
308, 309, 410, 411, 509, 510 Extension area
310, 412, 511 sidewall insulating film
313, 314, 315, 415, 416, 417 Nickel silicide layer
404 First Si_1-xGe_xlayer
405 first silicon layer
406 Second Si_1-xGe_xlayer
407 Second silicon layer
508 Silicon nitride film
512, 513 Si of source and drain regions_1-xGe_xlayer
601 SOI substrate
602 insulation separation layer
603 silicon active layer

Claims (11)

A semiconductor substrate having a surface region made of silicon;
A mixed crystal semiconductor layer made of silicon and germanium formed on the semiconductor substrate,
A gate insulating film formed on the mixed crystal semiconductor layer,
A gate electrode formed on the gate insulating film;
It has a source and drain region formed in the mixed crystal semiconductor layer so that the junction depth does not exceed the mixed crystal semiconductor layer while sandwiching the mixed crystal semiconductor layer below the gate insulating film. A semiconductor device including an insulated gate field effect transistor. 2. The semiconductor device according to claim 1, further comprising an extension region having a junction depth smaller than that of the source and drain regions and formed in the mixed crystal semiconductor layer. 3. 3. The semiconductor device including the insulated gate field effect transistor according to claim 1, wherein a silicon layer is formed on the mixed crystal semiconductor layer. 4. The semiconductor device according to claim 1, wherein the mixed crystal semiconductor layer and the silicon layer are alternately stacked on the mixed crystal semiconductor layer and the silicon layer formed thereon. 5. 12. A semiconductor device comprising the insulated gate field effect transistor according to claim 1. 5. The semiconductor device including the insulated gate field effect transistor according to claim 1, further comprising a buffer layer made of silicon between the semiconductor substrate and the mixed crystal semiconductor layer. Forming an element isolation region on a semiconductor substrate having a surface region made of silicon, and forming an element region surrounded by the element isolation region;
Forming a mixed crystal semiconductor layer made of silicon and germanium on the element region,
Laminating a gate insulating film and a gate electrode on the mixed crystal semiconductor layer,
Forming a source and a drain region in the mixed crystal semiconductor layer so that the mixed crystal semiconductor layer sandwiches the mixed crystal semiconductor region under the gate insulating film and the junction depth does not exceed the mixed crystal semiconductor layer; A method for manufacturing a semiconductor device including an insulated gate field effect transistor, comprising: Forming an extension region having a junction depth smaller than that of the source and drain regions in the mixed crystal semiconductor layer between the step of forming the gate electrode on the gate insulating film and the step of forming the source and drain regions; 7. A method for manufacturing a semiconductor device including an insulated gate field effect transistor according to claim 6, comprising: 8. The insulated gate field effect transistor according to claim 6, further comprising a step of forming a silicon layer on the mixed crystal semiconductor layer following the step of forming the mixed crystal semiconductor layer. And a method for manufacturing a semiconductor device. The method according to claim 1, further comprising, after the step of forming the silicon layer on the mixed crystal semiconductor layer, a step of alternately stacking a mixed crystal semiconductor layer and a silicon layer on the silicon layer. A method for manufacturing a semiconductor device including the insulated gate field effect transistor according to claim 6. The method according to any one of claims 6 to 9, further comprising a step of forming a buffer layer made of silicon between the step of forming the element isolation region and the step of forming the mixed crystal semiconductor layer. A method of manufacturing a semiconductor device including an insulated gate field effect transistor. Between the step of forming the extension region and the step of forming the source and drain regions,
Selectively removing the source and drain regions;
Forming a mixed crystal semiconductor layer selectively in the removed region. 11. The method of manufacturing a semiconductor device including an insulated gate field effect transistor according to claim 6, further comprising the step of: Method.

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