JPH11329997A - 貼り合わせ基材とその作製方法 - Google Patents
貼り合わせ基材とその作製方法Info
- Publication number
- JPH11329997A JPH11329997A JP13391198A JP13391198A JPH11329997A JP H11329997 A JPH11329997 A JP H11329997A JP 13391198 A JP13391198 A JP 13391198A JP 13391198 A JP13391198 A JP 13391198A JP H11329997 A JPH11329997 A JP H11329997A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- ion
- layer
- bonded
- implanted layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Element Separation (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13391198A JPH11329997A (ja) | 1998-05-15 | 1998-05-15 | 貼り合わせ基材とその作製方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13391198A JPH11329997A (ja) | 1998-05-15 | 1998-05-15 | 貼り合わせ基材とその作製方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11329997A true JPH11329997A (ja) | 1999-11-30 |
| JPH11329997A5 JPH11329997A5 (enExample) | 2005-09-29 |
Family
ID=15115986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13391198A Withdrawn JPH11329997A (ja) | 1998-05-15 | 1998-05-15 | 貼り合わせ基材とその作製方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11329997A (enExample) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002084738A1 (en) * | 2001-04-06 | 2002-10-24 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and its manufacturing method |
| WO2009011152A1 (ja) * | 2007-07-13 | 2009-01-22 | National University Corporation Tohoku University | Soi基板およびsoi基板を用いた半導体装置 |
| JP2011091264A (ja) * | 2009-10-23 | 2011-05-06 | Japan Atomic Energy Agency | 基板加工方法および半導体装置の製造方法 |
| KR20140142699A (ko) * | 2012-03-05 | 2014-12-12 | 소이텍 | 반도체 온 절연체 구조를 테스트하는 방법 및 이러한 구조의 제조를 위한 그 테스트의 적용 |
-
1998
- 1998-05-15 JP JP13391198A patent/JPH11329997A/ja not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002084738A1 (en) * | 2001-04-06 | 2002-10-24 | Shin-Etsu Handotai Co.,Ltd. | Soi wafer and its manufacturing method |
| US7560313B2 (en) | 2001-04-06 | 2009-07-14 | Shin-Etsu Handotai Co., Ltd. | SOI wafer and method for producing the same |
| WO2009011152A1 (ja) * | 2007-07-13 | 2009-01-22 | National University Corporation Tohoku University | Soi基板およびsoi基板を用いた半導体装置 |
| JPWO2009011152A1 (ja) * | 2007-07-13 | 2010-09-16 | 国立大学法人東北大学 | Soi基板およびsoi基板を用いた半導体装置 |
| JP2011091264A (ja) * | 2009-10-23 | 2011-05-06 | Japan Atomic Energy Agency | 基板加工方法および半導体装置の製造方法 |
| KR20140142699A (ko) * | 2012-03-05 | 2014-12-12 | 소이텍 | 반도체 온 절연체 구조를 테스트하는 방법 및 이러한 구조의 제조를 위한 그 테스트의 적용 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050512 |
|
| A621 | Written request for application examination |
Effective date: 20050512 Free format text: JAPANESE INTERMEDIATE CODE: A621 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20060307 |