JPH11297748A - Manufacture of semiconductor package - Google Patents
Manufacture of semiconductor packageInfo
- Publication number
- JPH11297748A JPH11297748A JP10102306A JP10230698A JPH11297748A JP H11297748 A JPH11297748 A JP H11297748A JP 10102306 A JP10102306 A JP 10102306A JP 10230698 A JP10230698 A JP 10230698A JP H11297748 A JPH11297748 A JP H11297748A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- electrode
- mounting board
- resin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
- H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体チップの金属
突起部と実装基板の電極との結線を行うボンディング工
程において、最初その金属突起部の結線を仮接合として
おき、次工程の樹脂封止後に、その金属突起部を高温に
て溶融させることにより電極の本接合を行う半導体パッ
ケージの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding step for connecting a metal projection of a semiconductor chip to an electrode of a mounting substrate, in which the connection of the metal projection is firstly temporarily joined, and after the next step of resin sealing, The present invention also relates to a method of manufacturing a semiconductor package in which electrodes are fully joined by melting the metal projections at a high temperature.
【０００２】[0002]
【従来の技術】従来の半導体パッケージの製造方法に関
して、電極の接合工程と樹脂封止の工程については以下
のような方法が取られていた。 （１）まず半導体チップの金属突起部を溶融させて電極
の接続を行った後に、次の樹脂封止する方法。 （２）最初に半導体チップの金属突起部を実装基板の電
極に接触させ、この状態を維持させながら樹脂封止を行
い、その樹脂の硬化により最終的に電極の接続を行う方
法。 （３）予め実装基板に溶融金属部を設置して置き、そし
て半導体チップの金属突起部と接合させて後、樹脂封止
する方法。 （４）まず半導体チップの金属突起部と実装基板の電極
を、導電性のペーストにより接続して導通を確保し、そ
の後、樹脂封止する方法。 （５）予め半導体チップと実装基板との間に異方性導電
材料を設置し、そして半導体チップの金属突起部と実装
基板の金属突起部とを、この異方性導電材料の導電粒子
を介して接合することにより導電を確保する方法。この
方法によれば異方性導電材料が樹脂封止の樹脂の役割を
も併せ持っている。2. Description of the Related Art With respect to a conventional method of manufacturing a semiconductor package, the following methods have been adopted for an electrode bonding step and a resin sealing step. (1) A method in which the metal projections of the semiconductor chip are first melted to connect the electrodes, and then the following resin sealing is performed. (2) A method in which the metal projections of the semiconductor chip are first brought into contact with the electrodes of the mounting substrate, resin sealing is performed while maintaining this state, and finally the electrodes are connected by curing the resin. (3) A method in which a molten metal portion is previously set on a mounting board, and is bonded to a metal projection of a semiconductor chip, and then sealed with a resin. (4) A method in which the metal protrusions of the semiconductor chip and the electrodes of the mounting board are connected by a conductive paste to ensure conduction, and then the resin is sealed. (5) An anisotropic conductive material is placed between the semiconductor chip and the mounting substrate in advance, and the metal protrusion of the semiconductor chip and the metal protrusion of the mounting substrate are interposed via the conductive particles of the anisotropic conductive material. A method of securing conductivity by joining together. According to this method, the anisotropic conductive material also has a role of a resin for resin sealing.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記説明の従
来の半導体パッケージの製造方法については、以下のよ
うな問題点があった。即ち、 （ａ）上記の（１）の場合、半導体チップの金属突起部
が高融点金属であれば溶融時間が長く必要となり、従っ
てボンディングに時間がかかる。しかし、一方ハンダの
ような低融点金属を用いれば溶融時間は短く良いが、溶
融後のフラックス洗浄等の時間が必要となり、何れにし
ても工数は多くかかる。又、この方法では、半導体チッ
プの金属突起部のピッチが狭い場合、金属突起部の溶融
したヒゲ状の跳ね返りにより、隣接する金属突起部が短
絡してしまう恐れもある。 （ｂ）上記の（２）の場合、樹脂の硬化が完了するまで
半導体チップを固定して置かなければならず、従ってボ
ンディングに時間がかかる。 （ｃ）上記の（３）の場合、実装基板に設置される溶融
金属は均一性と平坦度の良いことが求められるため、実
装基板の管理が難しくコストが高くなる。又、この方法
でも、半導体チップの金属突起部のピッチが狭い場合に
は、金属突起部の溶融したヒゲ状の跳ね返りにより、隣
接する金属突起部が短絡してしまう恐れがある。 （ｄ）上記の（４）の場合、金属溶融接続でないために
信頼性に乏しく、それ故、接触抵抗が大きくなる恐れが
ある。又、この方法では、ペーストのはみ出しがある場
合、これにより隣接する金属突起部が短絡してしまう恐
れがある。 （ｅ）上記の（５）の場合、設置された異方性導電材料
の硬化が完了するまで半導体チップを固定して置かなけ
ればならず、従ってボンディングに時間がかかる。又、
導電粒子を介しての間接的な接合であるために信頼性に
乏しい。本発明はこれらの問題点を解決し、ボンディン
グ時間も短く、それ故、加工工数も少なく、従ってコス
トを低減でき、且つ信頼性の高い半導体パッケージの製
造方法を提供することを目的としている。However, the conventional method of manufacturing a semiconductor package described above has the following problems. That is, (a) In the case of the above (1), if the metal projection of the semiconductor chip is a high melting point metal, a long melting time is required, and therefore, a long time is required for bonding. On the other hand, if a low melting point metal such as solder is used, the melting time can be short, but a time such as flux cleaning after the melting is required, and in any case, the number of steps is large. Further, in this method, when the pitch of the metal projections of the semiconductor chip is narrow, there is a possibility that the adjacent metal projections may be short-circuited due to the rebound of the metal projections in the form of a mustache. (B) In the case of the above (2), the semiconductor chip must be fixed and placed until the curing of the resin is completed, so that it takes a long time for bonding. (C) In the case of the above (3), since the molten metal provided on the mounting board is required to have good uniformity and flatness, it is difficult to manage the mounting board and the cost is high. Also in this method, when the pitch of the metal projections of the semiconductor chip is narrow, there is a possibility that the adjacent metal projections may be short-circuited due to the rebound of the metal projections in the form of a mustache. (D) In the case of the above (4), the reliability is poor because it is not a metal fusion connection, and therefore, the contact resistance may increase. Also, in this method, if the paste is protruding, there is a possibility that the adjacent metal protrusions may be short-circuited. (E) In the case of the above (5), the semiconductor chip must be fixed and placed until the hardening of the placed anisotropic conductive material is completed, so that the bonding takes time. or,
Poor reliability due to indirect bonding via conductive particles. An object of the present invention is to solve these problems and to provide a highly reliable method of manufacturing a semiconductor package which has a short bonding time, and therefore requires a small number of processing steps, thereby reducing costs.
【０００４】[0004]
【課題を解決するための手段】そこで本発明においては
上記の課題を以下に示す第一〜第二の手段により解決し
た。まず第一に、半導体基板表面の電極上に金属突起部
１を形成した半導体チップ２を反転させて、該金属突起
部１と実装基板３に形成した電極４とを位置合わせして
接合した後、上記半導体チップ２と上記実装基板３間を
樹脂４でモールドする半導体パッケージの製造方法にお
いて、上記樹脂モールド後に上記金属突起部１または上
記実装基板の電極４のいずれか一方、あるいは上記金属
突起部１と上記実装基板の電極４の両方を加熱溶融させ
て上記金属突起部１と上記電極４間を再接合させること
を特徴とする手段によるものである。In the present invention, the above-mentioned problems have been solved by the following first and second means. First, after inverting the semiconductor chip 2 having the metal protrusions 1 formed on the electrodes on the surface of the semiconductor substrate, the metal protrusions 1 and the electrodes 4 formed on the mounting substrate 3 are aligned and joined. In a method of manufacturing a semiconductor package in which a space between the semiconductor chip 2 and the mounting board 3 is molded with a resin 4, either the metal protrusion 1 or the electrode 4 of the mounting board or the metal protrusion after the resin molding. 1 and the electrode 4 of the mounting board are heated and melted to rejoin the metal projection 1 and the electrode 4.
【０００５】次に第二に、上記金属突起部１あるいは上
記電極４を低融点金属層６で被覆し、該低融点金属層６
を加熱溶融させることを特徴とする手段によるものであ
る。Second, the metal projection 1 or the electrode 4 is covered with a low melting point metal layer 6.
Is heated and melted.
【０００６】[0006]
【発明の実施の形態】以下に図１により、上記の手段に
よる本発明の実施形態を示す。図１は本発明の実施例の
模式的概略図である。図は半導体チップを反転させた状
態を示しており、１が金属突起部、２が半導体チップ、
３が実装基板、４が実装基板の電極、５が樹脂、を表し
ている。又、金属突起部１が高融点金属の場合には、そ
の先端部に低融点金属層６を設置することがある。本実
施例では半導体チップ２に、１５μｍ程度の金（Ａｕ）
の金属突起部１を設置し、更に３μｍ程度の錫（Ｓｎ）
の低融点金属層６を、電解メッキ等により形成してあ
る。そして、実装基板の電極４はタングステン（Ｗ）、
又は銅／ニッケル／金（Ｃｕ／Ｎｉ／Ａｕ）により形成
されている。その銅／ニッケル／金（Ｃｕ／Ｎｉ／Ａ
ｕ）は、厚さ１μｍ程度／１．５μｍ程度／１．５μｍ
程度のメタライズにより構成されている。FIG. 1 shows an embodiment of the present invention using the above means. FIG. 1 is a schematic diagram of an embodiment of the present invention. The figure shows a state where the semiconductor chip is inverted, 1 is a metal projection, 2 is a semiconductor chip,
Reference numeral 3 denotes a mounting board, 4 denotes an electrode of the mounting board, and 5 denotes a resin. When the metal projection 1 is made of a high melting point metal, a low melting point metal layer 6 may be provided at the tip thereof. In this embodiment, the semiconductor chip 2 is made of gold (Au) of about 15 μm.
Metal projection 1 is further provided, and tin (Sn) of about 3 μm is further provided.
Is formed by electrolytic plating or the like. Then, the electrode 4 of the mounting substrate is tungsten (W),
Alternatively, it is formed of copper / nickel / gold (Cu / Ni / Au). The copper / nickel / gold (Cu / Ni / A
u) has a thickness of about 1 μm / about 1.5 μm / 1.5 μm
It is composed of a degree of metallization.
【０００７】作業手順は以下の様になる。まず反転させ
た半導体チップ２を、金属突起部１を介して実装基板の
電極４に対面するように位置合わせして設置する。次
に、この状態で低融点金属層６を溶融させて、半導体チ
ップ２と実装基板３とを結合させる。ここで溶融温度と
しては、金属突起部１の溶融したヒゲ状の跳ね返りによ
り、隣接する金属突起部１が短絡しないような温度に設
定する。この場合は１６０〜２３０℃に設定するのが良
い。更に、接合の確実性を確保するために荷重をかけ
る、あるいは超音波を利用することもある。こうして低
融点金属層６の錫（Ｓｎ）と実装基板の電極４のメタラ
イズ上の金（Ａｕ）とにより半導体チップ２と実装基板
３との接合が行われる。そして、毛細管現象を利用して
側面から樹脂５を半導体チップ２と実装基板３との間に
注入して封止をし、所定温度、所定時間で加熱し、樹脂
を硬化させる。通常は温度１５０℃、１時間の条件で樹
脂の硬化を行う。そして最後に、本接合のために温度２
３０〜３００℃の雰囲気中でリフローを行う。これによ
り金属突起部１での仮接合は、低融点金属層６と実装基
板の電極４との合金層の形成により本接合となる。The work procedure is as follows. First, the inverted semiconductor chip 2 is positioned and installed so as to face the electrode 4 of the mounting board via the metal projection 1. Next, in this state, the low melting point metal layer 6 is melted, and the semiconductor chip 2 and the mounting substrate 3 are bonded. Here, the melting temperature is set to a temperature at which the adjacent metal projections 1 are not short-circuited due to the rebound of the metal projections 1 in the form of a mustache. In this case, the temperature is preferably set to 160 to 230 ° C. Further, a load may be applied or ultrasonic waves may be used to ensure the reliability of the joining. Thus, the semiconductor chip 2 and the mounting substrate 3 are joined by the tin (Sn) of the low melting point metal layer 6 and the gold (Au) on the metallization of the electrode 4 of the mounting substrate. Then, the resin 5 is injected between the semiconductor chip 2 and the mounting substrate 3 from the side surface by utilizing the capillary phenomenon to seal the resin, and the resin is heated at a predetermined temperature for a predetermined time to cure the resin. Usually, the resin is cured at a temperature of 150 ° C. for one hour. And finally, temperature 2
Reflow is performed in an atmosphere at 30 to 300 ° C. As a result, the temporary joining at the metal protrusions 1 is a final joining by forming an alloy layer between the low melting point metal layer 6 and the electrode 4 of the mounting board.
【０００８】[0008]
【発明の効果】以上説明したように、本発明のように構
成することにより、従来の半導体パッケージの製造方法
と比較して以下のような効果がある。 （ａ）半導体チップ２の金属突起部１に低融点金属層６
を設置してあるために溶融時間が短く、従ってボンディ
ングに時間がかからない。又、ハンダのような低融点金
属でもないために、溶融後のフラックス洗浄等も不要で
ある。何れも工数削減になる。又、この方法では、半導
体チップ２の金属突起部１のピッチが狭い場合でも、金
属突起部１の溶融したヒゲ状の跳ね返りにより、隣接す
る金属突起部１が短絡してしまう恐れが無い。 （ｂ）樹脂の硬化が完了するまで半導体チップを固定し
て置く必要が無い。従ってボンディングに時間がかから
ない。 （ｃ）従来の実装基板３に設置される溶融金属は均一性
と平坦度の良いことが求められるため、実装基板の管理
が難しくコストが高くなったが、本発明では、その必要
が無い。 （ｄ）従来の導電性のペーストによる接合とは違い、金
属溶融接続であるために信頼性に優る。それ故に、接触
抵抗が大きくなる恐れが無い。又、従来の導電性のペー
ストによる方法では、ペーストのはみ出しがある場合に
は、これにより隣接する金属突起部１が短絡してしまう
恐れがあったが、本発明では、その恐れが無い。 （ｅ）従来の異方性導電材料による接合とは違い、材料
の硬化が完了するまで半導体チップを固定して置く必要
が無い。従って、ボンディングに時間がかからない。
又、導電粒子を介しての間接的な接合ではないために信
頼性に優る。その他にも、最初の接合は仮接合であるた
めに１個のボンディングは短時間で良く、次の工程で複
数個を一括して本接合できるため、高価な設備である実
装機への投資を軽減できる。又、製品のスループットが
改善され生産性が向上すると言う効果もある。As described above, the configuration according to the present invention has the following effects as compared with the conventional semiconductor package manufacturing method. (A) Low melting point metal layer 6 on metal projection 1 of semiconductor chip 2
, The melting time is short, and therefore the bonding does not take much time. Further, since it is not a low-melting metal such as solder, it is not necessary to wash the flux after melting. In any case, the man-hour is reduced. Further, according to this method, even when the pitch of the metal projections 1 of the semiconductor chip 2 is narrow, there is no possibility that the adjacent metal projections 1 are short-circuited due to the rebound of the metal projections 1 in the form of a mustache. (B) There is no need to fix and place the semiconductor chip until the curing of the resin is completed. Therefore, no time is required for bonding. (C) Since the molten metal placed on the conventional mounting board 3 is required to have good uniformity and flatness, it is difficult to manage the mounting board and the cost is high. However, the present invention does not need to do so. (D) Unlike the conventional bonding using a conductive paste, the reliability is superior because of the metal fusion connection. Therefore, there is no possibility that the contact resistance increases. Further, in the conventional method using a conductive paste, when the paste overflows, there is a possibility that the adjacent metal protrusions 1 may be short-circuited, but the present invention does not. (E) Unlike conventional bonding using an anisotropic conductive material, there is no need to fix the semiconductor chip until the material is completely cured. Therefore, no time is required for bonding.
In addition, since it is not an indirect joining through conductive particles, the reliability is excellent. In addition, since the first bonding is a temporary bonding, a single bonding can be performed in a short time, and a plurality of final bonding can be performed at the same time in the next process. Can be reduced. Also, there is an effect that the throughput of the product is improved and the productivity is improved.
【図１】本発明の実施例であるところの半導体パッケー
ジの製造方法の模式的概略図。FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor package according to an embodiment of the present invention.
１……金属突起部 ２……半導体チップ ３……実装基板 ４……実装基板の電極 ５……樹脂 ６……低融点金属層 DESCRIPTION OF SYMBOLS 1 ... Metal projection part 2 ... Semiconductor chip 3 ... Mounting board 4 ... Electrode of mounting board 5 ... Resin 6 ... Low melting point metal layer
Claims (2)
形成した半導体チップを反転させて、該金属突起部と実
装基板に形成した電極とを位置合わせして接合した後、
上記半導体チップと上記実装基板間を樹脂モールドする
半導体パッケージの製造方法において、上記樹脂モール
ド後に上記金属突起部または上記実装基板の電極のいず
れか一方、あるいは上記金属突起部と上記実装基板の電
極の両方を加熱溶融させて上記金属突起部と上記電極間
を再接合させることを特徴とする半導体パッケージの製
造方法。1. A semiconductor chip having a metal projection formed on an electrode on a surface of a semiconductor substrate is inverted, and the metal projection and an electrode formed on a mounting substrate are aligned and joined.
In the method of manufacturing a semiconductor package in which the semiconductor chip and the mounting board are resin-molded, any one of the metal protrusion and the electrode of the mounting board after the resin molding, or the metal protrusion and the electrode of the mounting board A method of manufacturing a semiconductor package, wherein both are heated and melted to rejoin the metal projection and the electrode.
点金属層で被覆し、該低融点金属層を加熱溶融させるこ
とを特徴とする請求項１記載の半導体パッケージの製造
方法。2. The method of manufacturing a semiconductor package according to claim 1, wherein said metal protrusion or said electrode is covered with a low melting point metal layer, and said low melting point metal layer is heated and melted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10230698A JP3827442B2 (en) | 1998-04-14 | 1998-04-14 | Manufacturing method of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10230698A JP3827442B2 (en) | 1998-04-14 | 1998-04-14 | Manufacturing method of semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11297748A true JPH11297748A (en) | 1999-10-29 |
| JP3827442B2 JP3827442B2 (en) | 2006-09-27 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10230698A Expired - Fee Related JP3827442B2 (en) | 1998-04-14 | 1998-04-14 | Manufacturing method of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3827442B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002078079A1 (en) * | 2001-03-26 | 2002-10-03 | Citizen Watch Co., Ltd. | Package of semiconductor device and its manufacturing method |
| JP2014036103A (en) * | 2012-08-08 | 2014-02-24 | Panasonic Corp | Mounting method |
-
1998
- 1998-04-14 JP JP10230698A patent/JP3827442B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002078079A1 (en) * | 2001-03-26 | 2002-10-03 | Citizen Watch Co., Ltd. | Package of semiconductor device and its manufacturing method |
| US7053479B2 (en) | 2001-03-26 | 2006-05-30 | Citizen Watch Co., Ltd. | Package of semiconductor device and its manufacturing method |
| JP2014036103A (en) * | 2012-08-08 | 2014-02-24 | Panasonic Corp | Mounting method |
| US9508679B2 (en) | 2012-08-08 | 2016-11-29 | Panasonic Intellectual Property Management Co., Ltd. | Mounting method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3827442B2 (en) | 2006-09-27 |
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