JPH11297697A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11297697A JPH11297697A JP10098002A JP9800298A JPH11297697A JP H11297697 A JPH11297697 A JP H11297697A JP 10098002 A JP10098002 A JP 10098002A JP 9800298 A JP9800298 A JP 9800298A JP H11297697 A JPH11297697 A JP H11297697A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- semiconductor device
- wiring layer
- aluminum
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は特に、半導体装置に
おける配線構造に関する。The present invention particularly relates to a wiring structure in a semiconductor device.
【０００２】[0002]
【従来の技術】図２の如く、半導体基板２０１上に化学
気相成長法（ＣＶＤ法）により二酸化シリコン膜からな
る絶縁膜２０２が約８００ｎｍ形成され、次にフォトリ
ソ、エッチング工程により接続孔２０３を形成する。次
に第１金属配線層（Ｔｉ）２０４をスパッタ法により厚
さ０．０１５μｍ程度、第２金属配線層（ＴｉＮ）２０
５を０．０３μｍ程度、次に厚さ０．９μｍ程度の第３
金属配線層（アルミニウム）２０６を形成する。その
後、反射防止第３金属配線層２０７を０．０３μｍ程度
形成し、その後フォトリソグラフィー、エッチング法に
より所望のパターンに形成する。2. Description of the Related Art As shown in FIG. 2, an insulating film 202 made of a silicon dioxide film is formed on a semiconductor substrate 201 by a chemical vapor deposition method (CVD method) to a thickness of about 800 nm. Form. Next, the first metal wiring layer (Ti) 204 is sputtered to a thickness of about 0.015 μm and the second metal wiring layer (TiN) 20 is formed.
5 is about 0.03 μm and then a third about 0.9 μm thick.
A metal wiring layer (aluminum) 206 is formed. Thereafter, an anti-reflection third metal wiring layer 207 is formed to a thickness of about 0.03 μm, and then formed into a desired pattern by photolithography and etching.
【０００３】[0003]
【発明が解決しようとする課題】しかしながらこのよう
な単層の配線では結晶表面の粒界が多く、特に３つの粒
界が集まるトリプルポイントの数が多く電子が移動して
ボイド、ヒロックなどが発生し易い。そのためエレクト
ロマイグレーション耐性やストレスマイグレーション耐
性が悪く、信頼性を向上させるのは困難であった。However, in such a single-layer wiring, there are many grain boundaries on the crystal surface, and in particular, the number of triple points where three grain boundaries are gathered is large, and electrons move to generate voids and hillocks. Easy to do. Therefore, electromigration resistance and stress migration resistance are poor, and it has been difficult to improve reliability.
【０００４】[0004]
【課題を解決するための手段】半導体装置において金属
配線層（アルミニウム）の中間に第２の金属配線ＴｉＮ
を挟む構造にする。金属配線（アルミニウム）の膜厚は
０．８μｍ以下に形成し（アルミニウムのグレインサイ
ズは０．８μｍ程度であるため。）、多層配線構造の半
導体装置の第２層目配線以降も同様の形状であることを
特徴とする半導体装置。In a semiconductor device, a second metal wiring TiN is provided between metal wiring layers (aluminum).
Is sandwiched. The thickness of the metal wiring (aluminum) is formed to be 0.8 μm or less (because the grain size of aluminum is about 0.8 μm), and the same shape is applied to the second wiring and the subsequent wirings of the semiconductor device having the multilayer wiring structure. A semiconductor device, comprising:
【０００５】[0005]
【発明の実施の形態】（実施例１）図１は本発明の１実
施例に於ける半導体装置の主要断面図の一例である。実
施例の全図に於いて、同一の機能を有するものには同一
の符号を付けその繰り返しの説明は省略する。(Embodiment 1) FIG. 1 is an example of a main cross-sectional view of a semiconductor device according to an embodiment of the present invention. In all the drawings of the embodiment, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
【０００６】以下図１断面図により詳細に説明する。A detailed description will be given below with reference to FIG.
【０００７】半導体基板１０１上に化学気相成長（ＣＶ
Ｄ）法により二酸化シリコン膜からなる絶縁膜１０２を
約８００ｎｍ形成する。フォトレジストをマスク材とし
て用いたフォトリソグラフィーとエッチング工程を施す
ことにより直径約０．７μｍ程度の接続孔１０３を形成
する。次にスパッタ法により第１金属配線層１０４（Ｔ
ｉ）を０．０１５μｍ程度形成する。次にスパッタ法に
より第２金属配線層１０６（ＴｉＮ）を０．０３μｍ程
度形成する。次に第３金属配線層１０６（アルミニウ
ム）を０．７μｍ程度形成する。次に第４金属配線層１
０７（ＴｉＮ）を０．０３μｍ程度形成する。次に第５
金属配線層１０９（アルミニウム）を前記第３金属配線
層１０６（アルミニウム）と同程度の０．７μｍ程度ス
パッタ法により形成する。次にフォトリソ工程での反射
防止のための第６金属配線層１０９（ＴｉＮ）を約０．
０３μｍ程度形成する。次に前記第１金属配線層、前記
第２金属配線層、前記第３金属配線層、前記第４金属配
線層、前記第５金属配線層、前記第６金属配線層を同時
にフォトリソ、エッチング工程を施すことにより所望の
パターンに形成する。[0007] Chemical vapor deposition (CV)
An insulating film 102 made of a silicon dioxide film is formed to a thickness of about 800 nm by the method D). By performing photolithography using a photoresist as a mask material and an etching step, a connection hole 103 having a diameter of about 0.7 μm is formed. Next, the first metal wiring layer 104 (T
i) is formed to a thickness of about 0.015 μm. Next, a second metal wiring layer 106 (TiN) is formed to a thickness of about 0.03 μm by a sputtering method. Next, a third metal wiring layer 106 (aluminum) is formed to a thickness of about 0.7 μm. Next, the fourth metal wiring layer 1
07 (TiN) is formed to a thickness of about 0.03 μm. Then the fifth
The metal wiring layer 109 (aluminum) is formed by the same sputtering method as the third metal wiring layer 106 (aluminum) of about 0.7 μm. Next, a sixth metal wiring layer 109 (TiN) for preventing reflection in a photolithography process is added to a thickness of about 0.1 mm.
It is formed to a thickness of about 03 μm. Next, the first metal wiring layer, the second metal wiring layer, the third metal wiring layer, the fourth metal wiring layer, the fifth metal wiring layer, and the sixth metal wiring layer are simultaneously subjected to photolithography and etching steps. By applying, a desired pattern is formed.
【０００８】以上のようにアルミニウムの配線層の中間
（アルミニウム配線層の膜厚はアルミニウム単結晶の大
きさより短く、少なくとも０．８μｍ以下で形成する）
に第２金属絶縁膜１０７を挟むことにより、単層のアル
ミニウム配線に比べて電子が移動しやすい結晶粒界が減
る。アルミニウム配線層はエレクトロマイグレーション
耐性が最も良くなるバンブー構造となる。バンブー構造
となったアルミニウム配線層はアルミニウムのグレイン
の移動が起きにくくボイド、ヒロックが発生しにくくな
る。また、アルミニウム配線は前記第４金属配線層１０
７（ＴｉＮ）によって２層に分割されているので片側の
アルミニウム配線層で断線が起こってももう一方のアル
ミニウム配線層には電流を流すことが可能である。その
ためさらにエレクトロマイグレーション耐性が向上す
る。アルミニウム配線層の中間に形成する膜はできれば
ＴｉＮが望ましい。ＴｉＮはぬれ性が高く、ＴｉＮ上に
形成するアルミニウム配線層が形成しやすくなる。特に
コンタクトなどの接続孔中に形成されるアルミニウム配
線のカバレッジが良くなるからである。As described above, the middle of the aluminum wiring layer (the thickness of the aluminum wiring layer is shorter than the size of the aluminum single crystal and formed at least 0.8 μm or less)
By interposing the second metal insulating film 107, the number of crystal boundaries at which electrons easily move is reduced as compared with a single-layer aluminum wiring. The aluminum wiring layer has a bamboo structure with the best electromigration resistance. In the aluminum wiring layer having a bamboo structure, aluminum grains hardly move, and voids and hillocks hardly occur. Further, the aluminum wiring is formed in the fourth metal wiring layer 10.
Since it is divided into two layers by 7 (TiN), even if a disconnection occurs in one aluminum wiring layer, a current can flow in the other aluminum wiring layer. Therefore, the electromigration resistance is further improved. The film formed in the middle of the aluminum wiring layer is preferably made of TiN if possible. TiN has high wettability, and an aluminum wiring layer formed on TiN is easily formed. In particular, the coverage of the aluminum wiring formed in the connection hole such as a contact is improved.
【０００９】[0009]
【発明の効果】以上述べたように、本発明によればアル
ミニウムの配線層の中間（アルミニウム配線層の膜厚は
アルミニウムのグレインサイズより小さく、少なくとも
０．８μｍ以下で形成する）に第４金属絶縁膜１０７を
挟むことにより、単層のアルミニウム配線に比べて電子
が移動しやすい結晶粒界が減り、バンブー構造となる。
バンブー構造となったアルミニウム配線層はアルミニウ
ム結晶の移動が起きにくくボイド、ヒロックが発生しに
くくなる。また、アルミニウム配線はＴｉＮを中間に挟
むことにより２層に分割されているので片側のアルミニ
ウム配線層で断線が起こってももう一方のアルミニウム
配線層には電流を流すことが可能である。そのためさら
にエレクトロマイグレーション耐性及びストレスマイグ
レーション耐性の向上を図ることが可能になり、より信
頼性の高い半導体装置の配線を提供することができる。As described above, according to the present invention, the fourth metal is formed in the middle of the aluminum wiring layer (the thickness of the aluminum wiring layer is smaller than the grain size of aluminum and is formed at least 0.8 μm or less). By sandwiching the insulating film 107, crystal grain boundaries in which electrons easily move are reduced as compared with a single-layer aluminum wiring, and a bamboo structure is obtained.
In the aluminum wiring layer having the bamboo structure, the movement of aluminum crystal hardly occurs, and voids and hillocks hardly occur. Further, since the aluminum wiring is divided into two layers by sandwiching TiN in the middle, even if a disconnection occurs in one aluminum wiring layer, a current can flow through the other aluminum wiring layer. Therefore, it is possible to further improve the electromigration resistance and the stress migration resistance, and it is possible to provide a more reliable wiring of a semiconductor device.
【図１】本発明の半導体装置の製造方法の一例を説明す
るための主要断面図である。FIG. 1 is a main cross-sectional view for explaining an example of a method for manufacturing a semiconductor device of the present invention.
【図２】従来の半導体装置の製造方法の一例を説明する
ための主要断面図である。FIG. 2 is a main cross-sectional view illustrating an example of a conventional method for manufacturing a semiconductor device.
１０１、２０１・・・半導体基板 １０２、２０２・・・第１絶縁膜層 １０３、２０３・・・接続孔 １０４、２０４・・・第１金属配線層（Ｔｉ） １０５、２０５・・・第２金属配線層（ＴｉＮ） １０６、２０６・・・第３金属配線層（アルミニウム） １０７、２０７・・・第４金属配線層（ＴｉＮ） １０８・・・第５金属配線層（アルミニウム） １０９・・・第６金属配線層（ＴｉＮ） 101, 201 ... semiconductor substrate 102, 202 ... first insulating film layer 103, 203 ... connection hole 104, 204 ... first metal wiring layer (Ti) 105, 205 ... second metal Wiring layers (TiN) 106, 206: Third metal wiring layer (Aluminum) 107, 207: Fourth metal wiring layer (TiN) 108: Fifth metal wiring layer (Aluminum) 109: No. 6 metal wiring layer (TiN)
Claims (5)
第２の金属配線ＴｉＮを挟み、前記金属配線の膜厚は
０．８μｍ以下に形成し、多層配線構造の半導体装置の
第２層目配線以降も同様の形状であることを特徴とする
半導体装置。In a semiconductor device, a second metal wiring TiN is interposed between metal wiring layers, the thickness of the metal wiring is formed to be 0.8 μm or less, and the second wiring of the semiconductor device having a multilayer wiring structure is formed. A semiconductor device having the same shape after wiring.
の主成分とする金属配線層の材質は、少なくともアルミ
ニウム、銅、金、銀、亜鉛、白金、鉄であることを特徴
とする半導体装置。2. The semiconductor device according to claim 1, wherein:
A semiconductor device, characterized in that the material of the metal wiring layer as a main component of is at least aluminum, copper, gold, silver, zinc, platinum, and iron.
の主成分とする金属配線層の材料は、少なくともチタニ
ウム、タングステン、モリブデン、チッ化チタン、チッ
化タングステン、チッ化モリブデン、チタンナイトライ
ドであることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein
A semiconductor device, characterized in that the material of the metal wiring layer as a main component is at least titanium, tungsten, molybdenum, titanium nitride, tungsten nitride, molybdenum nitride, and titanium nitride.
２の金属配線層（ＴｉＮ）を挟む形状の前記第１の金属
配線層（アルミニウム）の膜厚は前記第１の金属配線層
に使用した物質のグレインサイズ（アルミニウムなら
０．８μｍ程度）より小さいことを特徴とする半導体装
置。4. The semiconductor device according to claim 1, wherein a thickness of said first metal wiring layer (aluminum) sandwiching said second metal wiring layer (TiN) is used for said first metal wiring layer. A semiconductor device having a grain size smaller than the grain size (about 0.8 μm for aluminum).
２の金属配線層（ＴｉＮ）を挟む２層の前記第１の金属
配線層（アルミニウム）の膜厚はそれぞれ同程度とする
ことを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein two first metal wiring layers (aluminum) sandwiching said second metal wiring layer (TiN) have substantially the same thickness. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10098002A JPH11297697A (en) | 1998-04-09 | 1998-04-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10098002A JPH11297697A (en) | 1998-04-09 | 1998-04-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11297697A true JPH11297697A (en) | 1999-10-29 |
Family
ID=14207489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10098002A Withdrawn JPH11297697A (en) | 1998-04-09 | 1998-04-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11297697A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8278667B2 (en) | 2009-08-11 | 2012-10-02 | Fuji Xerox Co., Ltd. | Light-emitting element and light-emitting element fabrication method |
-
1998
- 1998-04-09 JP JP10098002A patent/JPH11297697A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8278667B2 (en) | 2009-08-11 | 2012-10-02 | Fuji Xerox Co., Ltd. | Light-emitting element and light-emitting element fabrication method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050705 |