JPH11176835A - Structure of multi-layer wiring and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve adhesion between a metal layer and an interlayer insula tion film during polishing process for wiring metal film by chemical machine polishing by forming a dummy wiring groove pattern flush with a wiring layer of an isolated pattern in the vicinities. SOLUTION: A CVD plasma oxide film is formed on an interlayer film on the backing wiring. Next, a photoresist mask of a wiring groove is formed and the wiring groove is processed by a mask containing a dummy pattern, and the wiring groove is processed by dry etching. Next, a tungsten film is formed on the whole surface by a sputtering method and CVD. Then, the tungsten film is polished by metal chemical machine polishing until the thickness becomes equal to that of the interlayer insulation film. At this time, since the dummy wiring groove has been formed, the adhesion between the tungsten metal layer of isolated wiring in the vicinities and the interlayer insulation film layer is improved, and any trouble such as peeling-off of tungsten metal layer and poor adhesion between the wiring in the wiring groove and backing interlayer film does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure of a semiconductor device, and more particularly, to a method of polishing a metal by damascene by chemical mechanical polishing (hereinafter referred to as CMP).
Polishing) and a manufacturing method suitable for a multilayer wiring.

[0002]

2. Description of the Related Art In recent years, in order to meet the increasing demands for higher integration and higher speed of LSIs, miniaturization of wiring width and increase in the number of wiring layers have been promoted. As a technique for flattening a wide area of a wiring interlayer insulating film for realizing a multilayer fine wiring, there is CMP. Semiconductor manufacturers in the United States have begun research and development of CMP for this wide area planarization technology more than 10 years ago, and IBM and Intel have already applied this technology to some products. As a wiring structure using CMP, there is a wiring structure in which an interlayer insulating film is polished and flattened, and a structure in which a groove for forming a wiring is formed in the interlayer insulating film in advance, a metal is formed and then polished to form a wiring (damascene). can give. The use of damascene can be expected to reduce wiring resistance and improve electromigration resistance, and can be applied to metal materials that are generally difficult to dry-etch because dry etching of metal is not required.

[0003]

SUMMARY OF THE INVENTION In the above-mentioned damascene, C
In the MP technology, when the metal is polished by CMP, there is no clogging of a wiring groove or the like in a portion where the metal and the interlayer insulating film are in contact with a large area around an isolated pattern or a low wiring density pattern. The adhesiveness between the insulating films is reduced (FIG. 1). In particular, copper, tungsten, etc., which have poor adhesion to the silicon oxide film, apply stress to the bonding surface during the CMP process, and a large area around the isolated pattern portion where the metal and the interlayer insulating film are in contact with each other. There is a problem that the insulating film is peeled off (FIG. 2). The exfoliated metal causes foreign matter and causes a reduction in yield. Further, the adhesion between the metal wiring remaining in the wiring groove and the interlayer insulating film is reduced, which causes a reduction in reliability such as electromigration (FIG. 3).

[0004]

A film such as a W film having poor adhesion to an oxide film has a low pattern density and has poor adhesion when an interlayer film and a metal are in contact with each other over a wide area.
There is a problem of peeling. Peeling did not occur in the portion where the pattern density was high. This is because not only the contact area is increased due to the unevenness of the pattern, but also the adhesion between the metal and the oxide film is improved by being caught by the unevenness.
Taking advantage of this, when forming a metal polishing process by damascene using CMP, in a wiring groove forming step for forming an isolated wiring and a pattern having a low pattern density, the wiring layer is formed around the isolated pattern. A dummy wiring groove pattern is formed in the same layer, and the CM of the wiring metal film is formed.
In the polishing step using P, the adhesion between the metal layer and the interlayer insulating film can be improved by increasing the number of hooks caused by the dummy wiring grooves.

[0005] Thereby, even in a portion where the density of the wiring pattern during the metal CMP process is low, the adhesiveness between the metal and the interlayer insulating film can be improved, and peeling of the metal and the interlayer insulating film can be prevented. It is possible to suppress a decrease in yield due to the peeled metal foreign matter. Further, since the adhesiveness between the metal wiring and the interlayer insulating film is also improved, it is possible to suppress the occurrence of a decrease in wiring reliability such as electromigration.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, description will be made sequentially according to embodiments.

(Embodiment 1) CVD on underlying wiring and interlayer film
A 0.4 μm plasma oxide film is formed (FIG. 4). A photoresist mask for the wiring groove is formed using a mask including a dummy pattern, and the wiring groove is processed by dry etching (FIG. 5). A tungsten film is formed to a thickness of 0.1 μm or 1.0 μm on the entire surface by sputtering and CVD (FIG. 6). Next, the W film is polished by metal CMP until the thickness becomes the thickness of the interlayer insulating film (FIG. 7). At this time, since the dummy wiring groove is formed, the adhesion between the metal W layer around the isolated wiring and the interlayer insulating film layer is improved, the metal layer is peeled off, and the bonding between the wiring in the wiring groove and the underlying interlayer film is performed. No degradation occurs. As a result, it is possible to suppress a decrease in yield due to metal foreign matter and a decrease in wiring reliability due to electromigration (FIG. 8).

[Brief description of the drawings]

FIG. 1 shows an example in which adhesiveness between a metal and an interlayer insulating film is reduced.

FIG. 2 shows an example in which an interlayer insulating film on a pattern is peeled off.

FIG. 3 shows an example in which peeled metal causes foreign matter.

FIG. 4 shows a diagram in which a CVD plasma oxide film is formed on an underlying wiring and an interlayer film.

FIG. 5 shows a diagram in which a wiring groove is processed by dry etching.

FIG. 6 shows a diagram in which a tungsten film is formed on the entire surface by sputtering and CVD.

FIG. 7 shows a diagram in which a W film is polished by metal CMP to a thickness of an interlayer insulating film.

FIG. 8 shows an example in which the adhesion between the metal W layer and the interlayer insulating film layer around the isolated wiring is improved because the dummy wiring groove is formed.

Claims (3)

[Claims] In a multilayer wiring structure having a wiring structure formed by chemical mechanical polishing using damascene metal polishing, a wiring groove is formed around a wiring groove for forming an isolated wiring and a wiring pattern having a low pattern density. Improves adhesion between the wiring metal layer around the isolated wiring and the interlayer insulating film, and between the wiring metal in the wiring groove and the underlying interlayer insulating film by forming a wiring groove dummy pattern formed in the same layer as A multilayer wiring structure characterized by having been made. 2. A method for forming a groove for embedding metal in an interlayer insulating film, wherein a wiring groove for a dummy pattern is arranged around an isolated wiring and a groove for a wiring pattern having a low pattern density. By forming a wiring groove for a dummy pattern with a mask, forming a wiring material, and flattening the wiring by metal chemical mechanical polishing, the adhesiveness between the wiring metal layer and the interlayer insulating film around the isolated wiring, and the wiring A method for manufacturing a multilayer wiring, wherein the adhesiveness between a wiring metal in a groove and an underlying interlayer insulating film is improved. 3. In the above structure, the wiring material is copper, tungsten, molybdenum, chromium, nickel, titanium nitride, titanium, titanium, a laminated film of these films, or a laminated film of these films and aluminum. The multilayer wiring structure according to claim 1, wherein: