JP2000031147A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of thinning, without increasing the resistance of an embedded wiring a dual-damascene process. SOLUTION: In this manufacturing method, a via hole 5 and a wiring groove 6 are formed on a second interlayer insulating film 3, after a CMP stopper film 4 has been formed. Then, after a linear film 7 is formed, connecting electrodes and metal films 8 as embedded wirings are formed on the entire surface, so as to embed the inside parts of the via hole 5 and the wiring groove 6. Then a process, which removes excess CMP at the outside of the via hole 5 and the wiring groove 6, is provided. The film thickness of the CMP stopper film 4 is made sufficiently large. A second interlayer insulating film 3 is prevented from being polished by CMP. Furthermore, the film thickness of the liner film 7 is made small, and the increase in the resistance of the dual- damascene wiring 8 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring structure, and more particularly to a method for manufacturing a semiconductor device having a damascene type wiring structure.

[0002]

2. Description of the Related Art Present Ultra Large Scale Integrated Circuit (ULSIC)
In general, a multilayer wiring in which three or more embedded wirings are connected to each other is used. Conventionally, this kind of multilayer wiring has been formed as follows.

First, after a photoresist is applied on a metal film to be a first buried wiring, the photoresist is exposed and developed by photolithography to form a photoresist pattern having the buried wiring pattern.

Next, the metal film is anisotropically etched using the photoresist pattern as a mask, and the pattern of the photoresist pattern is transferred to the metal film to form an embedded wiring. Thereafter, the photoresist pattern is peeled off and the first
Embedded wiring is completed.

Next, after forming a first interlayer insulating film on the entire surface so as to cover the first embedded wiring, a via hole reaching the first embedded wiring is formed in the interlayer insulating film by photolithography and etching. I do.

Next, after a metal is buried in the via hole to form a connection plug electrode, a second buried wiring is formed in the same manner as in the case of the first buried wiring. This second buried wiring is connected to the first buried wiring via the connection plug electrode.

By repeating the series of steps described above as many times as necessary, a multilayer wiring is completed. However, in the conventional method of forming a multilayer wiring of this kind, the following two problems become remarkable as the degree of integration increases. (1) As the integration becomes higher, the pattern of the embedded wiring becomes finer. Therefore, as the degree of integration increases, it becomes increasingly difficult to form a buried wiring by etching a metal film. (2) The width between the buried wirings becomes narrower with higher integration. Accordingly, it becomes increasingly difficult to completely fill the voids between the buried wirings with the interlayer insulating film as the degree of integration increases. This kind of void causes a decrease in reliability. .

In order to solve such a problem, a so-called dual damascene process has been proposed as a method for forming a buried wiring and a connection plug electrode. The dual damascene process is outlined below.

First, as shown in FIG. 3A, a first embedded wiring 82 is formed in a _first interlayer insulating film 811. The embedded wiring 82 itself is also formed by a dual damascene process described below.

[0010] Next, as shown in FIG.
Forming an interlayer insulating film 81 _2. The thickness of the interlayer insulating film 81 ₂ is equal to the sum of the depth of the via hole 84 and the thickness of the second buried wiring (the depth of the wiring groove) forming later, for example in the range of 0.5~5μm Value.

Next, as shown in FIG. 3C, after a photoresist pattern 83 for forming a via hole is formed,
And the photoresist pattern 83 as a mask, the interlayer insulating film 81 ₂ is etched by RIE to form a via hole 84 reaching the buried wiring 82. Thereafter, the photoresist pattern 83 is stripped.

[0012] Next, as shown in FIG. 3 (d), after forming a photoresist pattern 85 for forming a wiring trench, and the photoresist pattern 85 as a mask, etching the interlayer insulating film 81 ₂ by RIE And via hole 84
A wiring groove 86 connected to the buried wiring 82 is formed. The depth of the wiring groove 86 is equal to the design value of the thickness of the second embedded wiring made of the metal film 87 formed in the next step, and is, for example, a value in the range of 0.1 to 3 μm. After this,
The photoresist pattern 85 is stripped.

Next, as shown in FIG. 3E, a metal film 87 to be a connection plug electrode and a second buried wiring is formed on the entire surface so as to bury the inside of the via hole 84 and the wiring groove 86.

The metal film 87 is formed by using, for example, a CVD method or a PVD method. Further, as a material of the metal film 87, for example, tungsten, aluminum, copper, an alloy of aluminum and copper, or the like can be used.

Here, before forming the metal film 87, a thin film or a laminated thin film made of an alloy or a metal such as titanium nitride, tungsten silicon nitride, niobium or tantalum is formed on the surface of the via hole 84 and the wiring groove 86. Is also commonly practiced. These are also intended to be formed by a CVD method or a PVD method, the thin film or object of laminated thin film prevents the diffusion of an interlayer insulating film 81 ₂ of the constituent metals of the promotion and metal film 87 deposited metal film 87 It is in.

Finally, as shown in FIG. 3F, an excess metal film 87 outside the via hole 84 and the wiring groove 86 is formed.
Is removed by CMP, the second buried wiring made of the metal film 87 and the connection plug electrode are simultaneously formed in the wiring groove 86 and the via hole 84, respectively. That is, the dual damascene wiring 87 is completed.

By repeating the series of steps described above as many times as necessary, a multilayer wiring is completed. The dual damascene process solves the two problems mentioned above.

That is, in the dual damascene process, since the second buried wiring is formed by burying the metal film 87 in the wiring groove, it is difficult to form a fine pattern by etching the metal film. Can be avoided.

Further, since the second buried wiring is formed by burying the metal film 87 in the wiring groove 86, the interlayer insulating film 81 is formed between the second buried wiring and the second buried wiring at the same time. _Since it is buried with ₂ , it is possible to prevent the generation of voids that cause a reduction in reliability.

Here, the method for forming the metal film 87 is as follows.
Either a physical film forming method such as a sputtering method or a chemical film forming method such as a CVD method may be used. However, in consideration of the processing cost and the maturity of the technology, it is preferable to use the physical film forming method. .

However, when the physical film forming method is used, there are the following problems. That is, FIG.
As shown in the figure, when the wiring pattern has a dense area and a coarse area, the metal film 87 formed in the dense area of the wiring pattern is replaced with the metal film 8 formed in the coarse area of the wiring pattern.
7, the height of the surface is reduced.

[0022] Thus, the excess metal film 87 is removed by CMP, your are also polished interlayer insulating film 81 ₂ At this time, as shown in FIG. 4 (b), before polishing of the metal film 87
Of the surface (cross-sectional shape) is directly reflected on the surface shape after polishing.

As a result, the thickness of the wiring becomes uneven, so that the resistance value of the wiring changes depending on the density of the wiring pattern. Such a change in the resistance value of the wiring adversely affects the performance of the chip as a whole. This phenomenon is known as "thinning".

This problem can be solved by the method shown in FIG. In this method, as shown in FIG. 5A, a metal film 87 is formed after a liner film 88 having a function as a CMP stopper is formed on the entire surface.

Therefore, even if the surplus metal film 87 is removed by CMP in the next step, the CMP stops at the liner film 88, so that the surplus metal film 87 is selectively removed as shown in FIG. Can be removed.

After that, as shown in FIG. 5C, the excess liner film 88 outside the wiring groove 86 is removed by dry etching or CMP. As described above, by stopping the CMP with the liner film 88, the step originally formed on the surface of the metal film 87 is removed from the CM.
It is not necessary to reflect the shape after P.

However, the drawback of this method is that it is almost impossible to completely stop the CMP of the metal film 87 with the liner film 88, and when the metal film 87 is polished and removed, some of the liner film 88 is also removed. Would.

This is because, when the entire surface of the wafer is polished, the polishing rate differs depending on the location, and therefore, in order to compensate for the difference in the polishing rate, the polishing must be performed excessively.

Therefore, the liner film 8 due to excessive polishing
The thickness of the liner film 88 must be designed in consideration of the removal of the liner 8. For example, assuming that the level difference of the metal film 87 is a typical value of 400 nm, even if the ratio of the polishing rate of the metal film 87 to the polishing rate of the liner film 88 is a considerably large value of 20, the liner film 88 has a large height. The thickness must be greater than 20 nm. If the selectivity of the polishing rate is smaller as usual, a thicker liner film 88 is required.

However, the wiring width in the current semiconductor device is already less than 250 nm, and it is expected that it will be narrower in the future. Usually, since the liner material has a considerably higher resistance value than the connection plug electrode, an embedded wiring having a wiring width of 250 nm and a thickness of 250 nm is used, for example.

In this case, about 23% of the conductive cross-sectional area is lost in the liner film having a thickness of 20 nm. Since the resistance value of the buried wiring increases in accordance with the loss, it cannot be used for a high-performance semiconductor device. This problem becomes more important in future semiconductor devices in which the width and thickness of the embedded wiring are further reduced.

[0032]

As described above, in the conventional dual damascene process, in order to solve the problem of so-called thinning by the liner film, the volume of the groove is reduced by the liner film. A new problem arises in that the resistance of the embedded wiring increases.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device capable of solving the problem of thinning without increasing the resistance of an embedded wiring. Is to do.

[0034]

Means for Solving the Problems To achieve the above object, a method for manufacturing a semiconductor device according to the present invention comprises a step of forming a protective film on an insulating film, Are sequentially etched to form a wiring groove in a laminated film composed of the protective film and the insulating film, and a first conductive film is formed on the laminated film so as to cover the surface of the wiring groove. A step of forming a second conductive film on the entire surface so as to fill the inside of the wiring groove with the first conductive film interposed therebetween, and shaving the insulating film by protecting the insulating film with the protective film. Forming a buried wiring made of the second conductive film by removing the first and second conductive films outside the wiring groove without forming the wiring.

In another method for manufacturing a semiconductor device according to the present invention, a step of forming a first wiring layer on a semiconductor substrate and a step of forming an insulating film on the semiconductor substrate so as to cover the first wiring layer are provided. Forming a protective film on the insulating film; etching the protective film and the first insulating film to form a first film on the laminated film including the protective film and the first insulating film; Forming a connection hole reaching the wiring layer and a wiring groove reaching the first wiring layer through the connection hole; and exposing the wiring groove and the surface of the connection hole, and the bottom surface of the connection hole. Forming a first conductive film on the laminated film so as to cover the surface of the first wiring; and forming a first conductive film on the entire surface so as to fill the wiring groove and the connection hole through the first conductive film. (2) a step of forming a conductive film; By protecting the buried wiring made of the second conductive film by removing the first and second conductive films outside the wiring groove and the connection hole without shaving the insulating film by protecting with the protective film. Forming step.

Further, another method of manufacturing a semiconductor device according to the present invention is characterized in that the embedded wiring is formed by using the method of manufacturing a semiconductor device. Preferred modes or more specific configurations of the present invention are as follows. (1) A step of removing the first and second conductive films is performed by CMP using a CMP stopper film as the protective film. (2) The first conductive film is a liner film, and the first conductive film and the protective film are conductive films made of the same material or different materials. (3) In the above (2), after the step of removing the second conductive film outside the wiring groove, the protective film outside the wiring groove is removed. (4) The first conductive film is a liner film, and the protective film is an insulating film. (5) In the above (4), after the step of removing the second conductive film outside the wiring groove, the protective film outside the wiring groove is left. (6) The protective film and the first insulating film are sequentially etched to form a connection hole reaching the first wiring layer in a laminated film including the protective film and the first insulating film. The insulating film is sequentially etched to form a wiring groove reaching the first wiring layer through the connection hole in the laminated film.

According to the present invention, the first and second wiring grooves or the insulating film in the region where the connection hole and the wiring groove are not formed (non-wiring region) are provided with the first and second protective films via the protective film. Since the conductive film is formed, excess first and second conductive films on the insulating film in the non-wiring region can be removed without shaving the insulating film in the non-wiring region with the protective film. Therefore, the problem of thinning can be solved.

Further, since the thickness of the protective film and the thickness of the first conductive film are determined independently of each other, the thickness of the protective film can be made large so that its function can be sufficiently exhibited. One conductive film can have a small thickness that does not increase the resistance of the embedded wiring. Therefore, according to the present invention, the problem of thinning can be solved without increasing the resistance of the embedded wiring.

[0039]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. 1 and 2 are process cross-sectional views showing a dual damascene process according to one embodiment of the present invention.

First, as shown in FIG.
First buried wiring 2 is buried in first interlayer insulating film 1 made of iO ₂ . The interlayer insulating film 1 is formed on a silicon substrate (not shown). The embedded wiring 2 itself is also formed by the dual damascene process of the present embodiment described below.

Next, as shown in FIG.
After forming the interlayer insulating film 3, forming the CMP stopper film 4 on the interlayer insulating film 1 _2. Here, the interlayer insulating film 2
The thickness of the second hole is determined by the depth of the via hole formed in a later process and the second
Equal to the total thickness of the embedded wiring of, for example, 0.5 μm.
m to 5 μm.

Examples of the material of the CMP stopper film 4 include metals such as niobium and tantalum, alloys such as titanium nitride and tungsten / silicon nitride, and nonmetals such as carbon. Use the same conductive material as the film. Also, CM
The thickness of the P stopper film 4 is, for example, 10 to 100 nm.

Next, as shown in FIG. 1C, the interlayer insulating film 3 is formed by photolithography and anisotropic etching.
Then, the CMP stopper film 4 is processed, and a via hole 5 for the embedded wiring 2 is formed in the laminated films 3 and 4.

Next, as shown in FIG. 1D, the interlayer insulating film 3 and the CMP stopper film 4 are processed by photolithography and anisotropic etching. A wiring groove 6 reaching the buried wiring 2 via the via hole 5 is formed on the surface.

Here, the depth of the wiring groove 6 is set equal to the thickness of the second embedded wiring. The depth of the wiring groove 6 is, for example, in a range of 0.1 μm to 3 μm. Next, as shown in FIG. 1E, a thin liner film 7 is formed on the entire surface so as to cover the surfaces of the via holes 5 and the wiring grooves 6, and then the insides of the via holes 5 and the wiring grooves 6 are buried. A metal film 8 is formed on the entire surface. The metal film 8 serves as a connection plug electrode and a second buried wiring.

Here, the metal film 8 may be formed by either a physical film forming method such as a sputtering method or a chemical film forming method such as a CVD method. Considering such costs and the maturity of the technology, it is preferable to use the physical film formation method.

The material of the metal film 8 is, for example, tungsten, aluminum, copper, or an alloy of aluminum and copper. As a material of the liner film 7,
Examples include metals such as niobium and tantalum, alloys such as titanium nitride, and tungsten / silicon / nitride. Here, the same conductive material as the CMP stopper film 4 is used.

As in the case of the metal film 8, the liner film 7 may be formed by either a physical film forming method such as a sputtering method or a chemical film forming method such as a CVD method.
The liner film 7 has various purposes such as promoting the growth of the metal film 8 and preventing the constituent materials of the metal film 8 from diffusing into the surroundings.

Next, as shown in FIG. 2A, the metal film 8 is subjected to CMP under the condition that the polishing rate of the liner film 7 is sufficiently lower than the polishing rate of the metal film 8, so that the via holes 4 and Excess metal film 8 outside wiring groove 5 is removed.

Here, although the CMP stopper film 4 and the liner film 7 are made of the same conductive material, the thickness of the CMP stopper film 4 and the thickness of the liner film 7 are determined independently of each other. Can be selected to be sufficiently thick.

Therefore, in consideration of the selectivity of the polishing rate between the metal film 8 and the liner film 7, the thickness of the CMP stopper film 4 is determined so that the CMP stopper film 4 does not disappear during the CMP of the metal film 8. If the thickness of the interlayer insulating film 3 is selected,
It is possible to reliably prevent thinning of the battery.

Since the thickness of the liner film 7 is determined independently of the thickness of the CMP stopper film 4, it can be made sufficiently thin, thereby minimizing the increase in the resistance of the embedded wiring. it can.

For example, a wiring width of 250 nm and a thickness of 250 n
In the case of forming a buried interconnect having a dimension of m, the thickness of the liner film is about 20 nm as described above in the conventional method,
Although about 23% of the conductive cross-sectional area is lost and the resistance increases, according to the present embodiment, the thickness of the liner film 7 is reduced to 7.5.
Since the thickness can be reduced to about nm, a loss of the conductive cross-sectional area of about 8.8% is sufficient, and an increase in resistance can be effectively suppressed.

After the CMP of the metal film 8 is completed, the CMP stopper film 4 and the liner film 7 remain on the interlayer insulating film 3 as shown in FIG. The total film thickness of the remaining CMP stopper film 4 and the liner film 7 is
It is equal to the sum of the initial thickness of the liner film 7 and the initial thickness of the CMP stopper film 4 minus the thickness of the liner film 7 removed by CMP.

Finally, as shown in FIG. 2B, by removing the CMP stopper film 4 and the liner film 7 remaining on the interlayer insulating film 3 by CMP, the connection plug electrode made of the metal film 8 and the second Two embedded wirings are simultaneously formed in the via hole 5 and the wiring groove 6, respectively. That is, the dual damascene wiring 8 is completed.

By repeating the series of steps described above as many times as necessary, a multilayer wiring having a dual damascene structure is completed. In the present embodiment, the case where the wiring groove 6 is formed after the formation of the via hole 5 has been described, but the via hole 5 may be formed after forming the wiring groove 6.

As described above, in the present embodiment, the liner film 7 is formed on the interlayer insulating film 3 in the region where the via hole 5 and the wiring groove 6 are not formed (non-wiring region) via the CMP stopper film 4. And a metal film 8 are formed.

Therefore, the excessive liner film 7 and metal film 8 on the interlayer insulating film 3 in the non-wiring region can be removed without polishing the interlayer insulating film 3 in the non-wiring region by the CMP stopper film 4, thereby reducing the thickness. Problem can be solved.

Since the thickness of the CMP stopper film 4 and the thickness of the liner film 7 are determined independently of each other,
The stopper film 4 can have a large thickness so that its function can be sufficiently exhibited, while the liner film 7 can have a small thickness which does not increase the resistance of the embedded wiring.

Thus, according to this embodiment, the problem of thinning can be solved without increasing the resistance of the embedded wiring. Note that the present invention is not limited to the above embodiment. For example, in the above embodiment, a case has been described in which the material of the CMP stopper film 4 and the material of the liner film 7 are the same conductive material, but they may be different conductive materials. Further, the material of the CMP stopper film 4 may be an insulating material.
There is no need to remove the P stopper film 4, and the process can be simplified.

In the above embodiment, the case where the first wiring layer is the buried wiring 2 has been described. However, an impurity diffusion layer such as a source / drain layer formed on the surface of a silicon substrate may be used.

In the above embodiment, the case of dual damascene wiring has been described. However, the present invention can be applied to the case of simple damascene wiring. In this case, it can be formed by the same process as that of the dual damascene wiring except for the step of forming the connection hole. In addition, various modifications can be made without departing from the scope of the present invention.

[0063]

As described above in detail, according to the present invention, the insulating film in the non-wiring region is not removed by the protective film.
Since the thickness of the protective film and the thickness of the first conductive film in the wiring groove and the like are independently determined, the problem of thinning can be solved without increasing the resistance of the embedded wiring.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a first half of a dual damascene process according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing the latter half of the dual damascene process according to the first embodiment of the present invention.

FIG. 3 is a process sectional view showing a conventional dual damascene process.

FIG. 4 is a process sectional view for explaining a problem of thinning in a conventional dual damascene process.

FIG. 5 is a process sectional view showing a dual damascene process using a conventional liner film that can solve the problem of thinning.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st interlayer insulating film 2 ... Embedded wiring 3 ... 2nd interlayer insulating film 4 ... CMP stopper film (protective film) 5 ... Via hole (connection hole) 6 ... Wiring groove 7 ... Liner film (1st conductive film) 8) Metal film (second conductive film)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomio Katata 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Junichi Wada 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa (72) Inventor Yasushi Oikawa Yasushi Oikawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Yokohama Office (72) Inventor Haruki Nojo 800, Yamano-Ishiki-cho, Yokkaichi-shi, Mie, Japan Toshiba Corporation Inside the Yokkaichi Plant (72) Inventor Katsunori Shiba 8 Shinsugitacho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5F033 AA02 AA04 AA17 AA19 AA29 AA66 AA68 BA12 BA15 BA17 BA25 BA38 BA46 DA04 DA35 DA36 DA36 DA38 EA25 EA33

Claims (8)

[Claims] A step of forming a protective film on the insulating film; a step of sequentially etching the protective film and the insulating film to form a wiring groove in a laminated film including the protective film and the insulating film; Forming a first conductive film on the laminated film so as to cover the surface of the wiring groove; and forming a second conductive film on the entire surface so as to fill the inside of the wiring groove via the first conductive film. Forming, and protecting the insulating film with the protective film,
By removing the first and second conductive films outside the wiring groove without shaving the insulating film, the second
Forming a buried wiring made of a conductive film. A step of forming a first wiring layer on the semiconductor substrate; a step of forming an insulating film on the semiconductor substrate so as to cover the first wiring layer; and forming a protective film on the insulating film. Forming the protective film and the first insulating film, and etching the first film into a laminated film including the protective film and the first insulating film.
Forming a connection hole reaching the wiring layer and a wiring groove reaching the first wiring layer via the connection hole; and exposing the wiring groove and the surface of the connection hole and the bottom surface of the connection hole. Forming a first conductive film on the laminated film so as to cover the surface of the first wiring; and forming a first conductive film on the entire surface so as to bury the inside of the wiring groove and the connection hole via the first conductive film. 2 forming a conductive film, and protecting the insulating film with the protective film,
Removing the first and second conductive films outside the wiring groove and the connection hole without shaving the insulating film, thereby forming a buried wiring made of the second conductive film. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein said buried wiring is formed by using the method of manufacturing a semiconductor device according to claim 1. 4. A step of using a CMP stopper film as said protective film and removing said first and second conductive films by CMP.
3. The method according to claim 1, wherein
13. The method for manufacturing a semiconductor device according to item 5. 5. The method according to claim 1, wherein the first conductive film is a liner film, and the first conductive film and the protective film are conductive films made of the same material or different materials. The method for manufacturing a semiconductor device according to claim 1, wherein: 6. The method of manufacturing a semiconductor device according to claim 5, wherein after the step of removing the second conductive film outside the wiring groove, the protective film outside the wiring groove is removed. Method. 7. The device according to claim 1, wherein said first conductive film is a liner film, and said protective film is an insulating film.
A method for manufacturing a semiconductor device according to claim 2. 8. The semiconductor device according to claim 7, wherein after the step of removing the second conductive film outside the wiring groove, the protection film outside the wiring groove is left. Production method.