JPH11284068A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of voids and short circuiting between wirings. SOLUTION: This device is provided with a semiconductor substrate 10 provided with an element 11, a first silicon oxide film 12 formed thereon, a silicon nitride film 13 formed thereon, a second silicon oxide film 14 formed thereon, a contact hole 16 formed by dry etching with photoresist for the contact hole as a mask, a wiring groove 18 formed through etching with the photoresist for the wiring groove as the mask and metal wirings 20 and 21 embedded in the contact hole 16 and the wiring groove 18. In this case, by eliminating the edge part of the upper end of the contact hole 16 through etching with the photoresist for the wiring groove as the mask, the generation of voids is prevented and short circuiting between the wirings is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, wiring formation by a dual damascene method is expected to be frequently used in the future as a method of manufacturing a semiconductor device because of shortening of steps and resistance to misalignment at the time of exposure. You. Further, the dual damascene method is an indispensable manufacturing method for a semiconductor device in which low resistance of wiring is an important point because it is easy to use a material such as copper which is difficult to etch.

In the dual damascene method, a wiring groove and a contact or via hole are basically formed by forming a contact hole (via hole) pattern on an interlayer insulating film by an exposure method using a normal photoresist. After a contact hole (via hole) is formed by anisotropic dry etching, the photoresist is removed, a wiring groove pattern is formed again by a normal exposure method, and a wiring groove is formed by anisotropic dry etching. And a contact hole (via hole) are simultaneously formed.

In the dual damascene method, a groove may be formed first, and a contact hole or a via hole may be formed later. When the groove is etched, an etching stopper provided in an interlayer insulating film is used. In general, the etching is stopped by controlling the depth of the groove.

A semiconductor device according to a conventional manufacturing method is shown in FIG.
As shown in FIG. 0, a semiconductor substrate 100 having an element or a lower wiring 101, a first insulating film 102 on which the semiconductor substrate 100 is formed, and an etching formed on the first insulating film 102 A stopper film 103;
A second insulating film 104 formed on the etching stopper film 103, a contact hole 105 formed in the first insulating film 102, and a contact hole (via hole) 105 formed on the contact hole (via hole) 105 Wiring groove 106 and a metal wiring 107 buried in the contact hole 105 and the wiring groove 106.

[0006]

However, in the above-described conventional method, since the upper end of the contact hole (via hole) 105 opened inside the wiring groove 106 has an edge shape, the metal is formed. At the time of film formation, the growth rate at the edge portion is high, and there is a problem that voids 108 are formed inside the contact holes (via holes) 105 as shown in FIG. The wiring groove 106 has a larger width-to-depth ratio (small aspect ratio) than the contact hole (via hole) 105, so that even if there is an edge portion, the wiring groove 106 can be sufficiently filled.

In general, the wiring groove 106 and the contact hole (via hole) 105 are buried by RF etching before sputtering of TiN or the like to remove a natural oxide film or the like generated at the contact portion. At this time, if the RF etching amount is sufficiently performed, the upper edge portion of the contact hole (via hole) 105 inside the wiring groove 106 is chamfered, and the subsequent embedding of tungsten or the like becomes good. The edge of the upper end of the groove 106 is also shaved, and as shown in FIG.
There is a problem that a short-circuit portion 109 in which the adjacent wirings 107 are short-circuited may be formed in a place where the distance between them is small.

According to the present invention, it is possible to prevent the occurrence of voids due to defective filling of a contact hole (via hole),
An object of the present invention is to provide a semiconductor device capable of preventing a short circuit between wirings and a method for manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor substrate including an element such as a transistor, and a first substrate formed on the semiconductor substrate.
A silicon oxide film, a silicon nitride film formed on the first silicon oxide film, a second silicon oxide film formed on the silicon nitride film, and a photoresist for a contact hole. A contact hole formed by dry etching, a wiring groove formed by etching using a photoresist for the wiring groove as a mask, and a metal wiring embedded in the contact hole and the wiring groove. Is characterized in that the upper edge portion is removed by etching using the photoresist for the wiring groove as a mask.

According to a second aspect of the present invention, there is provided a semiconductor substrate including a lower wiring, a first silicon oxide film formed on the semiconductor substrate, and a first silicon oxide film formed on the first silicon oxide film. A silicon nitride film, a second silicon oxide film formed on the silicon nitride film, a contact hole formed by dry etching using the photoresist for the contact hole as a mask, and a photoresist for a wiring groove. It has a wiring groove formed by etching as a mask, a contact hole and a metal wiring embedded in the wiring groove, and an edge portion at an upper end of the contact hole is removed by etching using a photoresist for the wiring groove as a mask. It is characterized by having been done.

According to a third aspect of the present invention, there is provided a semiconductor substrate including an element such as a transistor, wherein titanium silicide or cobalt silicide is formed at a contact portion between the element and an upper wiring to reduce contact resistance; A first silicon nitride film formed on a semiconductor substrate;
A first silicon oxide film formed on the first silicon nitride film, a second silicon nitride film formed on the first silicon oxide film, and a second silicon nitride film formed on the second silicon nitride film A second silicon oxide film, a contact hole formed by dry etching using a photoresist for a contact hole as a mask, a wiring groove formed by etching using a photoresist for a wiring groove as a mask, A contact hole and a metal wiring buried in the wiring groove, an edge portion at an upper end of the contact hole is removed by etching using a photoresist for the wiring groove as a mask, and a first portion located under the contact hole is removed. The silicon nitride film is removed by etching using the photoresist for wiring trenches as a mask. To.

According to a fourth aspect of the present invention, when a wiring groove and a contact hole or a via hole are formed by a dual damascene method, the contact hole or the via hole is formed first, and then the wiring groove is formed later.
Next, after the formation of the wiring groove, RF etching is performed while leaving the photoresist used as a mask to remove the upper edge portion of the contact hole or via hole opened inside the wiring groove.

According to a fifth aspect of the present invention, there is provided a step of preparing a semiconductor substrate including an element such as a transistor, a step of forming a first silicon oxide film on a semiconductor substrate, and a step of forming a first silicon oxide film. Forming a silicon nitride film thereon;
Forming a second silicon oxide film on the silicon nitride film, forming a contact hole pattern on the second silicon oxide film by an exposure method using a photoresist for the contact hole, A step of forming a contact hole by dry etching using the photoresist for the hole as a mask, a step of removing the photoresist for the contact hole from the second silicon oxide film, and an exposure method using the photoresist for the wiring groove. Forming a wiring groove pattern, forming a wiring groove by etching using a photoresist for the wiring groove as a mask, and forming an upper edge portion of the contact hole by RF etching using a photoresist for the wiring groove as a mask. Removal process and process to remove photoresist for wiring groove When, characterized in that a step of embedding a metal wiring in the contact hole and wiring groove.

According to a sixth aspect of the present invention, there is provided a step of preparing a semiconductor substrate including a lower wiring, a step of forming a first silicon oxide film on the semiconductor substrate, and a step of forming a first silicon oxide film on the first silicon oxide film. Forming a silicon nitride film, forming a second silicon oxide film on the silicon nitride film, and forming a contact hole pattern on the second silicon oxide film by an exposure method using a photoresist for the contact hole. Forming a contact hole by dry etching using the photoresist for the contact hole as a mask; removing the photoresist for the contact hole from the second silicon oxide film;
Forming a wiring groove pattern by exposure using a photoresist for the wiring groove, forming a wiring groove by etching using the photoresist for the wiring groove as a mask, and using the photoresist for the wiring groove as a mask The method includes a step of removing an edge portion at an upper end of the contact hole by RF etching, a step of removing a photoresist for a wiring groove, and a step of burying a metal wiring in the contact hole and the wiring groove.

According to a seventh aspect of the present invention, there is provided a semiconductor substrate including an element such as a transistor, wherein titanium silicide or cobalt silicide is formed at a contact portion between the element and an upper wiring to reduce contact resistance. Forming a first silicon nitride film on a semiconductor substrate; forming a first silicon oxide film on the first silicon nitride film; and forming a first silicon oxide film on the first silicon nitride film. Forming a second silicon nitride film, forming a second silicon oxide film on the second silicon nitride film, and forming a contact hole pattern by an exposure method using a photoresist for the contact hole. Forming a contact hole on the second silicon oxide film, and forming the contact hole by dry etching using a photoresist for the contact hole as a mask. Performing a step of removing a photoresist for a contact hole from the second silicon oxide film; a step of forming a pattern of a wiring groove by an exposure method using the photoresist for a wiring groove; A step of forming a wiring groove by etching using a resist as a mask; a step of removing an edge portion of an upper end of a contact hole by RF etching using a photoresist for the wiring groove as a mask; and a step of etching using a photoresist for the wiring groove as a mask. The method includes a step of removing the first silicon nitride film, a step of removing a photoresist for a wiring groove, and a step of burying a metal wiring in a contact hole and a wiring groove.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described in detail with reference to FIGS. As shown in FIG. 1, a semiconductor device according to a first embodiment of the present invention includes a semiconductor substrate 10 including an element 11 such as a transistor, and a first silicon oxide film formed on the semiconductor substrate 10. 12
A silicon nitride film 13 formed on the first silicon oxide film 12, a second silicon oxide film 14 formed on the silicon nitride film 13, and a photoresist for a contact hole as a mask. A contact hole 16 formed by dry etching, and a wiring groove 18 formed by etching using a photoresist for the wiring groove as a mask.
The edge of the upper end of 6 is removed by RF etching using the photoresist for the wiring groove as a mask. The TiN film 2 is formed in the contact hole 16 and the wiring groove 18.
0 and a tungsten film 21 are formed.

Next, as shown in FIG. 2, a semiconductor substrate 10 including an element 11 such as a transistor is prepared, and a first silicon oxide film 12 having a thickness of 10000 A is formed on the semiconductor substrate 10 by a plasma CVD method. After the formation, the first silicon oxide film 1 is formed by a chemical mechanical polishing (CMP) method.
2 is polished and flattened. After this polishing, the thickness of the first silicon oxide film 12 is set to 6000 A on the substrate 10. Next, a 5000A silicon nitride film 13 serving as a stopper at the time of groove etching is formed by a plasma CVD method. Further, a second silicon oxide film 14 of 5000 A is formed by a plasma CVD method.

Next, as shown in FIG. 3, a pattern of a contact hole is formed using a photoresist 15 by a normal exposure method. As shown in FIG.
5 is used as a mask to form a contact hole 16 for making a connection with the lower element 11 by anisotropic dry etching. The etching gas is C ₄ F ₈ / CO / Ar / O ₂
= 6/30/180/1 sccm, pressure 40 mt
orr, RF650W. Next, the photoresist 15 is removed. Subsequently, as shown in FIG. 5, a pattern of a wiring groove is formed again by a photoresist 17 using a normal exposure method, and as shown in FIG. 6, anisotropic dry etching is performed using the photoresist 17 as a mask. The wiring groove 18 is formed. The etching condition of the wiring groove 18 is the same as the above-described etching of the contact hole 16. At this time, the etching of the wiring groove 18 is stopped at the silicon nitride film 13. At this stage, the contact hole 16 and the wiring groove 18 are formed, but in the present invention, immediately after the etching of the wiring groove 18, as shown in FIG. Expose. In this step, the edge of the upper end of the contact hole 16 inside the wiring groove 18 is cut and chamfered.

After this treatment, the photoresist 17 is peeled off, and a TiN film 20 of 500 A is formed by a sputtering method as shown in FIG. 8, and further, as shown in FIG.
After the tungsten film 21 of 00A is formed by the CVD method, as shown in FIG. Get rid of. Since the upper end of the contact hole 16 inside the wiring groove 18 is chamfered, the tungsten film 21 is well embedded, and no void is generated inside the contact hole 16. Therefore, increase in contact resistance due to voids and deterioration of electromigration resistance are suppressed, and a high-performance and highly reliable semiconductor device can be realized.

In the first embodiment of the present invention, the element region of the transistor may be replaced with a lower wiring in a semiconductor device having a multilayer wiring.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described in detail with reference to FIGS. As shown in FIG. 10, the semiconductor device according to the second embodiment of the present invention includes an element 31 such as a transistor, and a contact portion between the element 31 and an upper wiring is made of titanium to reduce contact resistance. A semiconductor substrate 30 on which silicide or cobalt silicide 32 is formed; a first silicon nitride film 34 formed on the semiconductor substrate 30; and a first silicon nitride film 34 formed on the first silicon nitride film 34 First silicon oxide film 35
And a second silicon nitride film 36 formed on the first silicon oxide film 35, and a second silicon oxide film 3 formed on the second silicon nitride film 36.
7, a contact hole 39 formed by dry etching using a photoresist for contact holes as a mask, and a wiring groove 41 formed by etching using the photoresist for wiring grooves as a mask. Is removed by RF etching using the photoresist for the wiring groove as a mask, and the first silicon nitride film 34 located under the contact hole 39 is removed by etching using the photoresist for the wiring groove as a mask. Have been. An element isolation film 33 for isolating a plurality of elements 31 is formed on the semiconductor substrate 30. In the contact hole 39 and the wiring groove 41, a TiN film 42 and a tungsten film 43 are formed.

Next, as shown in FIG. 11, a semiconductor substrate 30 including an element 31 such as a transistor is prepared. On the semiconductor substrate 30, a titanium silicide or cobalt silicide 32 is formed in order to reduce contact resistance at a contact portion between the element 31 and an upper wiring. The plurality of elements 31 are separated by an element isolation film 33 made of a silicon oxide film. 500A first
Silicon nitride film 34 is formed by a low pressure CVD method.
The first silicon oxide film 35 of 0000 A is plasma-CV
After the formation by the method D, the first silicon oxide film 35 is polished and flattened by a chemical mechanical polishing (CMP) method.
After the polishing, the film pressure of the first silicon oxide film 35 is set to 6000 A on the semiconductor substrate 30. Next, a second silicon nitride film 36 of 500 A serving as a stopper at the time of etching the wiring groove is formed by a plasma CVD method. Another 500
A 0A second silicon oxide film 37 is formed by a plasma CVD method.

As shown in FIG. 12, a contact hole pattern is formed using a photoresist 38 by a normal exposure method. As shown in FIG. 13, using the photoresist 38 as a mask, a contact hole 39 for making a connection with the lower element 31 is formed by anisotropic dry etching. The etching gas is C ₄ F ₈ / CO / A
Using r / O ₂ = 6/30/180/1 sccm, the pressure is 40 mtorr and the RF is 650 W. At this time, the contact hole 38 is etched by the first silicon nitride film 34.
Stop at Next, the photoresist 38 is removed. Subsequently, as shown in FIG. 14, a pattern of a wiring groove is formed again by the normal exposure method using the photoresist 40, and as shown in FIG. 15, the wiring is formed by anisotropic dry etching using the photoresist 40 as a mask. A groove 41 is formed. The etching conditions for the wiring groove 41 are the same as the etching conditions for the contact hole 39 described above.
At this time, the etching of the wiring groove 41 is stopped at the second silicon nitride film 36.

At this stage, the contact hole 39 and the wiring groove 41 are formed. In the present invention, immediately after the wiring groove 41 is etched, argon is used while leaving the photoresist 40 as shown in FIG. Expose to RF etching. In this step, the edge of the upper end of the contact hole 39 inside the wiring groove 41 is cut and chamfered.
Further, as shown in FIG. 17, the first nitride film 34 remaining at the bottom of the contact hole 39 is removed by etching. At this time, a part of the second silicon nitride film 36 which is a stopper for etching the wiring groove 41 is also removed.

As shown in FIG. 18, after this treatment, the photoresist 40 is peeled off, a TiN film 42 of 500 A is formed by a sputtering method, and as shown in FIG.
After the tungsten film 43 of 00A is formed by the CVD method, as shown in FIG. remove. Since the upper edge portion of the contact hole 39 inside the wiring groove 41 is removed and chamfered, the tungsten film 43 is well embedded, and no void is generated inside the contact hole 39. Therefore, increase in contact resistance due to voids and deterioration of electromigration resistance are suppressed, and a high-performance and highly reliable semiconductor device can be realized.

Further, according to the present embodiment, since the etching of the contact hole 39 is once stopped by the first silicon nitride film 34 and the thin first silicon nitride film 34 is finally removed, the overetch amount is reduced. Less, element 3
Even if the contact hole 39 opened in the contact region with the upper wiring 1 extends over the element isolation, the oxide film for the element isolation is not greatly etched and the isolation performance is not deteriorated.

Further, the wiring groove 41 is formed by RF etching.
When chamfering the upper end of the contact hole 39 inside, the contact resistance is not increased because the silicide in the contact region is not etched.

The present invention can be applied to a case where a via hole is formed instead of a contact hole.

[0029]

According to the present invention, it is possible to prevent the occurrence of voids due to defective embedding of contact holes (via holes) and to prevent short-circuiting between wirings.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 3 is a view for explaining a step of manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 5 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 6 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 7 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 8 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 9 is a view illustrating a step of manufacturing the semiconductor device of FIG. 1;

FIG. 10 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a view illustrating a step of manufacturing the semiconductor device of FIG. 10;

FIG. 12 is a view illustrating a step of manufacturing the semiconductor device of FIG. 10;

FIG. 13 is a view illustrating a step of manufacturing the semiconductor device in FIG. 10;

FIG. 14 is a view illustrating a step of manufacturing the semiconductor device in FIG. 10;

FIG. 15 is a view illustrating a step of manufacturing the semiconductor device of FIG. 10;

FIG. 16 is a view illustrating a step of manufacturing the semiconductor device in FIG. 10;

FIG. 17 is a view illustrating a step of manufacturing the semiconductor device in FIG. 10;

FIG. 18 is a view illustrating a step of manufacturing the semiconductor device in FIG. 10;

FIG. 19 is a view illustrating a step to manufacture the semiconductor device of FIG. 10;

FIG. 20 is a diagram illustrating a main part of a conventional semiconductor device.

FIG. 21 is a diagram illustrating a conventional semiconductor device.

FIG. 22 is a diagram illustrating another conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 11 element 12 first silicon oxide film 13 silicon nitride film 14 second silicon oxide film 15 photoresist 16 contact hole 17 photoresist 18 wiring groove 20 TiN film 21 tungsten film 30 semiconductor substrate 31 element 32 titanium silicide or Cobalt silicide 33 Element isolation film 34 First silicon nitride film 35 First silicon oxide film 36 Second silicon nitride film 37 Second silicon oxide film 38 Photoresist 39 Contact hole 40 Photoresist 41 Wiring groove 42 TiN film 43 Tungsten film

Claims (7)

[Claims] 1. A semiconductor substrate including an element such as a transistor, a first silicon oxide film formed on the semiconductor substrate, and a silicon nitride film formed on the first silicon oxide film A second silicon oxide film formed on the silicon nitride film; a contact hole formed by dry etching using the contact hole photoresist as a mask; and a wiring groove photoresist as a mask. A wiring groove formed by etching; and a metal wiring embedded in the contact hole and the wiring groove. An edge portion at an upper end of the contact hole is etched using a photoresist for the wiring groove as a mask. A semiconductor device characterized by being deleted by the following. 2. A semiconductor substrate including a lower wiring, a first silicon oxide film formed on the semiconductor substrate, a silicon nitride film formed on the first silicon oxide film, A second silicon oxide film formed on the silicon nitride film, a contact hole formed by dry etching using the contact hole photoresist as a mask, and a contact hole formed by using the wiring groove photoresist as a mask. A wiring groove formed, and a metal wiring buried in the contact hole and the wiring groove, and an edge portion at an upper end of the contact hole is removed by etching using the photoresist for the wiring groove as a mask. A semiconductor device characterized by being performed. 3. A semiconductor substrate including an element such as a transistor, wherein titanium silicide or cobalt silicide is formed at a contact portion between the element and an upper wiring to reduce contact resistance; A first silicon nitride film formed; a first silicon oxide film formed on the first silicon nitride film; and a second silicon oxide film formed on the first silicon oxide film A second silicon oxide film formed on the second silicon nitride film; a contact hole formed by dry etching using a photoresist for the contact hole as a mask; A wiring groove formed by etching using a photoresist for mask as a mask, embedded in the contact hole and the wiring groove. An edge portion at an upper end of the contact hole is removed by etching using the photoresist for the wiring groove as a mask, and the first silicon nitride film located below the contact hole is A semiconductor device, which is removed by etching using the photoresist for the wiring groove as a mask. 4. When forming a wiring groove and a contact hole or a via hole by a dual damascene method,
After the formation of the contact hole or the via hole, the formation of the wiring groove is performed later, and then, after the formation of the wiring groove, RF etching is performed while leaving the photoresist used as a mask. A method of manufacturing a semiconductor device, comprising removing an edge portion of an upper end of the contact hole or the via hole opened inside. 5. A step of preparing a semiconductor substrate including an element such as a transistor, a step of forming a first silicon oxide film on the semiconductor substrate, and a step of forming a silicon nitride film on the first silicon oxide film. Forming a second silicon oxide film on the silicon nitride film; and forming a contact hole pattern on the second silicon oxide film by an exposure method using a contact hole photoresist. Forming a contact hole by dry etching using the photoresist for the contact hole as a mask; removing the photoresist for the contact hole from the second silicon oxide film; Forming a pattern of a wiring groove by an exposure method using a photoresist for the wiring; Forming a wiring groove by etching using a resist as a mask; removing an edge portion of an upper end of the contact hole by RF etching using the photoresist for the wiring groove as a mask; and removing the photoresist for the wiring groove. A method of manufacturing a semiconductor device, comprising: a step of removing; and a step of embedding a metal wiring in the contact hole and the wiring groove. 6. A step of preparing a semiconductor substrate including a lower wiring, a step of forming a first silicon oxide film on the semiconductor substrate, and forming a silicon nitride film on the first silicon oxide film. Forming a second silicon oxide film on the silicon nitride film; and forming a contact hole pattern on the second silicon oxide film by an exposure method using a contact hole photoresist. Forming a contact hole by dry etching using the photoresist for the contact hole as a mask; removing the photoresist for the contact hole from the second silicon oxide film; Forming a wiring groove pattern by an exposure method using a photoresist; and forming a photoresist for the wiring groove. Forming a wiring groove by etching as a mask, removing the edge portion of the upper end of the contact hole by RF etching using the photoresist for the wiring groove as a mask, and removing the photoresist for the wiring groove. And a step of burying a metal wiring in the contact hole and the wiring groove. 7. A step of preparing a semiconductor substrate including an element such as a transistor, wherein titanium silicide or cobalt silicide is formed at a contact portion between the element and an upper wiring to reduce contact resistance; Forming a first silicon nitride film on the substrate; forming a first silicon oxide film on the first silicon nitride film; and forming a second silicon oxide film on the first silicon oxide film. Forming a second silicon oxide film on the second silicon nitride film; and forming a contact hole pattern by exposure using a contact hole photoresist. Forming a contact on the second silicon oxide film; and contacting the contact hole by dry etching using the photoresist for the contact hole as a mask. Forming a hole, removing the contact hole photoresist from the second silicon oxide film, forming a wiring groove pattern by an exposure method using the wiring groove photoresist, Forming a wiring groove by etching using a photoresist for the wiring groove as a mask; removing an edge portion of an upper end of the contact hole by RF etching using the photoresist for the wiring groove as a mask; Removing the first silicon nitride film by etching using the photoresist as a mask, removing the photoresist for the wiring groove, and burying a metal wiring in the contact hole and the wiring groove. A method for manufacturing a semiconductor device, comprising: