JPS6057997A - Method of producing multilayer circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a multilayer wiring board suitable for high-density wiring, and particularly to a method for forming a multilayer wiring layer that is planarized and highly reliable.

[Background technology]

In substrates on which multiple semiconductor chips are mounted, wiring tends to be multi-layered as the packaging density increases, and therefore, at least two wiring layers (conductor layers) are overlapped via an interlayer insulating film. At the same time, each wiring layer is made conductive using an interlayer connecting member provided within the interlayer insulating film.

By the way, thin film forming techniques and thick film forming techniques are known for forming this type of interlayer insulating film. These are shown in "IC Mounting Technology" (Japan Microelectronics Association) published by the Japan Industrial Research Council. The thin film formation technology uses a sputtering method etc. to deposit SiO on the lower wiring layer.
, etc., and then form an upper wiring layer thereon. The thin film (insulating film) formed in this way has an advantage of high insulation reliability due to its dense structure, but it is difficult to form a sufficiently thick film due to the principle of film formation. However, there is a problem in that it is difficult to match characteristics and impedance. Moreover, since it is a thin film, the level difference in the 11J pattern of the lower wiring layer appears as it is on the upper surface of the thin film, reducing the coverage of the upper wiring layer and easily causing disconnections such as step breaks.

On the other hand, thick film formation technology is formed using a glass paste printing method, and although it has the advantage of easily obtaining a thick film and matching the characteristic impedance, the formation method is a coating method. There is a problem that defects such as bubbles are likely to occur inside, and these become pinholes, resulting in a decrease in insulation properties, that is, a decrease in the reliability of the insulation film.
). In addition, even in the case of thick film formation technology, if a film is formed on a heavily pressured lower wiring layer and only the upper and lower wiring layers are made conductive through through holes, breaks in the upper wiring layer tend to occur.

[Purpose of the invention]

The purpose of the present invention is to easily achieve the necessary impedance matching, prevent a decrease in reliability between the insulation film and the like due to bottle balls, etc., and planarize the wiring layer to prevent breakage. The object of the present invention is to provide a method for manufacturing multilayer wiring layers that is optimal for high-density wiring.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, after forming a protruding metallization at the interlayer connection part, each insulating film is formed as an interlayer insulating film using a thin film formation technique and a thick film formation technique, and a surface planarization treatment is performed. This makes it possible to easily obtain the film thickness necessary for matching characteristic impedance, improve the reliability of the insulating film due to the density of the thin film, and prevent breakage in the upper wiring layer by flattening it, thereby increasing the wiring height. This is to achieve density.

〔Example〕

FIGS. 1A to 1F are process diagrams illustrating a method according to an embodiment of the present invention.

First, the inner surface of the substrate 1 made of an insulating material such as alumina (A, (3tOs) or insulating silicon (SiC)), KTi (100OA thick), Cu (5In
Thickness), 'll' + (100OA thickness) were sequentially deposited using a wiring pattern mask (not shown).
A lower wiring layer 2 having a predetermined pattern shape as shown in the figure (not shown) is formed. Alternatively, each layer of Ti, Cu, and Ti may be formed into a button on the entire surface, and then patterning may be performed using photolithography. In this case, a glass layer is formed on the substrate 1 by coating, etc. 1. It is preferable to form a wiring pattern after flattening the surface.

Next, a metal such as Cu is vapor-deposited using the mask 3 for interlayer connection, and as shown in FIG. Formation 4. At this time, if electron beam evaporation is used, a large thickness can be obtained in a short time. The thickness of the metallization 4 is preferably about 25 μm.

Next, as a part of the interlayer insulating film 5, an insulating thin film 6 is formed using the Suba-Tsuta method or the Vapor Phase Chemical Reaction (CVD) method (as shown in the figure).
It is formed on the entire surface as shown in C). In this example, the 5i01 film is formed to a thickness of 3 to 5 μm by sputtering. The time required to form a thin film made of these materials does not matter at all as long as the thickness is within this range. Furthermore, extremely high film density can be obtained. Furthermore, with a thickness of this level, stress can be kept low even in thin films that are hard and tend to have large internal stress. Thereafter, a thick insulating film 7 is formed on the entire surface of the thin insulating film 6, as shown in FIG. 6(D), and these two insulating films 6.7 constitute an interlayer insulating film 5. The thick film insulating film 7 is formed of crystallized glass, polyimide resin, etc. by a so-called thick film forming technique such as thick film printing, spray coating, or coating using a spinner, and its thickness is, for example, 3011rIL, which is the thickness of the metallization 4. The thickness shall be no less than that. These methods result in a substantially flat surface. After the thick insulating film 7 is formed, it is stabilized by firing or baking at an appropriate temperature. In this case, the coefficient of thermal expansion of the glabellar insulating film 5 is smaller than that of the substrate 1, and it is preferable to leave compressive stress on the surface in order to prevent the occurrence of cracks.

Next, the interlayer insulating film 5 or metallization 4
The 0 surface is removed by a mechanical or chemical method, and the surface is flattened as shown in FIG. As a specific method, wet etching, dry etching, polishing, etc. are used. At this time, the surface of the metallization 4 is exposed. Then, by forming the upper wiring layer 8 thereon in the same manner as the lower wiring layer 2, it is possible to form a two-layer wiring structure as shown in Figure (F).

Therefore, according to this method, each upper and lower wiring layer has 2.8
Since the interlayer insulating film 5 in between can be flattened, problems such as breakage in the upper wiring layer 8 can be particularly prevented. Further, since the interlayer insulating film 5 formed in this way can easily be made thick as required by the single-layer insulating film 7, matching of characteristic impedance can be carried out in a Dutch-style manner. In addition, crosstalk can be effectively prevented when a signal that changes the cylinder speed is applied to each wiring. Note that since crystallized glass in particular has a large dielectric constant of 7 to 8, it is advantageous to be able to increase the film thickness. On the other hand, since the interlayer insulating film 5 has the thin film insulating film 6 with a dense structure, high insulation properties can be obtained even if defects such as pinholes occur in the thick film insulating film 7. Furthermore, Si formed using the ZW film formation technology
n, even if the film is thin, the dielectric constant is as small as 3.5 to 4, so
In order to obtain the same impedance matching, the thickness of the thick insulating film 7 can be reduced, and the total thickness of the interlayer insulating film 5 can also be reduced. Furthermore, the thin film insulating film 6
Since the lower wiring layer 2 is covered by forming the lower wiring layer 2, there is no fear that the lower wiring layer 2 will be oxidized and worn during thick film formation (baking, etc.).

Here in 1, Figure @2 is an example of forming three wiring layers,
This is possible by repeating the method described above. In the figure, the second layer interlayer insulating film 5A and the third wiring layer 8A are each indicated by a corresponding reference numeral I7 with a suffix attached.

〔effect〕

(1) The interlayer insulating film is a thin film insulating film formed by thin film formation technology,
Thick film formation technology Since the thick insulating film is formed using pressure 1-1, it is possible to easily obtain the film thickness to obtain the required characteristic impedance matching, but it is also possible to easily obtain the film thickness to obtain the required characteristic impedance matching. Insulation defects can be prevented by the thin film, and high insulation properties can be obtained.

(2) After forming the metallization, an interlayer insulating film is formed using thin film formation technology and thick film formation technology, and after this is flattened, the upper wiring layer is formed, so there is a disconnection due to a step in the upper wiring layer. Therefore, a highly reliable wiring structure can be obtained, which is advantageous for higher density.

(3) Since the upper and lower wiring layers are connected by metallization, through-holes can be eliminated, and the upper wiring layer can be cut off due to the through-holes.

] Although the present invention has been specifically described based on the embodiments of the invention made by the above inventor, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Needless to say, it is. For example, the specific technologies and film materials for thin film formation technology and thick film formation technology may also be applied to technologies and materials other than those described above. Although this invention was applied to a mounting board for semiconductor napkins, which is the field of application that formed the background of this invention, it is not limited thereto, and is applicable to multilayer wiring of commonly used printed circuit boards. Furthermore, it can also be applied to multilayer wiring technology formed on semiconductor wafers.

[Brief explanation of drawings]

1A to 1F are manufacturing process diagrams of an embodiment of the present invention, and FIG. 2 is a sectional view of another structural example formed using the same method. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Lower wiring layer, 4.4A...Metallization, 5.5A...Interlayer insulating film, 6,6
A... Thin film insulating film, 7, 7A... Thick film insulating film, R,
8, A... Upper wiring layer. Figure 1 (ff3) (C)

Claims (1)

[Claims] 1. After forming metallization as interlayer connections at required locations on the lower wiring layer, a thin film insulating film and a thick film insulating film are overlaid on the entire surface of the substrate. A method for manufacturing a multilayer wiring board, comprising forming an insulating film, and then flattening the surface of the interlayer insulating film or metallization to form an upper wiring layer. 2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the thin insulating film is formed by a deposition method such as sputtering or vapor deposition. 3. J! of the multilayer wiring board according to claim 1, in which the thick insulating film is formed by a printing method. ! ! How to send. 4. The method for manufacturing a multilayer wiring board according to claim 1 or 2, wherein the surface abrasion is performed by a chemical etching method or a mechanical grinding method.