JPS61271897A - Multilayer wiring circuit board and manufacture thereof - Google Patents

Multilayer wiring circuit board and manufacture thereof

Info

Publication number
JPS61271897A
JPS61271897A JP11224485A JP11224485A JPS61271897A JP S61271897 A JPS61271897 A JP S61271897A JP 11224485 A JP11224485 A JP 11224485A JP 11224485 A JP11224485 A JP 11224485A JP S61271897 A JPS61271897 A JP S61271897A
Authority
JP
Japan
Prior art keywords
circuit board
multilayer wiring
insulating film
wiring circuit
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11224485A
Other languages
Japanese (ja)
Other versions
JPH0682898B2 (en
Inventor
康稔 岩田
正己 寺澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP60112244A priority Critical patent/JPH0682898B2/en
Publication of JPS61271897A publication Critical patent/JPS61271897A/en
Publication of JPH0682898B2 publication Critical patent/JPH0682898B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、多層配線回路基板、特にサーマルプリンタヘ
ッド、光プリンターヘッド、高集積高周波IC搭載用回
路基板等に用いられる、有機高分子絶縁膜を有する多層
配線回路基板に関する。
Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an organic polymer insulating film used for multilayer wiring circuit boards, particularly thermal printer heads, optical printer heads, circuit boards for mounting highly integrated high-frequency ICs, etc. The present invention relates to a multilayer wiring circuit board having a multilayer wiring circuit board.

(従来の技術) 近年の電子技術のめざましい発展に伴い、電子機器の小
型化、l!量化、及びその高性能化の要求は、ますます
増大し、それに伴い、装置部品の高集積化が積極的に計
られつつある。
(Prior art) With the remarkable development of electronic technology in recent years, electronic devices have become smaller and l! Demand for quantification and higher performance is increasing, and as a result, efforts are being made to increase the degree of integration of device components.

そして、この高集積化の方法としては、サーマルプリン
タヘッド、尤プリンタヘッド及び高集積高周波IC搭載
用回路基板などの膜回路部品に多層配線基板を用いて集
積する手法が行なわれている。
As a method for achieving high integration, a method of integrating film circuit components such as thermal printer heads, digital printer heads, and circuit boards for mounting highly integrated high-frequency ICs using multilayer wiring boards has been used.

現在、このような多層配線基板部品には小型化、高密度
化、及び高速信号伝送化の要求が強くあり、小型化・高
密度化の要求に対しては多層配線構造を、高速信号伝送
化の要求に対しては比誘電率の低い絶縁材料を用いるな
ど各種方法及び材料が採用されている。
Currently, there is a strong demand for miniaturization, high density, and high-speed signal transmission for such multilayer wiring board components. Various methods and materials have been adopted to meet these requirements, such as using insulating materials with low dielectric constants.

(発明が解決しようとする問題点) しかしながら、小型化・高密度化された膜回路部品にあ
っては、一般に絶縁層を介して配線導体を二層以上重ね
た多層配線構造となっているため、各層間の接着強度は
、単層品に比べて゛充分強いことが必要であり、さもな
いと配線加工時及び熱処理時においてその界面から剥離
してしまう現象がしばしば発生する。
(Problems to be Solved by the Invention) However, in miniaturized and high-density membrane circuit components, they generally have a multilayer wiring structure in which two or more wiring conductors are stacked with an insulating layer interposed between them. The adhesion strength between each layer must be sufficiently stronger than that of a single-layer product, otherwise peeling from the interface often occurs during wiring processing and heat treatment.

また前記接着強度が充分でないと、成膜された配線導体
上に7オトレノストを塗布し膜加工する工程において、
フォトレジストが配線導体より浮さ又は剥離を生じるこ
とがあり、そのため配線導体のエツチング時に、本末配
線として残すべき部分までも腐食してしまうと言った不
具合が発生する。
In addition, if the adhesive strength is not sufficient, in the step of applying 7 Otrenost on the formed wiring conductor and processing the film,
The photoresist may float or peel off from the wiring conductor, resulting in a problem that when etching the wiring conductor, even the portion that should be left as the final wiring corrodes.

これらはいずれも、界面−二おける化学的結合が弱いた
めと、下地面が充分に平坦化していて接着界面の有効面
積が十分でないことのために発生するものである。
Both of these occur because the chemical bond at the interface is weak and because the underlying surface is sufficiently flattened and the effective area of the adhesive interface is insufficient.

また、絶縁層表面が充分に平坦である場合には、配線加
工時・熱処理時等において、施縁層と配線導体との内部
応力が絶縁層によって吸収緩和されることがほとんどな
いため、膜の剥離やクラックの発生を招くという問題が
ある。
In addition, if the surface of the insulating layer is sufficiently flat, the internal stress between the edge layer and the wiring conductor will hardly be absorbed and relaxed by the insulating layer during wiring processing, heat treatment, etc. There is a problem that peeling and cracking occur.

(問題点を解決するための手段) 本発明者は上記従来技術の間2n、I!r、を解決すべ
く研究を重ねた結果、本発明をなすに至ったものであり
、即ち本発明は、(1)電気絶縁基板上に配線導体と有
機高分子絶縁膜とが多層形J&された多層配線回路基板
において、前記育成高分子絶縁膜には固形物微粒体が充
填されており、かつ該絶縁材料膜の表面粗さは中心線平
均粗さRaが1.5〜0.5μ鶴であることを特徴とす
る多層配線回路基板、及V(2)電気絶縁基板上に、固
形物微粒体が充填された有機高分子絶縁膜と配線導体と
を多層に形成することによって、配線導体と高分子絶縁
材料膜との接着を強固にしたことを特徴とする多層配線
回路基板の製造方法、である。
(Means for Solving the Problems) The inventor of the present invention has discovered that 2n, I! As a result of repeated research to solve the problem, the present invention has been completed.(1) A wiring conductor and an organic polymer insulating film are formed in a multilayer structure on an electrically insulating substrate. In the multilayer wiring circuit board, the grown polymer insulating film is filled with solid particles, and the surface roughness of the insulating material film has a center line average roughness Ra of 1.5 to 0.5μ. A multilayer wiring circuit board characterized by This is a method for manufacturing a multilayer wiring circuit board, characterized in that the adhesion between the substrate and the polymeric insulating material film is strengthened.

次に、セラミック、ガラス等の電気絶縁性基板上に電気
配線導体と無我又は有機高分子絶縁膜層が形成される組
み合わせにおいて、前記高分子絶縁材料にそれと親和力
の強い固形物粒体を充填、混合することによって得ζ)
れる、表面粗化された絶縁膜を有する本発明の多層配線
回路基板についての説明をする。
Next, in a combination in which an electrical wiring conductor and an organic or organic polymer insulating film layer are formed on an electrically insulating substrate such as ceramic or glass, the polymer insulating material is filled with solid particles that have a strong affinity with it. , obtained by mixing ζ)
The multilayer wiring circuit board of the present invention having an insulating film with a roughened surface will be described.

6i)記配線導体としては、アルミニウム(Δ1)、銅
(Cu)、金(A u)、銀−パフノウム(Ag−Pd
)などの導電体材料が用いられ、従来周知のri、膜手
法や蒸着、スパッタ、CVD等の薄膜手法によって成膜
され、そして印刷技術や7オトリングラフイ技術により
配線パターンが加工される。ここにおいて、前記有機高
分子絶縁材料としては7エ/−ル、ブタジェン、ポリイ
ミド等の耐熱性・耐薬品性に摩れた電気絶縁材料が用い
られ、前記電気絶縁材料に充填する固形物微粒体として
は前記高分子絶縁材料と親和力の強い材料である前記高
分子絶縁材料と同系質の粉末状硬化固形物を用いるのが
好適である0京?2親和力の強いものであれば、ガラス
、セラミックスなどの電気絶縁性黒磯材料を用いるのも
好ましい。なかんづく、有機高分子絶縁材料としてのポ
リイミド系樹脂にこれと同系の熱硬化したポリイミド系
樹脂粉末を充填材として充填、混合することは特に推奨
し得る組み会わせ例であるが、ガラス、セラミックスを
充填材として用いる例も良い。
6i) As the wiring conductor, aluminum (Δ1), copper (Cu), gold (Au), silver-Pafnoum (Ag-Pd)
) is used, and a film is formed by conventionally well-known RI, film techniques, vapor deposition, sputtering, CVD, and other thin film techniques, and a wiring pattern is processed by printing technology or 7-orthogonography technology. Here, as the organic polymer insulating material, an electrically insulating material with excellent heat resistance and chemical resistance, such as 7 er/-, butadiene, polyimide, etc., is used, and solid fine particles filled in the electrically insulating material are used. Therefore, it is preferable to use a powdery hardened solid material that is similar to the polymer insulating material and has a strong affinity with the polymer insulating material. It is also preferable to use electrically insulating Kuroiso materials such as glass and ceramics as long as they have a strong affinity. Among other things, filling and mixing polyimide resin as an organic polymer insulating material with heat-cured polyimide resin powder of the same type as a filler is a particularly recommended combination example. It is also good to use it as a filler.

前記高分子絶縁材料に充填する固形物微粒体のサイズに
ついては、前記高分子絶縁材料により形成された絶縁膜
の上に電気配線導体を成膜する場合、径が1〜15μm
体積平均径が7μ(1)程度又はそれ以下であると良好
であり、そうすることにより、その絶縁膜に対する電気
配線導体の段差被覆性と電気配線導体をパターン加工す
るときに用いる7オトレノスト膜の段差被覆性及び絶縁
膜の膜厚ばらつきを抑えることができる。なお、該固形
物微粒体の九槙量は10〜35重量%であり、その形状
は球状であっても、不定形であってもがまわない。
Regarding the size of the solid particles filled in the polymeric insulating material, when an electrical wiring conductor is formed on an insulating film formed of the polymeric insulating material, the diameter is 1 to 15 μm.
It is preferable that the volume average diameter is about 7μ(1) or less, and by doing so, the step coverage of the electrical wiring conductor with respect to the insulating film and the 7 othrenost film used when patterning the electrical wiring conductor are improved. It is possible to suppress step coverage and variations in the thickness of the insulating film. In addition, the amount of solid particles is 10 to 35% by weight, and the shape thereof may be spherical or irregular.

そして前記固形物微粒体を充填した高分子絶縁材料はス
ピンナー、ロールコータ、印刷などの手法によって、電
気絶縁基板上に形成された電気配線導体上に成膜され、
また従来周知の7↑トリソグラフイ技術、印刷技術の採
用によって上下電気配線導体接続用スルーホール又は下
層電気配線導体保護用パターンの形成が行われる。
Then, the polymeric insulating material filled with the solid particles is formed into a film on the electrical wiring conductor formed on the electrically insulating substrate by a method such as a spinner, a roll coater, or printing.
Further, through-holes for connecting upper and lower electrical wiring conductors or patterns for protecting lower-layer electrical wiring conductors are formed by employing conventionally well-known 7↑trilithography technology and printing technology.

ここで、前記固形物微粒体入り高分子絶縁材料の印刷技
術による成膜と上下電気配線導体接続用スルーホール加
工を同時に行う絶縁層形成法について述べる。即ち、電
気絶縁性基板上に電気配線導体を形成した後、メタルマ
スク又はPVA(ポリビニールアルコール)マスクなど
の耐溶M性ステンレススクリーン製版を用いてスクリー
ン印刷により該形成法を実施する。この際において、乾
燥熱処理された絶縁膜の表面粗さは中心線平均粗さくJ
IS−B12O3−1976)Raが1.5μm0程か
それ以下になるように印刷加工を行うことが重要である
。その理由は、絶縁膜上に電気配置IA導体を成膜する
場合と配線導体上の7t)レノスト膜加工をする場合に
おけるそれぞれの膜の段差被覆性及び絶縁層11J7の
ばらつきを抑えるためであり、表面粗さRaが1.5μ
鎗を超えると、第2図に示すごとく、固形物粒体2の一
部が育成高分子絶縁膜(例えば、ポリイミド系樹脂)1
及び電気配線導体層3面から突出して露出し、その結果
電気配線導体層3において断線を生じる問題がある。
Here, a method for forming an insulating layer will be described in which film formation using the printing technique of the polymer insulating material containing solid particles and through-hole processing for connecting upper and lower electrical wiring conductors are simultaneously performed. That is, after forming an electrical wiring conductor on an electrically insulating substrate, the formation method is carried out by screen printing using a melt-resistant M stainless steel screen plate such as a metal mask or a PVA (polyvinyl alcohol) mask. In this case, the surface roughness of the insulating film subjected to dry heat treatment is the center line average roughness J
IS-B12O3-1976) It is important to perform printing so that Ra is about 1.5 μm0 or less. The reason for this is to suppress variations in the step coverage of the respective films and the insulating layer 11J7 when forming the electrically arranged IA conductor on the insulating film and when processing the 7t) Renost film on the wiring conductor. Surface roughness Ra is 1.5μ
As shown in FIG. 2, after passing the spear, a portion of the solid particles 2 forms a grown polymer insulating film (for example, polyimide resin) 1.
There is also a problem in that the wires protrude and are exposed from the surface of the electrical wiring conductor layer 3, resulting in disconnection in the electrical wiring conductor layer 3.

表面粗さが0.5μ鵠より低いと、膜層間の接着強度は
小さくなり、本発明がD的とする強固な接着強度の膜を
有する多層配線回路基板が得られない。
When the surface roughness is lower than 0.5 μm, the adhesive strength between the film layers becomes low, and it is impossible to obtain a multilayer wiring circuit board having a film with strong adhesive strength, which is the objective D of the present invention.

従って、表面粗さはRa0.5〜1.5μ−の範囲が好
適であり、この場合は第1図に示すごとき断面状態とな
る。
Therefore, the surface roughness is preferably in the range of Ra 0.5 to 1.5 .mu.-, and in this case the cross-sectional state as shown in FIG. 1 is obtained.

本発明に係る絶#a III!の接着強度を確かめるた
め、中心線平均粗1さRILが0.2μm以下のポリイ
ミド樹脂絶縁股上にアルミニウム(Δl)の導電体材料
を真空&着法により成膜してフォトリングラフィ扶術に
よりパッドを形成し、粘着性テープにょる引張試験をし
たところ、20%のパッドが剥離を示した。これに討し
て、中心線平均11さRaが0゜5〜1.5μ論のポリ
イミド樹脂絶縁股上に成膜されたアルミニウムはバンド
の剥離を示さなかった(なお、このときのポリイミド乾
燥熱処理条件は200℃×30分であった)。
Absolute #a III according to the present invention! In order to confirm the adhesive strength of the pad, a conductive material of aluminum (Δl) was formed by a vacuum & deposition method on a polyimide resin insulating crotch with a center line average roughness RIL of 0.2 μm or less, and a pad was formed by photolithography. When the pads were formed and subjected to a tensile test using adhesive tape, 20% of the pads showed delamination. In contrast, aluminum film formed on a polyimide resin insulating crotch with a centerline average 11. (200°C x 30 minutes).

ところで本発明の実施方法によると、−回の印刷で成膜
と上下配線導体接続用パターン加工が同時に形成するこ
とがでさるという有利性が生じる。
However, according to the method of implementing the present invention, there is an advantage that film formation and pattern processing for connecting upper and lower wiring conductors can be simultaneously formed in -times of printing.

本発明の実施例工程と従来法工程との比較を下記に示す
A comparison between the example process of the present invention and the conventional process is shown below.

m4」[0ユ    K迷」L0工   本1」■L1
、ポ リ イ  ミ  ド        1.ポ リ
 イ  ミ  ド     1.ポ リ イ  ミ  
ド塗布    塗布    印刷 2、乾燥、熱処理  2.プレベーク  2.熱処理3
.7オトレノス)3.露光 塗布 4、ブレベーク   4.現像 5、露光     5.熱処理 6、現像 フ、ボストベーク 8、ポリイミドエツチング 9.7オトレジスト剥離 (発明の効果) 本発明は以上記載したとおりの慴成であることから、次
のような作用効果を奏するものである。
m4” [0yu K-mei” L0-work book 1” ■L1
, Polyimide 1. Polyimide 1. poly i mi
Coating Coating Printing 2, drying, heat treatment 2. Pre-bake 2. Heat treatment 3
.. 7 Otorenos) 3. Exposure coating 4, Brebake 4. Development 5, exposure 5. Heat treatment 6, Development, Bost bake 8, Polyimide etching 9.7 Otoresist peeling (effects of the invention) Since the present invention is constructed as described above, it exhibits the following effects.

(a)有機高分子絶縁材料に固形物微粒体を充填し絶縁
膜を表面粗化すると接着界面の有効表面積が増加するた
め絶縁膜と上層配線導体との界面における密着性が向上
する。(b)更に表面粗化された絶縁膜上の配線導体を
加工するために使用するフォトレノストの密着性も向上
する。(C)絶縁膜が表面粗化されることにより配線導
体加工・熱処理等を施しても絶縁膜とその上層の配線導
体との内部応力を絶縁膜が吸収緩和するためそれぞれの
膜の剥離やクラックの発生が抑えられる。(d)ポリイ
ミドフェスのような粘着性のある育成高分子材料でも、
固形物微粒体を充填することによりチキントロピー性が
付与され、スクリーンメツシュを通し被印刷体へ転写す
ることが容易になり、スクリーン印刷が可能となる。(
C)そして、−回の印刷で成膜と上下配線導体接続用パ
ターン加工が同時に形成でさるため、従来周知の7オト
リソグラフイ技術によるパターン加工に比ベニ程数が、
172〜l/4に減少する。(r)また、加工そのもの
が単純化されているため信頼性も大幅に改善される。
(a) When an organic polymer insulating material is filled with solid particles and the surface of the insulating film is roughened, the effective surface area of the adhesive interface increases, so that the adhesion at the interface between the insulating film and the upper wiring conductor is improved. (b) Furthermore, the adhesion of photorenost used for processing the wiring conductor on the surface-roughened insulating film is also improved. (C) Due to the surface roughening of the insulating film, even if wiring conductor processing, heat treatment, etc. are performed, the insulating film absorbs and relieves the internal stress between the insulating film and the wiring conductor above it, resulting in peeling and cracking of each film. The occurrence of is suppressed. (d) Even with adhesive growth polymer materials such as polyimide face,
Filling with solid particles gives chicken tropism, which makes it easy to transfer to a printing material through a screen mesh, making screen printing possible. (
C) And, since film formation and pattern processing for connecting upper and lower wiring conductors are simultaneously formed in - times of printing, compared to pattern processing using the conventional well-known 7 otolithography technology,
It decreases to 172 to 1/4. (r) Furthermore, since the processing itself is simplified, reliability is also greatly improved.

(g)有機高分子絶縁材料に対し、熱膨張係数が充分に
小さい固形物を光層することによって、配線導体の熱膨
張係数に近付けることができるため、配線を積層化して
も熱膨張係数差の問題を解消することができ、そのため
それぞれの膜の剥離が防げる。(h)有機高分子絶縁材
料に灯して充分に高い熱伝導率をもつ固形物微粒体(良
熱伝導性セラミックス粉体等)を充填すると、多層配線
回路基板に挿入又は搭載する素子から発生する熱量を運
やかに基板外部へ放熱してしよ)二とができるため、温
度上昇に伴う回路基板の特性劣化が防止できる。
(g) By layering a solid substance with a sufficiently small coefficient of thermal expansion on the organic polymer insulating material, the coefficient of thermal expansion can be made close to that of the wiring conductor, so even if the wiring is laminated, there will be no difference in the coefficient of thermal expansion. This problem can be solved, and peeling of each film can therefore be prevented. (h) When an organic polymer insulating material is filled with solid fine particles (such as ceramic powder with good thermal conductivity) that have a sufficiently high thermal conductivity, generation occurs from elements inserted or mounted on a multilayer wiring circuit board. This allows the amount of heat to be radiated to the outside of the board, thereby preventing deterioration of the characteristics of the circuit board due to temperature rise.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明実施例の一部拡大断面図、第2図は実施
例から外れた同断面図を示す。 1:有機高分子絶縁膜 2:固形物微粒体 3:電気配線導体層
FIG. 1 is a partially enlarged sectional view of an embodiment of the present invention, and FIG. 2 is a partially enlarged sectional view of the embodiment. 1: Organic polymer insulating film 2: Solid fine particles 3: Electric wiring conductor layer

Claims (6)

【特許請求の範囲】[Claims] (1)電気絶縁基板上に配線導体と有機高分子絶縁膜と
が多層形成された多層配線回路基板において、前記有機
高分子絶縁膜には固形物微粒体が充填されており、かつ
該絶縁材料膜の表面粗さは中心線平均粗さRaが1.5
〜0.5μmであることを特徴とする多層配線回路基板
(1) In a multilayer wiring circuit board in which a wiring conductor and an organic polymer insulating film are formed in multiple layers on an electrically insulating substrate, the organic polymer insulating film is filled with solid particles, and the insulating material The surface roughness of the film has a center line average roughness Ra of 1.5.
A multilayer wiring circuit board characterized in that the thickness is 0.5 μm.
(2)固形物微粒体が有機高分子絶縁膜と同系質の熱硬
化物である特許請求の範囲第1項記載の多層配線回路基
板。
(2) The multilayer wiring circuit board according to claim 1, wherein the solid particles are a thermosetting material similar to the organic polymer insulating film.
(3)固形物微粒体及び有機高分子絶縁膜がポリイミド
系樹脂である特許請求の範囲第1項又は第2項記載の多
層配線回路基板。
(3) The multilayer wiring circuit board according to claim 1 or 2, wherein the solid particles and the organic polymer insulating film are polyimide resin.
(4)電気絶縁基板上に、固形物微粒体が充填された有
機高分子絶縁膜と配線導体とを多層に形成することによ
って、配線導体と高分子絶縁材料膜との接着を強固にし
たことを特徴とする多層配線回路基板の製造方法。
(4) By forming a multilayer organic polymer insulating film filled with solid particles and a wiring conductor on an electrically insulating substrate, the adhesion between the wiring conductor and the polymer insulating material film is strengthened. A method for manufacturing a multilayer wiring circuit board, characterized by:
(5)固形物微粒体が有機高分子絶縁膜と同系質の熱硬
化物である特許請求の範囲第4項に記載の多層配線回路
基板の製造方法。
(5) The method for manufacturing a multilayer wiring circuit board according to claim 4, wherein the solid fine particles are a thermosetting material similar to the organic polymer insulating film.
(6)固形物微粒体及び有機高分子絶縁膜がポリイミド
系樹脂である特許請求の範囲第4項又は第5項記載の多
層配線回路基板の製造方法。
(6) The method for manufacturing a multilayer wiring circuit board according to claim 4 or 5, wherein the solid particles and the organic polymer insulating film are polyimide resins.
JP60112244A 1985-05-27 1985-05-27 Multilayer printed circuit board and manufacturing method thereof Expired - Fee Related JPH0682898B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60112244A JPH0682898B2 (en) 1985-05-27 1985-05-27 Multilayer printed circuit board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60112244A JPH0682898B2 (en) 1985-05-27 1985-05-27 Multilayer printed circuit board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS61271897A true JPS61271897A (en) 1986-12-02
JPH0682898B2 JPH0682898B2 (en) 1994-10-19

Family

ID=14581848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60112244A Expired - Fee Related JPH0682898B2 (en) 1985-05-27 1985-05-27 Multilayer printed circuit board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0682898B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504575A (en) * 1973-05-18 1975-01-17
JPS52149358A (en) * 1976-06-08 1977-12-12 Fujitsu Ltd Multilayer wiring method
JPS5845819A (en) * 1982-08-23 1983-03-17 Mitsubishi Electric Corp Electrolytic machining device
JPS58189271A (en) * 1982-04-30 1983-11-04 Toray Ind Inc Ink for screen printing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504575A (en) * 1973-05-18 1975-01-17
JPS52149358A (en) * 1976-06-08 1977-12-12 Fujitsu Ltd Multilayer wiring method
JPS58189271A (en) * 1982-04-30 1983-11-04 Toray Ind Inc Ink for screen printing
JPS5845819A (en) * 1982-08-23 1983-03-17 Mitsubishi Electric Corp Electrolytic machining device

Also Published As

Publication number Publication date
JPH0682898B2 (en) 1994-10-19

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