JPH11295700A - Reflection liquid crystal device and reflection projector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reflection liquid crystal(LC) device with which the reduction of power consumption is attained, degradation of display quality caused by crosstalk is prevented and gradation display is facilitated. SOLUTION: Concerning this reflection LC device, a static RAM(SRAM) of 8 bits and a gradation display circuit 7 are provided under a reflection pixel electrode 1, the count value of the binary counter of 8 bits is outputted from a display control circuit 10 to the gradation display circuit 7 of respective pixels. In the gradation display circuit 7, the coincidence between the gradation data of 8 bits held in the SRAM and said count value is detected by a word line control circuit 8 and a bit line control circuit 9 and when they are coincident, a signal for determining the impression term of ON waveform to the pixel electrode 1 is switched from high level signal to low level signal. Besides, when starting the next scanning period, since said count value and the value of gradation data held in the SRAM are not coincident, said signal is switched to a high level signal. Therefore, the ON waveforms are impressed to the pixel electrode 1 just for the period based on the gradation data and the gradation display is performed for every scanning period for each pixel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of a liquid crystal device, and particularly to the technical field of a reflection type liquid crystal device having a memory cell in a pixel.

[0002]

2. Description of the Related Art In recent years, a liquid crystal device provided with a reflective liquid crystal panel has attracted attention as a liquid crystal device used for electronic equipment such as a notebook personal computer or a liquid crystal projector.

This reflection type liquid crystal panel is composed of, for example, a substrate such as a glass provided with a data line, a scanning line, a switching element such as a transistor, a charge storage capacitor, and a reflection type pixel electrode such as aluminum, and a transparent conductive film. A liquid crystal layer is sandwiched between a substrate made of glass or the like having a counter electrode and the like. Since the pixel electrode is of a reflective type, a switching element such as a transistor can be provided below the pixel electrode. Even when the resolution is increased, the aperture ratio of the panel does not decrease, and both high resolution and high luminance can be achieved. Can be.

However, when driving a reflective liquid crystal panel having such a configuration, the potential of the data line is temporarily stored in a charge storage capacitor provided in a pixel, and the potential is also applied to the reflective pixel electrode. In this case, since a driving method of applying an image signal voltage to the liquid crystal layer of each pixel is adopted, current leakage from the liquid crystal capacitance and the charge storage capacitance may occur. Therefore, the potential held by the liquid crystal capacitance is reduced, which may cause deterioration of the display state such as reduction in brightness and contrast.

Therefore, in order to maintain a high quality display image,
A signal must be supplied to the data line and the scanning line, and a voltage must be periodically applied to each pixel to maintain the potential, which causes a problem that it is difficult to reduce power consumption.

In order to solve such a problem, for example, as disclosed in Japanese Patent Application Laid-Open No. 8-286170, a 1-bit memory cell is arranged below the reflective pixel electrode of each pixel. LCD panels were proposed.

In a liquid crystal panel having such a memory cell for each pixel, an image signal from a data line is latched by the memory cell, and the signal is applied to a liquid crystal layer of each pixel. Then, since the memory cell holds the previous signal until a new signal is written, once the signal is written, even if the supply of the signal to the data line and the scanning line is stopped, it is not changed. Images written up to this point can be continuously displayed as still images. as a result,
When a still image is displayed, input of an external image signal can be stopped, and power consumption can be reduced.

Further, by digitizing the pixel voltage, there is an advantage that display quality is hardly deteriorated due to crosstalk or the like.

[0009]

However, when a conventional liquid crystal panel having the above-mentioned memory cell for each pixel is used, there is a problem that it is difficult to perform a gradation display. .

In the case where the memory cell is not provided for each pixel, the ON pulse width in the selection period of the signal supplied to the data line is controlled in accordance with the gradation data, so that the liquid crystal of each pixel is controlled. The voltage applied to the layer can be set to a value corresponding to the gradation data, and a desired gradation display can be performed.

However, in the case of a configuration in which a 1-bit memory cell is provided for each pixel, only ON or OFF display can be performed by 1-bit data, so that the applied voltage to the pixel voltage is reduced within one selection period. It cannot be controlled to a value corresponding to the key data.

Therefore, conventionally, for example, when the frame frequency is 60 Hz, the ON time and the OFF time of the voltage of each pixel are adjusted for each frame. That is, one frame is
If 1/60 second (16.6 msec) is further divided into 256 gradations, the image is divided by 256, the data of the entire screen is transferred in each period, and ON and OFF are displayed to display the gradation. .

As a result, it is necessary to rewrite the data of the memory cell of each pixel within 1/256 period of one frame, and it is not possible to take advantage of the above-described advantage in the case where the memory cell is provided for each pixel. There was a problem.

In order to perform the above control,
Since the on-time and the off-time are adjusted every 1/256 period of one frame, the number of switching of the voltage applied to the liquid crystal layer increases as a result, so that the voltage waveform becomes dull and accurate gradation display is performed. Could not do.

Therefore, the present invention solves the above problems,
It is an object of the present invention to provide a reflection type liquid crystal device and a reflection type projector which achieve low power consumption, prevent deterioration of display quality due to crosstalk and the like, and can easily perform gradation display.

[0016]

According to a first aspect of the present invention, there is provided a reflection type liquid crystal device, comprising: a first substrate; A reflection substrate comprising: a second substrate provided; a reflective pixel electrode provided in a matrix on the first substrate; and a liquid crystal sandwiched between the first substrate and the second substrate. Type liquid crystal device, wherein a gradation data holding means is formed for each of the pixels below the layer on which the pixel electrodes are formed on the second substrate, and holds a plurality of bits of gradation data. Pulse width modulation means for modulating an on or off period in one scanning period of each pixel as a pulse width based on a plurality of bits of gradation data held in the data holding means; and Based on the pulse signal modulated by the modulating means And voltage supply means for supplying an on voltage or an OFF voltage to the pixel electrode, characterized in that it comprises a tone data write control means for holding said tone data based on the image signal to each pixel.

According to the reflection type liquid crystal device of the present invention, when an image signal is supplied from the outside, the gradation data writing control means controls the gradation data holding means of each pixel based on the image signal. , A write control signal is output. Thus, the grayscale data holding means of each pixel holds grayscale data of a plurality of bits based on the output write control signal. Therefore, as long as the gradation data is held once unless the value of the gradation data in each pixel is different, the ON voltage or the OFF voltage is supplied to the pixel electrode based on the held gradation data. That is, it is not necessary to rewrite the gradation data in each pixel in each scanning period.

The pulse width modulation means sets the ON or OFF period in one scanning period of each pixel based on the multi-bit gradation data held for each pixel by the gradation data holding means. It is modulated as the magnitude of the pulse width. Further, the voltage supply means supplies an ON voltage or an OFF voltage to the pixel electrode based on the pulse signal modulated by the pulse width modulation means. Therefore, each pixel is turned on only during the period based on the gradation data within one scanning period, and gradation display is performed.

According to a second aspect of the present invention, there is provided a reflection type liquid crystal device, wherein the pulse width modulation means is formed for each of the pixels. A gray scale display circuit, and a display control circuit provided in common for all pixels, wherein the gray scale display circuit includes timing data supplied from the display control circuit and the gray scale data holding unit. The display control circuit includes a match detection circuit that detects a match with the held data and switches the polarity of its own output signal when the match is detected, and an output signal holding circuit that holds an output signal of the match detection circuit. A circuit for outputting, as the timing data, gradation data from a lowest gradation to a highest gradation to each of the gradation display circuits in an ascending order or a descending order within one scanning period.

According to the reflection type liquid crystal device of the present invention, the display control circuit applies the gradation data from the lowest gradation to the highest gradation as one timing data for each gradation display circuit as timing data. When output in ascending or descending order within the period, in the gradation display circuit provided for each pixel, by the coincidence detection circuit, the data held in the gradation data holding means provided for each pixel, It is determined whether or not the gradation data output in the ascending order or the descending order within the one scanning period matches. When a match is detected, the polarity of the output signal of the match detection circuit is switched, and the output signal is held by the output signal holding circuit with this polarity. Therefore, in each pixel, by setting the initial state of the polarity at the start of one scanning period to the polarity opposite to the polarity of the signal held by the output signal holding circuit, the output by the coincidence detection circuit is set. The switching of the polarity of the signal, the switching to the initial state at the start of the next scanning period, or the switching to the initial state, and the switching of the polarity of the output signal by the coincidence detection circuit, The held output signal is output as a pulse signal. Further, since the timing data is data in which the gradation data from the lowest gradation to the highest gradation is output in ascending or descending order within one scanning period, the pulse signal output as described above is turned on. The period or the off period is a pulse signal in which the on period or the off period is continuous with the leading edge or the trailing edge thereof being based on the leading edge or the trailing edge of one scanning period. Therefore, even if one scanning period is shortened and the display is performed at a high frequency, the number of times of switching of the voltage applied to the liquid crystal can be reduced, and the effective voltage can be prevented from lowering due to the rounding of the waveform, and accurate gradation display can be performed. It can be performed.

According to a third aspect of the present invention, there is provided a reflective liquid crystal device according to the first aspect, wherein the pulse width modulation means is formed for each of the pixels. A gray scale display circuit, and a display control circuit provided in common for a plurality of pixels, wherein the gray scale display circuit stores timing data supplied from the display control circuit and the gray scale data holding unit. A coincidence detection circuit that detects coincidence with the held data and switches the polarity of its own output signal when the coincidence is detected, wherein the display control circuit has a minimum of the timing data as the timing data for each of the gradation display circuits. A pulse signal representing gradation data from a gradation to the highest gradation as an ON period or an OFF period in one scanning period, and a trailing edge side of the one scanning period after the ON period or the OFF period. A reference, or as a reference front edge of the front edge of the ON period or OFF period of the one scanning period, characterized in that it comprises a circuit for outputting a pulse signal on period or OFF period are continuous.

According to the third aspect of the present invention, when a pulse signal as timing data is output from the display control circuit to each gradation display circuit, the reflective liquid crystal device is provided for each pixel. In the gradation display circuit, the coincidence detection circuit determines whether or not the data held in the gradation data holding means provided for each pixel matches the timing data. When a coincidence is detected, the polarity of the output signal of the coincidence detection circuit is switched. However, since the timing data is a pulse signal as described above, the coincidence is continuously performed during the ON period of the pulse signal. Will be detected. That is, the output signal whose polarity has been switched by the detection of the coincidence is held at that polarity during the ON period of the pulse signal.

Therefore, in each pixel, the initial state of the polarity at the start of one scanning period is set to the polarity opposite to the polarity of the signal held by the output signal holding circuit, thereby enabling the coincidence detection. The switching of the polarity of the output signal from the switching of the polarity of the output signal by the circuit, the switching to the initial state at the start of the next scanning period, or the switching to the initial state, and the switching of the polarity of the output signal by the coincidence detection circuit, The output signal held by the holding circuit is output as a pulse signal.

The pulse signal as the timing data is obtained by converting gradation data from the lowest gradation to the highest gradation,
A pulse signal represented as an ON period in one scanning period, wherein the trailing edge of the one scanning period is used as a reference of the trailing edge of the ON period, or the leading edge of the one scanning period is used as a reference of the leading edge of the ON period. , A pulse signal having a continuous ON period. Therefore, even if one scanning period is shortened and the display is performed at a high frequency, the number of times of switching of the voltage applied to the liquid crystal can be reduced, and the effective voltage can be prevented from lowering due to the rounding of the waveform, and accurate gradation display can be performed. It can be performed.

According to a fourth aspect of the present invention, there is provided a reflection type liquid crystal device according to any one of the first to third aspects, wherein the gradation data holding means is provided. Represents a static RAM (SRAM) or a dynamic RAM formed using a switching element.
AM (DRAM).

According to the reflection type liquid crystal device of the present invention, the gradation data holding means includes a static RAM (S) formed by using a switching element in each pixel.
RAM) or dynamic RAM (DRAM). Therefore, even when the pixel electrode is downsized in accordance with the increase in the resolution of the liquid crystal device, etc., the gradation data holding means can be reliably formed in the lower layer of the pixel electrode, and the number of bits can be easily increased. Can be.

According to a fifth aspect of the present invention, there is provided a reflection type liquid crystal device according to any one of the first to third aspects, wherein the gradation data holding means is provided. Is a latch circuit formed using a switching element and operating in synchronization with a clock signal.

According to the reflection type liquid crystal device of the present invention, the gradation data holding means is a latch circuit formed using a switching element in each pixel and operating in synchronization with a clock signal. Therefore, it is possible to easily hold the gradation data only by controlling the clock signal.

The reflection type projector according to claim 6 is
A reflection type liquid crystal device according to any one of claims 1 to 5 is provided.

According to a sixth aspect of the present invention, a reflective projector includes the above-described reflective liquid crystal device of the present invention, and is capable of easily performing accurate gradation display. The apparatus can perform high-quality image display.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram for explaining a circuit configuration of the reflection type liquid crystal device in the present embodiment.

Although not shown in FIG. 1, the reflection type liquid crystal device of the present embodiment comprises a plurality of data line pairs ([D11: D11 ', D21: D2) on a first substrate such as glass or Si.
1 ′, to D81: D81 ′] to [D1m: D1
m ', D2m: D2m', ~ D8m: D8m '])
And a plurality of display control lines (S1 to Sn) are arranged substantially orthogonally to each other in a matrix.

The data line pair is D11: D11 ', D2
1: D21 'to D81: Eight pairs of D81' are set as one set. Although not shown in FIG. 1, m sets of these data line pairs are provided along the x direction shown in FIG. The line pairs correspond to the pixel regions in the first to m-th columns.
In FIG. 1, since only a part of the pixel region is shown, the second to m-th data line pairs ([D12: D
12 ′, D22: D22 ′, to D82: D82 ′]
~ [D1m: D1m ', D2m: D2m', ~ D8
m: D8m ']) is not shown.

Although not shown in FIG. 1, n display control lines (S1 to Sn) are provided along the y direction shown in FIG.
It corresponds to each pixel area of the first row to the n-th row. In FIG. 1, the display control lines (S3 to S3) of the third to n-th rows are shown.
Illustration of n) is omitted.

The region where each set of data line pairs intersects with the display control line as described above is composed of n × m pixel regions (P11 to Pnm) from the first row, first column to the nth row, mth column. It has become. That is, in the present embodiment, a block including eight data line pairs and one display control line corresponds to one pixel region. Each pixel region is provided with a reflective pixel electrode 1 made of aluminum or the like. In FIG. 1, the pixel region P11 in the first row and the first column
And only the pixel area P21 in the second row and first column.

On the other hand, a second substrate made of glass or the like is arranged at a position facing the first substrate on which the pixel electrodes 1 are formed as described above. On a side facing the pixel electrode 1, a counter electrode 2 formed of a transparent electrode is provided. The counter electrode 2 is not formed in a matrix on the second substrate, but is formed as a common electrode covering all pixel regions or in a stripe for each pixel row. Then, a light-shielding film such as a black matrix is formed on the second substrate so as to cover a region of the first substrate where the pixel electrode 1 is not formed as necessary.

A liquid crystal layer is sealed between the pixel electrode 1 and the counter electrode 2, and a liquid crystal cell 3 is formed corresponding to each pixel region. The liquid crystal includes a twisted nematic (TN) liquid crystal, a super twisted nematic (STN) liquid crystal, a TN liquid crystal having bistable memory properties, a super homeotropic (SH) liquid crystal, and a guest-host (GH) liquid crystal. For example, various liquid crystals can be used. However, except for the GH type, a polarizer such as a polarizing plate or a polarizing beam splitter is required outside the second substrate.

Next, the pixel electrode 1 in each pixel region is
Below (the side opposite to the side where the pixel electrode 1 is in contact with the liquid crystal cell 3) is a transistor 4 as a switching element.
5 and an 8-bit random access memory (RAM) as a gradation data holding means comprising a memory section 6 and a gradation display circuit 7.

The RAM stores a pair of data lines ([D11: D11 ', D21: D2) in which complementary data is transmitted as a pair.
1 ′, to D81: D81 ′] to [D1m: D1
m ', D2m: D2m', ~ D8m: D8m '])
And an N-channel field-effect transistor (FET) 4 which is a transfer gate for writing complementary data D and / D into the memory unit 6 from the memory device 6 and an N-channel FET 5. Word lines W1, W2 to Wn are connected to the gate terminals of these FETs 4, 5, as shown in FIG.

The memory section 6 of this embodiment has an SRAM type configuration as shown in FIG.
A memory cell 6a composed of a flip-flop composed of two inverters 6b and 6c composed of a T or load resistance type N-channel FET, and a complementary inverter 6d for inverting and outputting the logic of data stored in the memory cell 6a; It is composed of

The operation of the RAM having such a configuration will be described with reference to the first bit RAM 1 provided in the pixel area P11 as an example. In the steady state, the data line D1
1, both data lines D11 'are at a high level potential,
It is assumed that the word line W1 has a low-level potential.

First, when data of a high-level potential is applied to the node Q of the memory cell 6a, the data line D11 is set to the high level by the bit line control circuit 9 as the gradation data writing control means shown in FIG. , And the data line D11 ′ is set to a low-level potential. Next, when the word line W1 is set to a high-level potential by the word line control circuit 8 as the gradation data writing control means shown in FIG. 1, the FETs 4 and 5 are turned on. Thereby, as shown in FIG. 2, the potential of the node Q on the FET4 side of the memory cell 6a becomes a high level, the potential of the node Q 'on the FET5 side becomes a low level, and a stable state is maintained. Writing is performed.

Once data is written, word line W
Even when 1 is set to the low level potential and the FETs 4 and 5 are turned off, the states of the nodes Q and Q ′ of the memory cell 6a do not change and are held.

Therefore, the potential of the output section OUT of the memory section 6 is obtained by changing the potential of the node Q 'of the memory cell 6a to the level of the inverter 6.
d to a high level, and the gradation display circuit 7
, The data of the high-level potential first written to the data line D11 is output.

When writing low-level potential data to the memory cell 6a, the bit line control circuit 9 shown in FIG.
The potential of the data line D11 'is set to a high level potential,
The word line W1 is set to a high level potential by the word line control circuit 8, and the FETs 4 and 5 are turned on. As a result, the potential of the node Q on the FET4 side of the memory cell 6a becomes low level, and the node Q ′ on the FET5 side.
Becomes a high level, a stable state is maintained, and data writing is performed.

Therefore, the potential of the output section OUT of the memory section 6 is calculated by changing the potential of the node Q 'of the memory cell 6a to the level of the inverter 6.
d inverts to a low level, and the gradation display circuit 7
, The data of the low-level potential first written to the data line D11 is output.

As described above, data can be written to each bit of the RAM for each pixel region arranged in the row direction. In this embodiment, first, for each bit of the RAM in the pixel area in the selected column direction, the bit line control circuit 9 sets the data line pair ([D11: D11 ′,
D21: D21 ′ to D81: D81 ′] to [D1
m: D1m ′, D2m: D2m ′ to D8m: D8
m ′]), high-level and low-level complementary data are output to each of them, and then the word line control circuit 8 sets any one of the word lines W1 to Wn to the high level to set a pixel area in any row direction. By selecting all at once, desired data is written to each bit of the RAM.

That is, in the present embodiment, since 8-bit digital data can be stored for each pixel area, the gradation data for each pixel included in the image signal is stored in the RAM of each pixel area. As a result, a maximum of 256 gradations can be expressed.

It should be noted that once data is written in the RAM of each pixel area, the value is held until the next data is written, and the response speed of the liquid crystal to the writing voltage is much slower than the speed at which data is rewritten. The timing of writing data to the RAM can be completely asynchronous with the timing of displaying an image.

The memory cell 6 of the RAM in each pixel area
The configuration a is not limited to the SRAM type shown in FIG. 2A, but may be a DRAM type as shown in FIG. 2B. In the case of the DRAM type, the data potential is written to the storage capacitor 6f, and the written potential is output via the inverter 6e and the inverter 6d. When the DRAM type is used, a refresh operation is required. However, since the area of the memory cell 6a on the first substrate can be reduced,
High integration of AM becomes possible.

Incidentally, in the case of a DRAM, the data line pairs shown in FIG. 1 except for D11 ', D21',..., D81 'and the transfer gate 5, except for the inverter 6 shown in FIG.
e can be eliminated, so that the data holding means of each pixel can be constituted by the FET 4, the capacitor 6f, and the complementary inverter 6d.

Next, the gradation data written to the 8-bit RAM in each pixel area as described above is stored in the liquid crystal cell 3.
The configuration of the gradation display circuit 7 for displaying an image by writing in the image data will be described.

In order to reflect the gray scale data digitized by a plurality of bits as an effective voltage applied to the liquid crystal cell 3, the on period of the signal supplied to the pixel electrode 1 connected to the liquid crystal cell 3 must be set to the gray scale data. It is necessary to perform pulse width modulation control for performing modulation in accordance with the above.

In this embodiment, the gradation display circuit 7 is arranged for each pixel, and the gradation display circuit 7 is configured as shown in FIG. As shown in FIG. 3, the gradation display circuit 7 includes a coincidence detection circuit 7a and an on / off waveform selection circuit 7b.

The coincidence detecting circuit 7a includes, in the input section 11, an input gate circuit in which a negative circuit is connected to the output stage of the exclusive OR circuit, for the number of bits of the RAM in the pixel area.
The input gate circuit of the input unit 11 includes binary signals P0 to P7 output from each stage of an 8-bit binary counter provided in the display control circuit 10 shown in FIG.
An output signal from each bit of the RAM in the pixel area is configured to be input. Therefore, the value represented by the binary signals P0 to P7, that is, the count value (0 to 255) by the 8-bit binary counter
Becomes equal to the value of the data stored in the RAM, the outputs of all the input gate circuits go high,
As a result, the outputs of all the AND gate circuits of the AND circuit unit 12 provided at the previous stage of the input unit 11 become high level. The high-level output of the AND circuit unit 12 is A
Since the signal is input to one input terminal of the latch gate circuit 13 composed of the ND gate circuit, the other input terminal of the latch gate circuit 13 rises to the high level output from the display control circuit 1 shown in FIG. When the latch pulse signal LP is input, a pulse signal that rises to a high level is input to a clock input terminal C of a latch circuit 14 serving as an output signal holding circuit including a D flip-flop circuit. As a result, in the latch circuit 14, the signal input to the input terminal D is output from the output terminal XQ.
Will be output. In the present embodiment, since the low level signal VSS is input to the input terminal D, a signal that falls to low level is output from the output terminal XQ, and a reset signal is input to the reset terminal R. Maintained until input. The reset terminal R is configured to receive a timing signal YD output from the display control circuit 10 shown in FIG. 1 and indicating the start of one scanning period (cycle T) via an inverter circuit 15. The 8-bit binary counter is also reset in synchronization with the timing signal YD, and starts counting. The timing signal YD, the binary signals P0 to P7, and the latch pulse signal LP are transmitted from the display control circuit 10 to all the pixels via the display control lines (S1 to Sn) as shown in FIG. It is configured to be supplied to each of the provided gradation display circuits 7. Note that the AND circuit in FIG. 3 may be omitted by connecting the output of the input gate circuit by wire.

The on / off waveform selection circuit 7b is provided in
It is a switch circuit as shown in FIG. ON waveform ONW and OFF waveform OFFW output from the display control circuit 10
Is selected by a signal from the coincidence detection circuit 7a.

The operation of the gradation display circuit 7 configured as described above will be described with reference to FIGS. First, when a timing signal YD indicating the start of one scanning period is output to the gradation display circuit 7, the output of the latch circuit 14 becomes a high-level potential which is an initial state. Therefore, the ON waveform ONW is selected in the ON / OFF waveform selection circuit 7b,
It is supplied to the pixel electrode 1.

At the same time, the counting operation of the 8-bit binary counter in the display control circuit 10 is started. As a result, binary signals P0 to P7 having values of 0 to 255 are output to the gradation display circuit 7. Further, FIG.
Since the latch pulse signal LP output from the display control circuit 10 is also output in synchronization with the count cycle of the 8-bit binary counter, the data value stored in the RAM provided in each pixel region is When the counter value matches the counter value, the output of the latch circuit 14 is switched to a low-level signal, and is maintained as a low-level signal until the next scanning period starts. Latch circuit 14
Is turned to a low level signal, the off waveform OFFW is selected in the on / off waveform selection circuit 7b and supplied to the pixel electrode 1. As described above, by maintaining the on-potential in accordance with the time width applied to the pixel electrode, an effective voltage corresponding to the gradation level can be applied to the liquid crystal cell of each pixel.

The example shown in FIG. 4 shows an example in which the data of the RAM is "7". In one scanning period, the selection pulse for the on / off waveform selection circuit 7b is shifted for each pixel area. It can be seen that pulse width modulation corresponding to the tone data is performed.

FIG. 5 shows an example of the selection pulse corresponding to each gradation data. As shown in FIG. 5, according to the present embodiment, the ON period of each selection pulse is aligned with the start position of the scanning period, and the ON periods are not dispersed.
It is configured continuously. Therefore, according to the present embodiment, it is possible to reduce the number of transitions of the voltage waveform applied to the liquid crystal. In particular, even when the scanning frequency becomes high and the on-period of each pulse becomes short, the waveform can be reduced. Accurate gradation display can be performed without causing rounding.

Further, in the present embodiment, as shown in FIG.
As shown in (1), a pulse signal that can be alternately switched between +3.0 V and 0 V for each scanning period is supplied.
Then, a pulse signal having the same phase as the pulse signal supplied to the counter electrode 2 as shown in FIG. 6 is used as the OFF waveform OFFW, and a pulse signal supplied to the counter electrode 2 as shown in FIG. Pulse signals of opposite phases were used.

That is, a pulse signal as shown in FIG. 6 is supplied to the counter electrode 2 and an OFF waveform OFF of a pulse signal having the same phase as the pulse signal is supplied to the pixel electrode 1.
When W is supplied, the potential difference between the counter electrode 2 and the pixel electrode 1 disappears, and no voltage is applied to the liquid crystal cell 3. However, as the ON waveform ONW, the counter electrode 2
When a pulse signal having the opposite phase to the pulse signal supplied to the pixel electrode 1 is supplied to the pixel electrode 1, the potential difference between the counter electrode 2 and the pixel electrode 1 is always 3 V, but the direction of the voltage is different every scanning period. , AC drive is performed.

As described above, according to the present embodiment, even when the operating voltage of the circuit formed on the first substrate is 3.0 V and the gate withstand voltage of the circuit is 3.0 V + α, the liquid crystal is driven by AC. Therefore, the liquid crystal can be driven favorably even when the pattern is miniaturized. Further, since the operating voltage (power supply voltage) of each of the above circuits can be reduced, the power consumption can be significantly reduced.

Then, based on the output of the coincidence detecting circuit 7a, the ON / OFF waveform selecting circuit 7b as described above
By selecting the ON waveform ONW and the OFF waveform OFFW, the selection period of the ON waveform ONW in one scanning period can be extended in accordance with the gradation data stored in the RAM, and a good gradation display can be performed. It becomes possible.

Further, by using the gradation display circuit of this embodiment, it is possible to easily correct the transmittance characteristics of the liquid crystal cell.

FIG. 17 shows an example of the transmittance characteristics with respect to the voltage (effective value) applied to the liquid crystal cell in the case of the normally white mode and the case of the normally black mode.

As shown in FIG. 17, in any of the modes, the change in the transmittance with respect to the applied voltage becomes less linear as the gradation level approaches the maximum or minimum gradation level. , The pulse width of the applied voltage must be corrected.

Therefore, in this embodiment, the pulse width of the applied voltage is corrected by using a pulse width correction circuit as described below. In the following description,
For simplicity of description, a case where the RAM is composed of 4 bits will be described. Further, in the following description, the present embodiment is different from this embodiment in that the selection pulse is aligned with the end position of the scanning period.

FIG. 7 shows an example of a pulse width correction circuit, FIG. 8 shows a time chart of each part of the pulse width correction circuit, FIG. 9 shows an equivalent circuit of a liquid crystal cell in which a liquid crystal layer is sandwiched between a pixel electrode and a counter electrode, and FIG. FIG. 2 shows a relationship diagram between the voltage applied to the pixel and the voltage applied to the liquid crystal layer.

The pulse width correction circuit shown in FIG. 7 includes a counter 601, a D-type flip-flop 602, an AND gate 603, a PLA circuit 604, and a PLA circuit 60
P-channel MOSFET 605 for pull-up
And an AND gate 606.

The counter 601 is a 9-stage binary counter, and counts the clock signal f1 input to the clock signal terminal CL. The clock signal f1 is also input to the D-type flip-flop 602, and a circuit including the D-type flip-flop 602 and the AND gate 603 forms a rising differential pulse of the reset signal R synchronized with the clock signal f1. Then, the differentiated pulse is input to the reset signal terminal R of the counter 601, and the counter 601 is reset by the differentiated pulse.

A 7-bit output of Q2 to Q8 of the counter 601 is provided with a PLA using an N-channel MOSFET.
The circuit 604 is connected. The PLA circuit 604 has 10
And decodes numerical values such as [78] to [27]. Here, setting of this numerical value will be described.

[0075] FIG. 10 is obtained by drawing a voltage curve of the charge voltage V _LC of the liquid crystal layer with respect to the applied voltage V _P to the pixel. This voltage curve is determined by the time constant of the pixel,
This time constant is represented by the product of the equivalent capacitance _CLC of the liquid crystal layer and the resistance component R of the pixel when the equivalent circuit of the pixel is considered as shown in FIG. The resistance component R of the pixel is a combined resistance of the combined resistance R ₀ of the output resistances of the row-side and column-side drive circuits and the equivalent resistance R _{NL of the} transistor. The time constant this represented as 80% of the ON voltage _{V ON} of the charging voltage _{V LC} of the liquid crystal layer in the scanning period _{T H} the transistor
Assuming that the voltage rises to the _maximum , the change with time of the charging voltage _VLC applied to the liquid crystal layer is as shown in FIG.

[0076] The numbers on the curve shown in FIG. 10, the charging voltage _{V LC} of the liquid crystal layer, with respect to the applied voltage _{V P} of the pixel, V
When the _LC = 0.8 V _P, the charging voltage _{V LC} evenly 15 split, when the _T H / 80 to 1 pulse further 80 dividing one scanning period _{T H,} divided each voltage Is the number of pulses required to obtain With such a setting, a total of 14 numbers are described on the curve shown in FIG. 10, which corresponds to outputting 16 gradations. The complement of these 14 numbers to 80 is the numerical value to be decoded shown in parentheses in FIGS. FIG. 8 shows P
As a result of decoding by the LA circuit 604, pulse signals output from the ten outlets of the PLA circuit 604 are shown corresponding to the numerical values to be decoded shown in parentheses. As shown in FIG. 8, since these pulse signals are signals of negative polarity, the polarity is inverted by an inverter circuit, a pulse signal as a decoding result obtained by inverting the polarity, and a quartered output of the clock signal f1 are output. AND with the output Q1 of the counter 601
, A corrected clock signal f2 is output.

The corrected clock signal f2 obtained as described above is input to a 4-bit binary counter (not shown), and the corrected clock signal f2 generated by the binary counter is used.
Is counted. Then, a match between the count result and the value obtained by inverting the polarity of the data stored in the RAM is detected, and when the match is detected, the latch circuit is set. For example, when the data stored in the RAM is (0010), as shown in FIG. 8, when the value of the 4-bit binary counter becomes (1101), that is, the thirteenth correction clock signal f2 , The output of the latch circuit is set to the high level. When the data stored in the RAM is (0110), the value of the 4-bit binary counter is (1) as shown in FIG.
001), that is, the ninth correction clock signal f
At the timing of counting 2, the output of the latch circuit is set to the high level. Further, when the data stored in the RAM is (1100), the latch circuit is activated when the value of the 4-bit binary counter becomes (0011), that is, at the timing of counting the third correction clock signal f2. Is set to high level.

The ON waveform ONW is selected during the period when the output of the latch circuit is set to the high level as described above, and the OFF waveform OFFW is selected during the other periods.

With the above configuration, the correction clock signal f2 is output at intervals reflecting the nonlinearity of the change in the transmittance with respect to the applied voltage, and the latch set based on the correction clock signal f2 Since the non-linearity is also reflected in the high level period of the circuit, it is possible to apply an appropriate charging voltage _VLC corresponding to the non-linearity to the liquid crystal layer.

[0080] In this embodiment, RAM is composed of 8 bits, for performing gradation display 256 gradations, for example, in the scanning period _{T H,} the liquid crystal layer which rises to 80% of the applied voltage _{V P} to the pixels Of the charging voltage _VLC to 255,
Using a reference pulse having a period obtained by dividing the scanning period _TH by 255 as one cycle, the number of reference pulses up to each of the 255 divided voltages is obtained according to a curve as shown in FIG. Furthermore, the number of the reference pulse, and decoded using binary counter and PLA circuit shown in FIG. 7, to output the corrected clock signal f2 which is output 254 to one scanning period T _H. Then, the correction clock signal f2 is counted by an 8-bit binary counter, and the binary signals P0 to P7 shown in FIG. 3 are output. In this manner, an appropriate voltage corresponding to the nonlinearity of the change in the transmittance with respect to the applied voltage can be applied to the pixel, and good gradation display can be performed.

As described above, according to this embodiment, since the RAM for holding the gradation data is provided in each pixel, the gradation data in each pixel is rewritten unless the value of the gradation data changes. Therefore, an appropriate voltage can be applied to the liquid crystal only by writing the grayscale data once to the RAM.

The RAM is composed of a plurality of bits, not one bit as in the prior art. Further, the RAM is provided with a gradation display circuit for each pixel, and the gradation data held in the plural-bit RAM is provided. , The ON-pulse selection pulse is pulse-width-modulated, so that gradation display for each scanning period can be performed independently for each pixel. That is, gradation display can be performed by simply performing the same processing as the processing of writing gradation data to the frame memory, and gradation display control can be easily performed.

Further, since the on-period of the selection pulse is aligned with the start position of the scanning period and is continuous without being dispersed within one scanning period,
Even when the display frequency becomes high and the on-period of the selection pulse becomes short, the number of transitions of the voltage waveform applied to the liquid crystal does not increase, and the waveform of the selection pulse does not become rounded. Therefore, good gradation display is possible without lowering the effective voltage applied to the liquid crystal. Note that the off period may be aligned with the start position, and the transition to the on period may be performed at a timing corresponding to the gradation level in one scanning period.

Further, by applying an AC voltage signal to the counter electrode and switching the phase of the AC voltage signal to the same phase as the opposite phase, the ON waveform and the OFF waveform applied to the pixel electrode are switched. With this configuration, the withstand voltage of the gate means for supplying a voltage to the pixel electrode can be reduced as compared with the related art, and fine patterning can be realized.

In this embodiment, a P11 multi-bit RAM and a gradation display circuit 7 are formed on the first substrate below each reflective pixel electrode 1.

Therefore, according to the present embodiment, it is possible to perform easy and good gradation display with low power consumption while making use of the advantage of the reflection type liquid crystal device that high resolution and high luminance can be achieved at the same time.

Although the present embodiment has been described with respect to an example in which the ON periods of the selection pulses are summarized based on the starting position of the scanning period, the present invention is not limited to such a configuration. You may comprise so that it may be set based on the end position of a period.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. Note that the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In this embodiment, as shown in FIG. 11, for each pixel, instead of the RAM as in the first embodiment, latch circuits 30 and 31 each composed of an inverter are used and input to a coincidence detection circuit. The difference from the first embodiment is that timing data that directly defines the ON period of the selection pulse is used instead of using the count data of the binary counter as data.

Latch circuits 30 and 31 provided for each pixel
Is composed of two complementary clocked inverters 30a, 30b (31a, 31b) and one complementary inverter 30c (31c) as shown in FIG. 11 and shown in FIG. Thus, the input data D1 (D2) is latched at the fall of the clock signal CL. In the present embodiment, a 2-bit latch circuit is provided.
Four-gradation expression is possible.

The coincidence detection circuit 32 provided for each pixel is
As shown in FIG. 11, it is composed of an AND gate circuit 32a and an OR gate circuit 32b.
When a bit data match and a match between the latched data and the timing data are detected, a high level signal is output.

In this embodiment, in order to reduce the number of gates, no latch circuit is provided in the coincidence detection circuit 32, and the display control circuit 10 directly supplies the AND gate circuit 32a to the AND gate circuit 32a as shown in FIG. The timing data G1 and G2 as shown are input.

The on / off waveform selection circuit 33 comprises an exclusive circuit and a negation circuit. When the output of the coincidence detection circuit is a high level signal, the on / off waveform selection circuit 33 converts the waveform having the opposite phase to the waveform FR applied to the counter electrode 2 into a pulse width. Output as a modulated signal.

FIG. 12A is a timing chart of the operation in this embodiment. As shown in FIG. 12A, in the present embodiment, when the data latched by the latch circuit 30.31 is (M1, M2 = 1, 1), the timing data G1, G2 are used. Instead, the ON waveform is selected during the entire scanning period. The data latched by the latch circuit 30.31 is (M1,
In the case of (M2 = 1, 0), the timing data G1 is selected as it is, and the ON waveform is selected in a period of 2/3 of one scanning period. Further, the latch circuit 3
The data latched at 0.31 is (M1, M2 = 0,
In the case of 1), the timing data G2 is selected as it is, and the ON waveform is selected in one third of one scanning period.

By using the timing data as described above, in this embodiment, not only can the configuration of the coincidence detection circuit be simplified, but also the latch circuit 14 in the first embodiment can be omitted. The circuit can be simplified. FIGS. 13A and 13B are circuit diagrams in which the circuit of this embodiment is configured by complementary FETs. FIG. 14 shows a pattern diagram of this circuit.

As shown in FIG. 12, according to the present embodiment, the above-described circuit is formed on the first substrate below each reflective pixel electrode. Therefore, even when the size of the liquid crystal device is reduced and the resolution is increased, and the area of the pixel electrode is reduced, it is possible to manufacture a reflective liquid crystal device including the circuit of the present embodiment.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. Note that the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 15, the reflection type liquid crystal device of this embodiment has a second substrate 1304a and a first substrate 13
04b, and a TCP (Tape Carrier Package) in which an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed is provided on the first substrate 1304b.
1320 is connected. The IC chip 1324 assists the control of the reflective liquid crystal device, and may not be added when all the functions are incorporated in the first substrate 1304b. In the present embodiment, the liquid crystal device configured as described above is connected to the liquid crystal light valve 100B (10
0R, 100G) for a reflection type projector.

FIG. 16 is a diagram showing the configuration of the reflection type projector of this embodiment. As shown in FIG. 16, in the reflection type projector of this embodiment, light (generally white light) emitted from the light source lamp 200 is converted into blue light B and red light R / green light by a color separation mirror 201 composed of a cross dichroic mirror. It is split into light G. In addition, each light is transmitted to the mirror 202.
, And is incident on a polarizing beam splitter (PBS) 203, and the PBS 203 causes the S-polarized light to enter the reflective liquid crystal light valves 100B, 100R, and 100G for color light modulation. The incident color light enters the liquid crystal layer from the second substrate 1304a of each light valve, is reflected by each reflective pixel electrode, and is transmitted again through the liquid crystal layer and emitted. When passing through this liquid crystal layer, the polarization axis of the incident S-polarized light is shifted between the P-polarization axis and the S-polarization axis according to the effective voltage applied between each pixel electrode and the counter electrode. The rotation is controlled every time. In PBS203, reflective liquid crystal light valve 1
The S-polarized light components returned from 00B, 100R, and 100G are reflected and transmitted through the P-polarized light components. Therefore, each PBS 20
3, the liquid crystal light valves 100B, 100R, 10
Color light of an amount corresponding to the degree of rotation of the polarization axis of light emitted from 0G is transmitted. This light amount corresponds to a light amount (transmittance) corresponding to the gradation level assigned to each color light.
The color light transmitted through each PBS 203 is transmitted to the color combining prism 20.
The blue light B and the red light R are reflected by the wavelength selective reflection layer of the blue light reflection and the red light reflection formed in the X shape in 4,
The green light G is transmitted, and the color light is synthesized and emitted. This color light is projected on a screen 206 by a projection lens 205.

Also in such a configuration, since gradation display is performed by the data stored in the RAM of each pixel of the liquid crystal light valve, the number of times of switching of the voltage applied to the liquid crystal layer is smaller than that of the conventional liquid crystal light valve. Therefore, accurate gradation display can be performed. Therefore, it is possible to project a higher quality color image than before.

As described above, the reflection type liquid crystal device of the present invention can be used not only for an image display unit such as a notebook type personal computer, a small VTR camera, or a television but also for a color liquid crystal projector. In addition, it is possible to perform good gradation display with high luminance.

In the above embodiment, the ON period in one scanning period is set with reference to the trailing edge of the scanning period. However, even if the ON period and the OFF period are reversed, the display quality may be reduced. It does not matter if there is no problem. Further, the gradation data and the timing data may indicate an ON period or may indicate an OFF period. Further, it goes without saying that not only the case where the first substrate is a semiconductor substrate but also a light transmissive substrate may be used as the reflective liquid crystal device.

[0103]

As described above in detail, according to the present invention, the reflection type pixel electrode defining each pixel is formed below the reflection type pixel electrode.
A multi-bit gradation data holding unit is provided. Based on the multi-bit gradation data held by the gradation data holding unit, the ON period in one scanning period of each pixel is set to a pulse width modulation unit by a pulse width modulation unit. Since the modulation is performed as the size, the power consumption can be reduced by reducing the number of times of writing the grayscale data to each pixel, and the grayscale display for each scanning period can be performed for each pixel. As a result, good image display is possible.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a reflective liquid crystal device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a memory cell in the reflective liquid crystal device of FIG. 1;
M is a circuit diagram in the case where the memory cell is configured by DR.
FIG. 3 is a circuit diagram in the case of being constituted by AM.

FIG. 3 is a circuit diagram showing a configuration of a gradation display circuit in the reflective liquid crystal device of FIG.

FIG. 4 is a timing chart showing operation timing in the reflective liquid crystal device of FIG.

5 is a timing chart showing an application period of an ON waveform corresponding to gradation data in the reflective liquid crystal device of FIG.

6 is a diagram showing a waveform applied to a counter electrode and an ON waveform and an OFF waveform applied to a pixel electrode in the reflective liquid crystal device of FIG.

FIG. 7 is a circuit diagram showing an example of a pulse width correction circuit for explaining a pulse width correction circuit used in the reflection type liquid crystal device of FIG. 1;

8 is a timing chart showing operation timings of the pulse width correction circuit and the latch circuit of FIG.

9 is a circuit diagram showing an equivalent circuit of a pixel of a liquid crystal device used for explaining the pulse width correction circuit in FIG.

FIG. 10 is a diagram illustrating a waveform of a charging voltage applied to a liquid crystal layer with respect to an applied voltage of a liquid crystal device used for explaining the pulse width correction circuit of FIG. 7;

FIG. 11 is a circuit diagram showing a configuration of a gradation display circuit in a reflective liquid crystal device according to a second embodiment of the present invention.

FIG. 12 is a timing chart showing operation timings in the reflection type liquid crystal device according to the second embodiment of the present invention, in which (A) shows an output timing of a coincidence detection circuit and on / off waveform selection when timing data is input; FIG. 3B is a timing chart showing the output timing of the circuit, and FIG. 3B is a timing chart showing the operation of the latch circuit.

FIGS. 13A and 13B are circuit diagrams illustrating a gray scale display circuit using N-channel TFTs in a reflective liquid crystal device according to a second embodiment of the present invention; FIG. 13A is a circuit diagram of a latch circuit;
(B) is a circuit diagram of the coincidence detection circuit.

FIG. 14 is a diagram illustrating an example of a pattern of a gradation display circuit in a reflective liquid crystal device according to a second embodiment of the present invention.

FIG. 15 is a perspective view illustrating a schematic configuration of a reflective liquid crystal device as a liquid crystal light valve according to a third embodiment of the present invention.

FIG. 16 is a schematic diagram showing a schematic configuration of a reflection type projector using the liquid crystal light valve of FIG.

FIG. 17 is a diagram showing a change in transmittance of a liquid crystal display panel with respect to an applied voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Pixel electrode 2 ... Counter substrate 3 ... Liquid crystal cell 4, 5 ... Switching element 6 ... Memory cell 7 ... Gradation display circuit 7a ... Match detection circuit 7b ... On / off waveform selection circuit 8 ... Word line control circuit 9 ... Bit line control Circuit 10 Display control circuit 14 Latch circuit 20 AC power supply 30, 31 Latch circuit 32 Match detection circuit 33 On / off waveform selection circuit

Claims (6)

[Claims] 1. A first substrate, a second substrate having a light-transmitting property and opposed to the first substrate, and a reflective pixel provided in a matrix on the first substrate. A reflective liquid crystal device comprising: an electrode; and a liquid crystal sandwiched between the first substrate and the second substrate, the reflective liquid crystal device comprising: a first substrate; In a lower layer, a gradation data holding unit formed for each of the pixels and holding a plurality of bits of gradation data, and based on the plurality of bits of gradation data held in the data holding unit, A pulse width modulator for modulating an on or off period in one scanning period as a pulse width; and supplying an on voltage or an off voltage to the pixel electrode based on a pulse signal modulated by the pulse width modulator. Voltage supply means, and the pixel Crystal device characterized by comprising a gradation data write control means for holding said tone data based on the image signal, to the. 2. The gradation display circuit according to claim 2, wherein the pulse width modulation unit includes a gradation display circuit formed for each of the pixels, and a display control circuit provided commonly to a plurality of pixels. A match detection circuit for detecting a match between the timing data supplied from the display control circuit and the data held in the gradation data holding means, and switching the polarity of its own output signal when the match is detected; And an output signal holding circuit for holding an output signal of the circuit, wherein the display control circuit, for each of the gradation display circuits,
2. The reflection type liquid crystal device according to claim 1, further comprising a circuit for outputting, as the timing data, gradation data from a lowest gradation to a highest gradation in an ascending order or a descending order within one scanning period. 3. The gradation display circuit, comprising: a gradation display circuit formed for each of the pixels; and a display control circuit provided commonly to all the pixels. A match detection circuit that detects a match between the timing data supplied from the display control circuit and the data held in the gradation data holding means, and switches the polarity of its own output signal when the match is detected, A control circuit is provided for each of the gradation display circuits.
A pulse signal representing, as the timing data, gradation data from the lowest gradation to the highest gradation as an ON period or an OFF period in one scanning period, and a trailing edge side of the one scanning period is an ON period or an OFF period. A circuit that outputs a pulse signal having a continuous on-period or off-period as a reference of a trailing edge of a period or a leading edge of the one scanning period as a reference of a leading edge of an on-period or an off-period. The reflective liquid crystal device according to claim 1. 4. A static RAM (SRA) formed by using a switching element,
4. The reflection type liquid crystal device according to claim 1, wherein the reflection type liquid crystal device is M) or a dynamic RAM (DRAM). 5. The device according to claim 1, wherein the gradation data holding means is a latch circuit formed using a switching element and operating in synchronization with a clock signal. The reflective liquid crystal device according to the above. 6. A reflection type projector comprising the reflection type liquid crystal device according to any one of claims 1 to 5.