JP2002169137A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high definition and lower power consumption in a liquid crystal display, which is provided with a structure for switching, between driving by digital memory and driving by an ordinary TFT system. SOLUTION: High definition is realized by connecting several adjacent pixel electrode 10-1, 10-2, 10-3 with digital memory(DM) 18, and constituting them so as to supply a binarized video signal, held in a single digital memory 18 to the three pixel electrodes 10-1-3, at display of a static image, and thereby reducing area for arranging the digital memory 18. In this case, since the number of the switching elements constituting the digital memory 18 is reduced, the load capacity is also reduced, and moreover, since peripheral drive circuits can be stopped or driven at a low frequency, lower power consumption can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition, low-power-consumption liquid crystal display device used for mobile phones, electronic books, and the like.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been used as displays for small information terminals such as mobile phones and electronic books, taking advantage of the advantages of light weight, thinness, and low power consumption. Since these small information terminals are generally driven by a battery, reducing power consumption is an important issue. For example, a mobile phone is required to be able to display with low power consumption during a standby time, and a technique for realizing this is disclosed in, for example, Japanese Patent Application Laid-Open No. 58-23091. The image display device disclosed herein includes a digital memory in a pixel, and operates only an AC driving circuit for AC driving the liquid crystal during standby (at the time of displaying a still image).
By stopping other peripheral drive circuits, a significant reduction in power consumption is achieved.

[0003]

By the way, recently, color halftone display and moving image display such as the Internet and TV telephones have been started on portable telephones, and higher definition and lower power consumption are required. . To cope with this, there has been proposed a liquid crystal display device having a structure for switching between driving by a digital memory and driving by a normal TFT system by using a switch element built in each pixel. However, in the liquid crystal display device having such a structure, an area for arranging a digital memory in each pixel is required. Therefore, when the pixel size is reduced, it is difficult to arrange the digital memory, and high definition is achieved. It was difficult. Further, when the definition is increased, the load capacity increases, so that it is difficult to further reduce the power consumption.

An object of the present invention is to realize higher definition and lower power consumption in a liquid crystal display device having a structure for switching between driving by a digital memory and driving by a normal TFT system.

[0005]

In order to achieve the above object, the present invention is directed to a plurality of adjacent scanning lines and a plurality of signal lines, which are arranged crossing each other, and a plurality of scanning lines and a plurality of signal lines each having an intersection. On / off control is performed by the arranged pixel electrode and a scanning signal supplied to the scanning line, and when the pixel electrode is turned on, the signal line is connected to the pixel electrode to supply a video signal supplied to the signal line to the pixel electrode. A first electrode substrate including a first switch element to be written, a second electrode substrate including a counter electrode disposed to face the pixel electrode at a predetermined interval, the first electrode substrate and the second electrode substrate A liquid crystal layer interposed between the liquid crystal layer, a signal line driving circuit for supplying a video signal to the plurality of adjacent signal lines, and a scanning line driving circuit for sequentially supplying a scanning signal to the scanning line. In the display device, the first A polar substrate is electrically connected to a plurality of adjacent pixel electrodes, and a digital memory capable of holding a video signal supplied to the signal line, and a plurality of adjacent pixel electrodes and an output of the digital memory. And a digital memory switch circuit for controlling electrical conduction between them.

According to a second aspect of the present invention, in the first aspect, the digital memory switch circuit is arranged for each of a plurality of adjacent pixel electrodes.

According to a third aspect of the present invention, in the first or second aspect, the plurality of adjacent pixel electrodes connected to the output of the digital memory have three pixels corresponding to red, green, and blue constituting one pixel. It is an electrode.

According to a fourth aspect of the present invention, in the first or second aspect, the plurality of adjacent pixel electrodes connected to the output of the digital memory are at least two pixel electrodes of the same color.

In a preferred embodiment, the pixel electrode is a light reflection type pixel electrode formed of a metal thin film.

In a preferred embodiment, the digital memory switch circuit includes at least a second switch element connected to a non-inverted output terminal of the digital memory and a third switch element connected to an inverted output terminal of the digital memory. It is characterized by comprising.

In a preferred embodiment, the second switch element and the third switch element are connected to independent control signal lines.

In a preferred embodiment, the digital memory comprises at least two inverter circuits and a fourth switch element.

In a preferred embodiment, the respective elements constituting the digital memory are dispersedly arranged in respective regions of a plurality of adjacent pixel electrodes.

In a preferred embodiment, the fourth switch element is connected to the scanning line.

In a preferred embodiment, the first switch element and the fourth switch element are constituted by complementary MOS transistors.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device according to the present invention will be referred to as an active matrix type liquid crystal display device (hereinafter, referred to as an active matrix type liquid crystal display device).
An embodiment applied to an AM-LCD will be described.

[First Embodiment] FIG. 3 is a circuit diagram of an AM-LCD according to the first embodiment, and FIG. 4 is a schematic sectional view of FIG.

In the first embodiment, the combination of a plurality of adjacent pixel electrodes connected to the output of one digital memory is controlled by the same scanning line, and the red and green pixels which are adjacent to each other in the horizontal direction and constitute one pixel. , Blue will be described.

The AM-LCD 100 has a display pixel section 11.
0, a scanning line driving circuit 120 and a signal line driving circuit 130. Here, on the array substrate 101 (FIG. 4), the scanning line driving circuit 120 and the signal line driving circuit 130 are connected to the signal line 11, the scanning line 12, and the pixel electrode 1 respectively.
Although an example in which the scanning line driving circuit 120 and the signal line driving circuit 130 are formed integrally with the third driving circuit 3 and the like is shown, the scanning line driving circuit 120 and the signal line driving circuit 130 may be arranged on an external driving substrate (not shown).

In the display pixel section 110, a plurality of signal lines 11 and a plurality of scanning lines 12 intersecting the signal lines 11 are arranged in a matrix on an array substrate 101 via an insulating film (not shown). A display pixel 10 is arranged at each intersection.

The display pixel 10 includes a pixel electrode 13, a first switch element 14, a counter electrode 15, a liquid crystal layer 16, a digital memory switch circuit (hereinafter referred to as a DM switch circuit) 17,
It comprises a digital memory (hereinafter, DM) 18 and an auxiliary capacitor 19. FIG. 3 shows a state in which one pixel is constituted by three (red, green, and blue) display pixels 10 (sub-pixels) arranged in the horizontal direction. In FIG. 3, for simplicity of description, the DM 18 is connected to the central display pixel 10 among the three display pixels 10 arranged in the horizontal direction. As will be described later, the pixels are dispersedly arranged in three display pixels 10.

In the display pixel 10, the source of the first switch element 14 is the signal line 11, and the gate of the first switch element 14 is the scanning line 12.
The drains are connected to the pixel electrodes 13, respectively. The pixel electrode 13 is connected to a DM 18 via a DM switch circuit 17, and the DM switch circuit 17
Is connected to the control signal line 20 and the source is the pixel electrode 13.
And the drains are connected to the DM 18 respectively. D
The configurations of the M switch circuit 17 and DM 18 will be described later.

Although two control signal lines 20 are arranged as control signal lines 20a and 20b as described later, FIG. 3 shows one control signal line 20 for ease of explanation. I have.

The pixel electrode 13 is formed on an array substrate 101, and a counter electrode 15 facing the pixel electrode 13 is formed on a counter substrate 102. The counter electrode 15 has a control IC disposed on an external drive substrate (not shown).
, A predetermined counter potential is provided. The pixel electrode 1
A storage capacitor 19 is connected in parallel to 3 in order to maintain a potential relationship with the counter electrode 15. This auxiliary capacity 19
Form a capacitance Cs between the pixel electrode 13 and the auxiliary capacitance line 29. The auxiliary capacitance line 29 is commonly connected to the auxiliary capacitances 19 of all the display pixels 10, and is supplied with a predetermined potential from a controller IC (not shown).

The scanning line driving circuit 120 is composed of a shift register 121 and a buffer circuit (not shown), for one horizontal scanning period based on a control signal (vertical clock / start signal) supplied from the control IC. An on-level scanning signal is sequentially output to the scanning line 12 every time.

In the scanning line drive circuit 120, when displaying a halftone or a moving image (hereinafter, when displaying a halftone / moving image), a scanning signal is applied to the scanning line 12 from the top in the same manner as in a normal active matrix type liquid crystal display device. Is output. When displaying a still image, the scanning line 12 is turned off. Further, the scanning line drive circuit 120 supplies a memory control signal of a predetermined level to the control signal line 20 at the time of displaying a halftone / moving image and at the time of displaying a still image, respectively, as described later.

The signal line driving circuit 130 includes a shift register 131, an ASW (analog switch) 132, and the like. A control signal (horizontal clock / start signal) from a control IC (not shown) and a video signal through a video bus 133 are supplied to the signal line driving circuit 130. Supplied. The signal line drive circuit 130 supplies an open / close signal of the ASW 132 from the shift register 131 based on the horizontal clock / start signal, thereby sampling the video signal supplied from the video bus 133 onto the signal line 11 at a predetermined timing. I do.

The scanning line drive circuit 120 and the signal line drive circuit 130 are supplied with a drive power supply voltage from a control IC (not shown).

Further, the array substrate 101 and the counter substrate 10
2, a liquid crystal layer 16 is sandwiched therebetween, and the periphery thereof is sealed with a sealant 103.

Here, the AM-L configured as described above is used.
The basic operation of the CD 100 will be briefly described.

A scanning signal is output from the scanning line driving circuit 120, and each scanning line 12 is sequentially scanned from the top every one horizontal scanning period. When a video signal is sampled on the signal line 11 in synchronization with this, scanning is performed. All the first switch elements 14 connected to the scanning line 12 are turned on only for one horizontal scanning period, and the video signal sampled on the signal line 11 is written to the pixel electrode 13 through the first switch element 14. . This video signal is transmitted between the pixel electrode 13 and the counter electrode 1.
5 (and the auxiliary capacitor 19) is charged as a signal voltage, and the liquid crystal layer 16 responds according to the magnitude of the signal voltage to control the amount of transmitted light from the display pixels. By performing such an operation for all the scanning lines 12 within one frame period, an image of one screen is completed.

Next, the circuit configuration of the display pixel 10 according to the first embodiment will be described in more detail with reference to FIGS.

FIG. 1 is a circuit configuration diagram of the display pixel 10, and FIG.
Is a schematic plan view thereof. Here, 3
In order to distinguish one display pixel 10, its constituent elements are described as, for example, 14-1, 14-2, and 14-3.
However, in the text, it is described as 14, for example, as necessary. In addition, a pixel common to each display pixel is denoted by, for example, 15.

Each DM switch circuit 17 is composed of a second switch element 21 and a third switch element 22.
18 are inserted between the non-inverting output terminal 27 and the inverting output terminal 28 and each pixel electrode 13. In the DM switch circuit 17, the gate of the second switch element 21 is connected to the control signal line 20a, and the gate of the third switch element 22 is connected to the control signal line 20b. The control signal lines 20a and 20b are connected to the scanning line driving circuit 1
The two switch elements are independently controlled by being supplied with an on or off level potential according to the display mode. The DM switch circuit 17 and the first switch element 14 are both constituted by MOS transistors.

The DM 18 has two inverter circuits 24,
25 and a fourth switch element 26. Among them, the fourth switch element 26 is a switch element having a channel opposite to that of the first switch element 14, and is configured by a MOS transistor complementary to the first switch element 14. These elements constituting the DM 18 are dispersedly arranged in three display pixels. However, the arrangement of each element is not limited to the example of FIG. 1 and can be replaced with any configuration that can function equally.

The gate of the fourth switch element 26 is connected to the first
Are connected to the same scanning line 12 as the gate of the switch element 14. Therefore, when an on-level scanning signal is applied during halftone / moving image display, the first switch element 14 is turned on and the fourth switch element 26 is turned off. At this time, display is performed by writing the video signal sampled on the signal line 11 to the pixel electrode 13, and during this time, the DM1
Function 8 stops. Further, when the scanning signal is turned off at the time of displaying a still image, the first switch element 14 is turned off,
The fourth switch element 26 turns on. In this case, DM
Display is performed by writing the video signal written in 18 to the pixel electrode 13, and during this time, the operation of the signal line drive circuit 130 that samples the video signal on the signal line 11 stops.

Next, the AM-LC configured as described above
The operation in D100 when displaying a halftone / moving image (normal display) and displaying a still image will be described.

First, at the time of displaying a halftone / moving image, the control signal lines 20a and 20b are both turned off, and the DM switch circuit 17 is turned off. During this time, the scanning line driving circuit 12
A clock signal, a start signal, and a video signal are supplied to the 0 and the signal line driving circuit 130, respectively, to perform full-color high-quality halftone / moving image display. In this case, similarly to a general AM-LCD having no DM, a video signal sampled on the signal line 11 is supplied to the pixel electrode 13.
, Full-color display is performed.

On the other hand, when switching from the normal display to the still image display, the control signal line 20a is turned on and the control signal line 20b is turned off in the last frame (still image writing frame) which shifts from the normal display to the still image display. Level. While the first switch element 14 is turned on by the on-level scanning signal, the signal line driving circuit 13 is turned on.
The video signal binarized from 0 to the signal line 11 is sampled and written to the DM 18 through the first switch element 14 and the second switch element 21 of the DM switch circuit 17. Here, the binarized video signal is a video signal for a multi-color image displayed when a still image is displayed.

After the binarized video signal is written to the DM 18, the scanning signal goes to the off level, and when the first switch element 14 is turned off, the fourth switching element 26
Is turned on, and the written video signal is held in a loop around the two inverter circuits 24 and 25. Further, in this state, the control signal line 20b is turned on, and the control signal line 2
When 0a is set to the off level, the binarized video signal held in the DM 18 is output to the third switch of each DM switch circuit 17.
, And is written to the pixel electrodes 13 of the three display pixels 10-1 to 10-3, whereby binary multi-color display is performed.

As in the first embodiment, the combination of a plurality of adjacent pixel electrodes 13 connected to the output of the DM 18 is divided into three pixels of red, green, and blue which are adjacent to each other in the horizontal direction and constitute one pixel.
In the case where one pixel electrode is used, the sampling frequency of the video signal is 1/3 of the halftone / moving image display. Therefore,
In order to perform normal display, it is necessary to convert a binarized video signal supplied from outside to the DM 18 into a video signal for monochrome display in advance.

In the still image display period, DM1
The video signal written in 8 can be held in this state for a short time, but if it is held for a long time, the liquid crystal layer 16 is deteriorated by a DC component, so that it is necessary to drive it by AC. For this reason, the control signal lines 20a and 2
0b is alternately turned on, the two switch elements 21 and 22 of the DM switch circuit 17 are alternately turned on, and the AC drive is performed by inverting the potential of the corresponding electrode 15 accordingly.

As described above, the two switch elements 21 and
2 are alternately turned on, the power supply / ground potential is alternately output as the potential of the pixel electrode 13, and the potential of the counter electrode 15 is shifted between the power supply / ground potential in synchronism with this, whereby the potential of the counter electrode 15 is changed. In the display pixels 10 having the same polarity, no voltage is applied to the liquid crystal layer 16, and in the display pixels 10 having the opposite polarity, a voltage is applied to the liquid crystal layer 16, so that binary display (monochrome display) can be performed. At this time, the operation of the display pixel unit 110 is performed by the low-frequency storage capacitor line 29 and the counter electrode 15.
In addition, since the signal line driving circuit 130 is also driven at a low sampling frequency, the image resolution is slightly lower during standby (when displaying a still image) than when displaying a halftone / moving image. In addition, monochrome display can be performed with lower power consumption.

Further, when switching from the still image display to the normal display, the two control signal lines 20a and 20b are both turned off again after the last frame (still image final frame), and the scanning line drive circuit 120 and the A normal clock signal, a start signal, and a video signal are supplied to the signal line driving circuit 130, respectively.

According to the first embodiment, since three pixel electrodes 13 adjacent in the horizontal direction are driven by one DM 18, the arrangement area of the DM per pixel can be reduced. Therefore, even when the pixel size is reduced, the DM can be accommodated in the pixel, and a high definition screen can be achieved. Also, since the number of switch elements constituting the DM can be reduced as compared with the conventional configuration in which the DM is arranged for each pixel, the load capacity can be reduced, and the driving of the peripheral driving circuit is stopped or changed. Since driving can be performed at an extremely low frequency, power consumption can be further reduced.

[Second Embodiment] Next, as a second embodiment,
An example will be described in which a combination connected to the output of one DM is two pixel electrodes of the same color that are adjacent in the vertical direction. However, description corresponding to FIGS. 3 and 4 of the first embodiment is omitted, and only the configuration and operation of the display pixel will be described.

FIG. 5 shows a display pixel 10 according to the second embodiment.
FIG. 6 is a schematic plan view thereof, and the same reference numerals are given to the same parts as those in FIG. Here, in order to distinguish the two display pixels 10 arranged in the vertical direction, the constituent elements are described as, for example, 14-1 and 14-2. However, in the text, it is described as 14, for example, as necessary. In addition, a pixel common to each display pixel is denoted by, for example, 15.

The DM switch circuit 31 is composed of a second switch element 34 and a third switch element 35.
33 are inserted between the non-inverting output terminal 27 and the inverting output terminal 28 and each pixel electrode 13. In the DM switch circuit 31, the gate of the second switch element 34 is connected to the control signal line 20a, and the gate of the third switch element 35 is connected to the control signal line 20b. The control signal lines 20a and 20b are connected to a scanning line driving circuit (not shown), and the two switch elements are independently controlled by supplying an on or off level potential according to a display mode. This DM switch circuit 31
And the first switch element 14 are both formed by MOS transistors.

The DM 33 has two inverter circuits 36,
37 and a fourth switch element 38. The fourth switch element 38 is a switch element having a channel opposite to that of the first switch element 14, and the first switch element 1
4 and a complementary MOS transistor. However, the arrangement of each element is not limited to the example of FIG. 5 and can be replaced with any configuration that can function equally.

Next, the AM-LC configured as described above
In D, an operation when displaying a halftone / moving image (normal display) and displaying a still image will be described.

First, at the time of displaying a halftone / moving image, the control signal lines 20a and 20b are both turned off, and the DM switch circuit 31 is turned off. During this time, a clock signal, a start signal, and a video signal are supplied to the scanning line driving circuit 120 and the signal line driving circuit 130 shown in FIG. 3, respectively, to perform full-color high-quality halftone / moving image display. In this case, a general AM-LCD without DM
Similarly to the above, full-color display is performed by writing the video signal sampled on the signal line 11 to the pixel electrode 13.

On the other hand, when switching from the normal display to the still image display, the control signal line 20a is turned on and the control signal line 20b is turned off in the last frame (still image writing frame) which shifts from the normal display to the still image display. Level. While the first switch element 14 is turned on by the on-level scanning signal, the signal line driving circuit 13 is turned on.
The video signal binarized from 0 to the signal line 11 is sampled and written to the DM 33 through the first switch element 14 and the second switch element 34 of the DM switch circuit 31.

After the binarized video signal is written to DM 33, the scanning signal goes off and the first switch element 14 is turned off.
Is turned on, and the written video signal is held in a loop around the two inverter circuits 36 and 37. Further, in this state, the control signal line 20b is turned on, and the control signal line 2
When 0a is set to the off level, the binarized video signal held in the DM 33 is output to the third
, And written to the pixel electrodes 13 of the upper and lower two display pixels 10-1 and 10-2, thereby performing a binary multi-color display.

As in the second embodiment, the combination connected to the output of the DM 33 is the same as that of the same color adjacent to each other in the vertical direction.
In the case of one pixel electrode 13, the sampling frequency of the video signal is の of the halftone / moving image display. Therefore, in order to perform normal display, it is necessary to perform frequency conversion and data rearrangement of the binarized video signal supplied from the outside to the DM 33.

Further, during a still image display period, the control signal lines 20a and 20b are alternately turned on at a constant cycle,
Two switch elements 34 and 35 of the DM switch circuit 31
Are turned on alternately, and the corresponding electrode 1
By performing the AC driving for inverting the potential of No. 5, deterioration of the liquid crystal layer 16 can be prevented. Embodiment 2
Also, in standby mode (during display of a still image), multi-color display can be performed with lower power consumption than in the past, although the resolution of the image is slightly lower than that during halftone / moving image display.

Further, when switching from the still image display to the normal display, the two control signal lines 20a and 20b are turned off again after the last frame (still image final frame), and the scanning line drive circuit 120 and the A normal clock signal, a start signal, and a video signal are supplied to the signal line driving circuit 130, respectively.

According to the second embodiment, since two pixel electrodes 13 adjacent in the vertical direction are driven by one DM 33, the arrangement area of the DM per pixel can be reduced. In addition, it is possible to increase the definition of the screen. Further, since the number of switch elements constituting the DM can be reduced, the load capacity can be reduced, and the driving of the peripheral driving circuit can be stopped or driven at a lower frequency, so that further lower power consumption can be achieved. Can be achieved.

Next, the AM-LC of the first and second embodiments will be described.
The method of manufacturing D will be described with reference to FIG.

[0059] Figure 7 is a schematic cross-sectional views showing a manufacturing process of the AM-LCD, the right area is a pixel portion of the solid line (the display pixel portion 110), the left area is a driver circuit portion (the scanning line driving circuit 120 Etc.). Hereinafter, FIG.
Description will be made in the order of (f).

(A) An amorphous silicon (a-Si) thin film 51 having a thickness of 50 nm is deposited on a transparent insulating substrate 50 made of glass or the like by a plasma CVD method. The material is polycrystallized by annealing. Here, the laser beam 5 from the XeCl excimer laser device was used.
2 is scanned in the direction of A in the figure, and the region irradiated with the laser light 52 is crystallized to become a polycrystalline silicon film 53. At this time, by performing laser irradiation more than once while increasing the laser irradiation energy stepwise, hydrogen in the amorphous silicon film can be effectively removed, and ablation during crystallization can be prevented. The irradiation energy is 2
00 to 500 mJ / cm2.

(B) The polycrystalline silicon film 53 is patterned by photolithography to form an active layer 54 of the thin film transistor.

(C) After forming a gate insulating film 55 of a silicon oxide film by a plasma CVD method, a molybdenum-tungsten alloy film is formed by a sputtering method and patterned to form a gate electrode 56. Scanning lines are also formed at the same time as the patterning. Gate insulating film 55
Alternatively, a silicon nitride film or a silicon oxide film formed by a normal pressure CVD method can be used.

After forming the gate electrode 56, the gate electrode 5
Impurities are implanted by ion doping using the mask 6 as a mask to form source / drain regions 54a of the thin film transistor. As impurities, phosphorus can be used for an N-ch transistor and boron can be used for a P-ch transistor. The LDD (Light) is used for the transistor in the pixel portion in order to suppress the leak current at the time of OFF.
It is effective to use a (Tly DopedDrain) structure. In this case, after the impurity is implanted into the source / drain electrodes 54a, the gate electrode 56 is re-patterned to make it smaller by a certain amount, and then the low concentration impurity is implanted again.

(D) Plasma CVD on the gate electrode 56
A first interlayer insulating film 57 of a silicon oxide film is formed by a CVD method or a normal pressure CVD method.

(E) After forming contact holes in the first interlayer insulating film 57 and the gate insulating film 55, A is formed by sputtering.
Source / drain electrodes 59 and 60 are formed by forming and patterning an l film. At this time, signal lines are formed at the same time.

(F) A low dielectric constant insulating film (second interlayer insulating film) 61 is formed on the Al film. Low dielectric constant insulating film 61
For example, a low-k insulating film such as a silicon nitride film, a silicon oxide film, or an organic insulating film formed by a plasma CVD method can be used. Then, a contact hole is formed in the low dielectric constant insulating film 61, an Al thin film 62 is formed, and a pixel electrode is formed by patterning.

By the above process, the transparent insulating substrate 50
A pixel portion and a driver circuit portion can be formed over the same. Thereafter, the transparent insulating substrate 50 and the opposing substrate on which the opposing electrode (not shown) is formed are opposed to each other, the periphery thereof is sealed with a sealing material made of epoxy resin, and a liquid crystal composition is injected therein.
The liquid crystal display device can be completed by sealing (see FIG. 4).

Note that a p-Si (polysilicon) TFT
Since the mobility of electrons is about two orders of magnitude higher than that of an a-Si TFT, the TFT size can be reduced,
The peripheral driving circuit can also be integrally formed on the substrate at the same time. It is desirable that the peripheral circuit has a CMOS structure in order to achieve high speed and low power consumption. For this reason, the impurity doping step is performed in two steps of P-type and N-type impurity doping steps using a resist mask.

Also, as in this embodiment, the pixel electrode 1
When the pixel electrode 3 is a light-reflection type pixel electrode made of a metal thin film, a backlight is not required, so that driving with lower power consumption can be performed as compared with a transmission type configuration using a backlight. Become. Incidentally, when a still image was displayed at a frame frequency of 60 Hz on a liquid crystal panel having a diagonal of 5 cm and 250,000 pixels, the power consumption could be reduced to 5 mW.

[0070]

As described above, according to the liquid crystal display device according to the present invention, the arrangement area of the digital memory per pixel can be reduced. And the screen can be made higher definition. In addition, since the number of switch elements constituting the digital memory can be reduced, the load capacity can be reduced, and the driving of the peripheral driving circuit can be stopped or driven at a lower frequency, so that further lower power consumption can be achieved. Electricity can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a display pixel according to a first embodiment.

FIG. 2 is a schematic plan view of FIG.

FIG. 3 is a circuit configuration diagram of the AM-LCD according to the first embodiment.

FIG. 4 is a schematic sectional view of FIG. 3;

FIG. 5 is a circuit configuration diagram of a display pixel according to a second embodiment.

FIG. 6 is a schematic plan view of FIG.

FIG. 7 is a schematic sectional view showing a manufacturing process of the AM-LCD.

[Explanation of symbols]

10: display pixel, 11: signal line, 12: scanning line, 13:
Pixel electrode, 14 first switch element, 15 counter electrode, 16 liquid crystal layer, 17 DM switch circuit, 18 D
M (digital memory), 19 ... auxiliary capacity, 20 (20
a, 20b) ... control signal line, 21, 34 ... second switch element, 22, 35 ... third switch element, 24, 2
5, 36, 37: inverter circuit, 26, 38: fourth switch element, 101: array substrate, 102: counter substrate, 110: display pixel section, 120: scanning line drive circuit, 1
30 ... Signal line drive circuit

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court II (Reference) G09G 3/36 G09G 3/36 (72) Inventor Hiroyuki Kimura 1-9-2 Hara-cho, Fukaya-shi, Saitama Inside Toshiba Fukaya Plant (72) Inventor Takashi Maeda 1-9-2 Hara-cho, Fukaya-shi, Saitama Prefecture Inside Toshiba Fukaya Plant (72) Inventor Takanori Tsunashima 1-9-1-2 Harara-cho, Fukaya-shi, Saitama Prefecture F-term in the Toshiba Fukaya Plant (reference)

Claims (4)

[Claims] 1. A plurality of scanning lines and a plurality of signal lines arranged to cross each other, a pixel electrode arranged at each intersection of these lines, and on / off control by a scanning signal supplied to the scanning lines. A first electrode substrate including a first switch element for writing the video signal supplied to the signal line to the pixel electrode by conducting between the signal line and the pixel electrode when the pixel electrode is turned on; A second electrode substrate including a counter electrode disposed to face at a predetermined interval, a liquid crystal layer sandwiched between the first electrode substrate and the second electrode substrate,
In a liquid crystal display device comprising: a signal line driving circuit that supplies a video signal to the plurality of signal lines; and a scanning line driving circuit that sequentially supplies a scanning signal to the scanning line, wherein the first electrode substrate includes: A digital memory electrically connected to the adjacent pixel electrode and capable of holding a video signal supplied to the signal line; and electrical continuity between a plurality of adjacent pixel electrodes and an output of the digital memory. A liquid crystal display device, comprising: a digital memory switch circuit for controlling the operation of the liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein the digital memory switch circuit is arranged for each of the plurality of adjacent pixel electrodes. 3. The pixel electrode according to claim 1, wherein the plurality of adjacent pixel electrodes connected to the output of the digital memory are three pixel electrodes corresponding to red, green and blue constituting one pixel. 3. The liquid crystal display device according to 2. 4. The liquid crystal display device according to claim 1, wherein a plurality of adjacent pixel electrodes connected to an output of the digital memory are at least two pixel electrodes of the same color.