JP2002341381A - Thin film transistor array and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the high-speed response of a liquid crystal display device using a polycrystalline silicon-thin film transistor array. SOLUTION: Wirings made of the same material as that of a data line of thin film transistors for displaying a picture 103 are connected electrically to an auxiliary capacitance formation electrode wiring 106 via contact holes formed on the auxiliary capacitance formation electrode wiring 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix array for an image display device in which polycrystalline silicon thin film transistors (hereinafter abbreviated as TFTs) are integrated in a matrix.

[0002]

2. Description of the Related Art A conventional thin film transistor array will be described with reference to FIG.

FIG. 5A is an equivalent circuit diagram of each pixel of an active matrix array for a liquid crystal display device. As shown in FIG. 5A, the liquid crystal 101 is driven by a thin film transistor 103 provided for each pixel. A scanning signal is input to the thin film transistor from a gate electrode wiring 104 and a data signal is input from a source electrode wiring 105 to charge the liquid crystal and the auxiliary capacitor 102. The auxiliary capacitance is formed in parallel with the liquid crystal capacitance to hold the voltage charged in the pixel while the thin film transistor is off, and the auxiliary capacitance of each pixel is connected to the same potential (Vdd in FIG. 5A). Is done.

FIG. 5B shows a sectional structure of each pixel when a polycrystalline silicon thin film transistor is used as a pixel electrode driving element. The auxiliary capacitance 102 is a capacitance formed by the interlayer insulating film 16 between the electrode wiring 106 connected to the common potential (Vdd in FIG. 5A) and the drain electrode 105 of the thin film transistor.
The capacitance formed by the gate insulating film 15 is connected in parallel with the polycrystalline silicon 13 connected to the drain electrode.

The polycrystalline silicon thin film 13 under the storage capacitor has a high resistance without being implanted because impurities are implanted using the gate electrode as a mask when forming the source and drain regions of the thin film transistor.

As described above, when the polycrystalline silicon thin film under the auxiliary capacitance has a high resistance, in order to form a sufficient capacitance, the potential of the auxiliary capacitance wiring is changed to an inversion state of the polycrystalline silicon thin film under the auxiliary capacitance wiring to lower the resistance and reduce the auxiliary resistance. This is supported by setting (usually, Vdd or Vss) such that the MOS capacitance of the capacitance section is maximized.

FIG. 6 shows a driving waveform of a liquid crystal display device using the p-channel thin film transistor array shown in FIG.
FIG. 6B shows a change in pixel potential accompanying the change.

As shown in FIG. 6A, the gate potential is +9 V (Vd
d: Vgoff) to -6V (Vgon), source potential from -2.5V (Vs +)
It is changed to 7.5V (Vs-). The pixel potential is charged during the period when the gate potential is -6 V (Vgon), and is held by the auxiliary capacitance during the OFF period until the gate potential next reaches -6 V. 1
When the gate potential is in the ON state after the field period, the pixel potential is written in a polarity opposite to the opposite potential (Vcom), and a DC component is superimposed on the liquid crystal to prevent burn-in.
The auxiliary capacitance line is fixed to a specific potential for all pixels, in this case, -9 V (Vss). This driving method is a general driving method called one-field inversion driving.

[0009]

Although the details of the capacitive coupling drive are described in the embodiments, this is a drive method for modulating the potential of the auxiliary capacitance line in each thin film transistor array. By modulating the auxiliary capacitance wiring potential, the source signal amplitude can be reduced, which is an effective driving method for reducing power consumption.

However, when the storage capacitor potential is modulated, the MOS-
There is a problem that the capacitance value largely fluctuates depending on the auxiliary capacitance wiring potential due to the CV effect, which greatly affects display quality. On the other hand, since a polycrystalline silicon thin film transistor has a higher process temperature than an amorphous silicon thin film transistor, it is difficult to use a low-resistance Al wiring as an auxiliary capacitance wiring material. Therefore, the gate and the auxiliary capacitance wiring of the polycrystalline silicon thin film transistor have a high melting point,
In addition, it is common to use a material such as Mo, W, Cr, or Ta having a relatively small resistivity, or an alloy thereof.

[0011] However, even a low-resistance high-melting-point metal has a wiring resistance three times or more that of Al. In particular, in the case of modulating the capacitance wiring potential using the capacitive coupling driving method for a large screen panel using a polycrystalline silicon thin film transistor, display quality such as crosstalk caused by the wiring resistance of the capacitance wiring becomes a problem.

[0012]

According to the present invention, there is provided an image display thin film transistor array having a polycrystalline silicon thin film as an active layer. A contact formed on the auxiliary capacitance forming electrode wiring with respect to the auxiliary capacitance forming electrode wiring; An active matrix array for an image display device is provided, which has a wiring made of the same material as the data wiring of the thin film transistor for image display electrically connected through a hole.

The auxiliary capacitance forming electrode wiring formed of the same material as the gate electrode is made of a high melting point material containing Mo, W, Cr, Ta, Ni as a main component. By using Al as a main component as a wiring made of the same material as the data wiring of the image display thin film transistor electrically connected through a contact hole formed on the auxiliary capacitance forming electrode wiring, heat resistance to process temperature and Improve wiring resistance.

By implanting impurities of the same conductivity type as the source and drain regions of the image display thin film transistor into the polycrystalline silicon thin film formed under the auxiliary capacitance forming electrode wiring, the potential of the auxiliary capacitance forming electrode wiring is changed from the outside. Eliminates the voltage dependence of the auxiliary capacitance value that occurs when modulation is performed.

The auxiliary capacitance forming electrode wiring is connected to each pixel in the direction of the gate electrode wiring, and a circuit for driving the auxiliary capacitance forming electrode wiring composed of a polycrystalline silicon thin film transistor is provided at both ends of the auxiliary capacitance forming electrode wiring. Forming on the substrate prevents waveform distortion due to the influence of the wiring resistance of the auxiliary capacitance forming electrode, and reduces the number of components by integrating the drive circuit on the same substrate. Further, the active matrix array for an image display device has a display electrode made of an oxide transparent conductor, and the display electrode is directly connected to a polycrystalline silicon thin film formed below the auxiliary capacitance forming electrode wiring via a contact hole. By doing so, the aperture ratio of the thin film transistor array is improved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(Embodiment 1) An active matrix array for a liquid crystal display device using the present invention will be described with reference to FIG.

FIG. 1A is an equivalent circuit diagram of each pixel of an active matrix array for a liquid crystal display device. As shown in FIG. 1A, the liquid crystal 101 is driven by a thin film transistor 103 provided for each pixel. A signal formed by the gate drive circuit 108 is applied to the thin film transistor on the gate electrode wiring 1.
A signal input from the source driver circuit 107 is input via the source electrode wiring 105 to charge the liquid crystal and the auxiliary capacitor 102. The source drive circuit and the gate drive circuit are formed over the same substrate using a polycrystalline silicon thin film transistor. The auxiliary capacitance is formed in parallel with the liquid crystal capacitance for the purpose of holding the voltage charged in the pixel while the thin film transistor is off, but in the present invention, the capacitive coupling that sets the potential applied to the liquid crystal through the auxiliary capacitance Since the driving method is used, the auxiliary capacitance wiring connected for each scanning line is connected to the capacitance wiring driving circuit 109 formed at both ends of the wiring.

The purpose of forming the driving circuits at both ends of the auxiliary capacitance wiring is to reduce the wiring resistance of the capacitance wiring equivalently and to cause the wiring resistance of the capacitance wiring which becomes a problem when the display area of the liquid crystal display device is enlarged. This is to prevent display quality deterioration such as crosstalk. This capacitance wiring drive circuit is also formed on the same substrate using a polycrystalline silicon thin film transistor.

FIG. 1B shows a sectional structure of each pixel when a polycrystalline silicon thin film transistor is used as a pixel electrode driving element. The auxiliary capacitance 102 is formed by a capacitance formed by the gate insulating film 15 between the electrode wiring 106 connected for each scanning line and the polycrystalline silicon 13 connected to the drain electrode of the thin film transistor. The same impurity as the source and drain regions of the polycrystalline silicon thin film transistor is introduced into the polycrystalline silicon thin film 13c under the auxiliary capacitance to reduce the resistance so that the capacitance does not change even when the potential of the auxiliary capacitance line is modulated.

FIG. 2A shows a driving waveform of capacitive coupling driving using the thin film transistor array shown in FIG. 1, and FIG. 2B shows a change in pixel potential accompanying the driving waveform. As shown in FIG. 2A, the gate potential is from +9 V (Vdd: Vgoff) to -6 V (Vgon) as in the conventional example.
Source potential from 0V (Vs +) to 5V (V
s-) and the amplitude voltage are set to half those of the conventional example. As a result, the amplitude of the source voltage having a high frequency is halved, and the power consumption is significantly reduced.

However, since the pixel potential is halved as it is, the shortfall is supplied by modulating the capacitance wiring potential (Vcs). When the capacitance wiring potential is changed by ΔVcs (| Vdd−Vsc |) as in the example shown in FIG. 2A, the pixel potential is changed by the potential of Expression 1. ΔVlc = Cst / (Cst + Clc)
× ΔVcs (Equation 1) Therefore, by setting the Cst value so that ΔVlc can compensate for the reduced source voltage amplitude, the power consumption is reduced and the effective voltage applied to the liquid crystal is the same as that of the conventional driving method. Becomes possible. It has been reported that in the capacitive coupling drive, the response speed of the liquid crystal can be improved by setting the ratio of Cst and Clc to about 1: 1. By setting Cst to this ratio, the power consumption can be reduced and the liquid crystal can be improved. The response speed can be improved.

The thin-film transistor array for a liquid crystal display device of the present invention shown in FIG. 1B reduces the wiring resistance of the auxiliary capacitance line, and introduces impurities into the polycrystalline silicon thin film under the auxiliary capacitance to change the capacitance line potential. As a result, the change in capacitance can be prevented, and as a result, the response speed can be improved while reducing the power consumption of the liquid crystal display device using the polycrystalline silicon thin film transistor array using the high melting point metal for the gate electrode.

(Embodiment 2) FIG. 3 is an example of a sectional view of a manufacturing process of the thin film transistor array when a p-type thin film transistor is used for a pixel electrode driving element. First, as shown in FIG. 3A, an amorphous silicon thin film is formed on a glass substrate 11 coated with silicon oxide 14 by plasma CVD.
It is formed with a thickness of 50 nm by the method. After heat-treating amorphous silicon in nitrogen at 450 ° C. for 90 minutes to reduce the hydrogen concentration in the film, the amorphous silicon thin film is crystallized by excimer laser irradiation to form a polycrystalline silicon thin film. Process into the shape of

Next, as shown in FIG.
Using 5 as an implantation mask, selectively introduce impurities into the polycrystalline silicon thin film under the auxiliary capacitance line 13c. As an impurity, boron was implanted by an ion doping method at an acceleration voltage of 10 kV and a dose of 5 × 10 ¹⁵ / cm ² . After the introduction of the impurities, silicon oxide as the gate insulating film 14 is
It is formed to a thickness of 00 nm. A gate electrode 104 is formed over silicon oxide. The gate electrode was formed of an alloy of molybdenum and tungsten (Mo-35% W) with a thickness of 250 nm.

In the auxiliary capacitance forming portion, an auxiliary capacitance wiring 106 is formed of the same material at the same time as the formation of the gate electrode. After the gate electrode is formed, as shown in FIG. 3 (3), boron is ion-doped at an acceleration voltage of 70 KV and an implantation dose of 2
X 10 ¹⁵ / cm ^{2 is} implanted to form source and drain regions of the pixel thin film transistor. In the ion doping method, a gas obtained by mixing hydrogen gas with boron at a concentration of 15% is plasma-decomposed by high-frequency discharge, and generated ions are injected into a thin film transistor without a mass separation step.

After the impurity implantation, the implanted impurity was activated by a heat treatment at 450 ° C. for 1 hour in a hydrogen atmosphere.
This activation treatment uses a batch-type heat treatment furnace. When the temperature in the furnace reaches 300 ° C. during the temperature drop process after the treatment, high-frequency power is applied and hydrogen plasma is generated for one hour, and then taken out. went. After activation treatment, plasma CVD
Inter-layer insulating film of silicon oxide: 16 to 500 nm
Form. After forming the interlayer insulating film, a contact hole is opened by wet etching containing hydrofluoric acid as shown in FIG.

After opening the contact hole, molybdenum (Mo)
A source electrode 105 in which aluminum (Al) and molybdenum (Mo) are laminated on a thin film and a wiring is also formed on the auxiliary capacitance wiring 106 for the purpose of lowering the resistance of the auxiliary capacitance wiring (FIG. 3 (5)).
After forming the source and the auxiliary capacitance wiring, a flattening film 51 made of an organic material is formed as shown in FIG. 3 (6), and a display electrode 52 made of an ITO film is formed on the flattening film. The thin film transistor array for use is completed.

In this embodiment, a direct contact method is used for electrical connection between the display electrode and the thin film transistor. This eliminates the need for a source electrode, which is a non-translucent material, to be interposed between the display electrode and the thin film transistor, thereby increasing the aperture ratio of the thin film transistor array, reducing power consumption, and improving display luminance.

(Embodiment 3) FIG. 4 is an example of a configuration sectional view of a liquid crystal display device manufactured using the active matrix array described in Embodiments 1 and 2, and a pixel portion is enlarged and displayed. An alignment film 46 is provided between the active matrix array substrate formed on the light-transmitting substrate 11 and the opposing substrate 43.
A liquid crystal 47 is held via the TFT, and the pixel electrode 17 is driven by using the thin film transistor as a switching element to charge the liquid crystal and display an image.

The liquid crystal display device of the present invention is used for driving pixels by connecting p-channel thin film transistors in series.
Although the auxiliary capacitance wiring is formed of a Mo-W alloy, it has a low resistance because it is backed up by a three-layer wiring of Mo / Al / Mo same as the source wiring material through a contact hole, and as a result, as shown in FIG. In addition, wiring delay and waveform rounding when the potential of the auxiliary capacitance wiring is changed by the capacitive coupling drive are eliminated, and the display quality is greatly improved.

Although a p-channel thin film transistor is used as the pixel driving thin film transistor in this embodiment, the same effect can be obtained by using an n-channel thin film transistor having a normal LDD structure.

[0033]

As described in the above embodiments, the thin film transistor array for a liquid crystal display device of the present invention reduces the wiring resistance of the auxiliary capacitance line, and introduces impurities into the polycrystalline silicon thin film under the auxiliary capacitance to reduce the capacitance line potential. Capacitance-coupling drive is applied by preventing the capacitance change due to the change, resulting in improved response speed while reducing power consumption of liquid crystal display device using polycrystalline silicon thin film transistor array using high melting point metal for gate electrode We were able to.

[Brief description of the drawings]

FIG. 1A shows an example of an equivalent circuit diagram of a thin film transistor array for a liquid crystal display device of the present invention. FIG. 1B shows an example of a cross-sectional view of a pixel structure of the thin film transistor array for a liquid crystal display device of the present invention.

2A shows an example of a driving waveform diagram of a liquid crystal display device using the thin film transistor array of the present invention. FIG. 2B shows an example of a pixel potential diagram of a liquid crystal display device using the thin film transistor array of the present invention.

FIG. 3 is a diagram showing an example of a cross-sectional process drawing of manufacturing a thin film transistor array of the present invention.

FIG. 4 is a diagram showing an example of a liquid crystal display device using the thin film transistor array of the present invention.

5A is a diagram showing an example of an equivalent circuit diagram of a conventional thin film transistor array for a liquid crystal display device. FIG. 5B is a diagram showing an example of a pixel configuration cross-sectional view of a conventional thin film transistor array for a liquid crystal display device.

6A is a diagram illustrating an example of a driving waveform diagram of a conventional liquid crystal display device. FIG. 6B is a diagram illustrating an example of a pixel potential diagram of the conventional liquid crystal display device.

[Explanation of symbols]

Reference Signs List 11 glass substrate 13 polycrystalline silicon 13c high-concentration impurity implantation region (source and drain region) 14 undercoat 15 gate insulating film 16 interlayer insulating film (silicon oxide) 25 photoresist 41 black matrix 42 polarizing plate 43 counter substrate 44 color filter 45 Transparent conductive layer 46 Alignment film 47 Liquid crystal 51 Organic planarization film 52 Display electrode 101 Liquid crystal 102 Auxiliary capacitance 103 Thin film transistor 104 Gate electrode wiring 105 Source electrode wiring 106 Auxiliary capacitance wiring 107 Source driving circuit 108 Gate driving circuit 109 Capacitor wiring driving circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 F-term (Reference) 2H092 JA25 JA28 JA46 JA49 JB63 JB66 JB68 KA04 KA16 KA22 KB12 NA23 NA28 5F048 AB10 AC10 BA16 BB03 BB09 BC06 BF02 BF07 5F110 AA03 AA09 BB02 CC02 DD02 DD13 EE02 EE04 EE06 EE29 FF02 FF30 GG02 GG13 GG25 GG45 HJ01 HJ04 HJ12 HJ18 HJ23 HL03 HL04 HL07 HL12 NN13 NN02 NN13 NN02 NN12 NN03

Claims (8)

[Claims] 1. An image display thin film transistor array having a polycrystalline silicon thin film as an active layer on a light-transmitting substrate, wherein each pixel has an auxiliary capacitance forming electrode wiring formed of the same material as a gate electrode, An image display thin film transistor having a polycrystalline silicon thin film below the auxiliary capacitance forming electrode wiring via a gate insulating film, and a contact hole formed on the auxiliary capacitance forming electrode wiring with respect to the auxiliary capacitance forming electrode wiring; An active matrix array for an image display device, wherein the active matrix array is electrically connected to a wiring made of the same material as the data wiring. 2. An auxiliary capacitance forming electrode wiring formed of the same material as the gate electrode is made of a high melting point material containing Mo, W, Cr, Ta, Ni as a main component.
4. The active matrix array for an image display device according to item 1. 3. A wiring made of the same material as a data wiring of the image display thin film transistor electrically connected to the auxiliary capacitance forming electrode wiring via a contact hole formed on the auxiliary capacitance forming electrode wiring. The active matrix array for an image display device according to claim 1, wherein the active matrix array is mainly composed of Al. 4. The method according to claim 1, wherein an impurity of the same conductivity type as a source and drain region of the image display thin film transistor is implanted as a polycrystalline silicon thin film formed under the auxiliary capacitance forming electrode wiring. 4. The active matrix array for an image display device according to any one of 3. 5. A circuit for driving said auxiliary capacitance forming electrode wiring, comprising a polycrystalline silicon thin film transistor at both ends of said auxiliary capacitance forming electrode wiring, each pixel being connected in the direction of a gate electrode wiring. Are formed on the same substrate.
The active matrix array for an image display device according to any one of the above. 6. The active matrix array for an image display device has a display electrode made of a transparent conductive oxide, and the display electrode is formed under the auxiliary capacitance forming electrode wiring via a contact hole. 6. The device according to claim 1, wherein the film is directly connected to the thin film.
The active matrix array for an image display device according to any one of the above. 7. The auxiliary capacitance forming electrode using the active matrix array for an image display device and using the auxiliary capacitance forming electrode wiring driving circuit composed of a polycrystalline silicon thin film transistor formed at both ends of the auxiliary capacitance forming electrode wiring. 7. The liquid crystal display device using a thin film transistor array according to claim 1, wherein a wiring potential is changed within each display field period. 8. An image display device comprising an active matrix array, wherein said auxiliary capacitance Cst and a liquid crystal capacitance Clc are used.
The liquid crystal display device using the thin film transistor array according to any one of claims 1 to 7, wherein the ratio of (1) to (2) is set between 0.8 and 1.2.