JP2004536347A - Active matrix display device - Google Patents

Abstract

The active matrix display device has a plurality of pixels arranged in a matrix and column electrodes extending along the columns of the corresponding pixels. The pixel has a capacitance for storing image data and a readout circuit for reading out the charge stored in the capacitor and driving the column electrode using the readout charge.

Description

【Technical field】
[0001]
The present invention relates to an active matrix display device having an array of display pixels, and more particularly, but not exclusively, to an active matrix liquid crystal display device and an active matrix electroluminescent display device.
[Background Art]
[0002]
Active matrix displays, especially active matrix liquid crystal displays (AMLCDs), are used in a number of product areas, including laptop computer screens, notebook computer screens, desktop computer monitors, PDAs, electronic organs and mobile phones. Telephones are considered the most common.
[0003]
The structure and general operation of a typical active matrix display device, in this case an AMLCD, is described, for example, in US Pat. No. 4,130,829, the entire contents of which are incorporated herein by reference. Briefly, the display comprises an array of pixels arranged in rows and columns, each comprising an electro-optic display element and an associated switching device, usually in the form of a thin film transistor (TFT). The pixels are connected to a set of row and column address electrodes, and each pixel is disposed adjacent an intersection between each electrode of each set, through which pixels are sequentially supplied to each of the row electrodes. The row is selected by being addressed by a select (scan) signal, and a data (video information) signal is supplied to and connected to the pixels of the selected row through the column address electrodes while synchronizing with the row selection. Determine the display output of the individual pixels in the row. The data signal is obtained by appropriately sampling an input video signal of a column address circuit coupled to a column address electrode. Each row of pixels is sequentially addressed to construct a display from an entire array of one field (frame) period, and thus the array of pixels is repeatedly addressed in successive fields. Due to the losses that occur in the pixels, the pixels need to be refreshed regularly with the video information. In the case of AMLCD, it is necessary to periodically invert the polarity of the data signal voltage supplied to the display element in order to prevent deterioration of the LC material. This must be done, for example, after each field (so-called field inversion) or after each row has been addressed similarly (so-called line or row inversion).
[0004]
Most of the power consumption of an active matrix display is related to the transfer of video information from a video signal source to the pixels of the display. This component of power can be reduced if the display pixels can store video information at irregular intervals. In this case, when a change in the display output (brightness) state of the pixel is not required, the designation of the address having the fresh video information can be stopped.
[0005]
Thus, by combining the pixels of an active matrix display with a memory, power can be reduced when still images are allowed. The reason is that data only needs to be sent to the pixel when the image changes, thus reducing power consumption in external circuits and reducing the power in driving the capacitance associated with the connection to the pixel. Consumption is reduced.
[0006]
One approach is to incorporate static memory cells into the pixel and use the state of the memory to control the connection of the pixel electrode to the appropriate drive. However, a major disadvantage of static memories is the complexity associated with the number of transistors and bus lines required for power and control signals.
[0007]
Another known approach to AMLCD is to use pixels (with one TFT / pixel) as a dynamic one bit / pixel memory. The state of a pixel can be detected by adding a sense amplifier to a column electrode capable of detecting a small voltage change when a pixel is connected to the column electrode. At this time, the pixels can be refreshed as required by the dynamic nature of the memory. The problem with this approach is to determine the magnitude of the signal sensed at the column electrodes to the ratio of pixel to column capacitance, making it very small for AMLCDs with a predetermined pixel pitch and resolution. Can be. Another problem is that when driving LC materials used in AMLCDs, it is common to use alternating polarity voltages to suppress material degradation, so sophisticated external sensing and A refresh circuit is required.
[0008]
One example of this type of AMLCD is described in U.S. Pat. No. 4,430,648, the entire contents of which are incorporated herein by reference. In this case, a periodic refresh of the pixel voltage to maintain the image on the display is provided by incorporating sensing and refreshing circuitry within the column addressing circuitry of the display. During a refresh operation, charge is transferred from one row of pixels of the display to the corresponding associated column electrode. A sense circuit is used to detect this charge and determine the state of the pixel. This information is written back to the same pixel by the refresh circuit. Since the value of the column capacitance is large compared to the pixel capacitance, the signal that needs to be detected by the sense circuit is relatively small, which makes the design of the sense circuit difficult and its performance is detrimental to the operation of the display device. Become serious. In particular, the display device may be susceptible to an electrical noise source. Further, when the pixels in the display device are refreshed, the columns of the display device are driven by the refresh circuit according to the stored video information. The charging and discharging of the column capacitance contributes to the power consumption of the display device.
[0009]
U.S. Pat. No. 6,169,532, which is hereby incorporated by reference in its entirety, describes examples of both an AMLCD and an active matrix electroluminescent display using dynamic memory pixels also associated with a sense amplifier coupled to a column electrode. are doing.
[0010]
It is also known that a display device having some memory in a pixel circuit can be operated in a normal mode without using a memory having a pixel function. In this case, an integrated memory (which can be limited to 1 bit / color due to layout constraints) is used in low power mode when displaying still images.
[0011]
European Patent Publication No. 0797182, which is hereby incorporated by reference in its entirety, describes various examples of dynamic memory circuits having in-pixel low impedance drive circuits used in AMLCDs.
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0012]
However, there are problems associated with incorporating a dynamic memory into a pixel. The integration of reliable dynamic memory into the pixels of an active matrix display to avoid adverse complexity or the adverse effect on the pixel aperture by limiting the number of elements such as transistors is considered as an important issue. You. In addition, the refreshing of the dynamic storage element of the pixel must be considered along with the appropriate drive voltage (or in some cases the intra-pixel drive circuit) required for a particular type of display device.
[0013]
The present invention seeks to provide an active matrix display device that is superior to known devices. Various novel concepts, inventive concepts, and specific embodiments are disclosed herein with reference to, but not limited to, the accompanying drawings.
[Means for Solving the Problems]
[0014]
An active matrix display device according to a first aspect of the present invention includes a plurality of pixels arranged in a matrix and a column electrode extending along a corresponding pixel column, wherein the pixel has an image data storage capacitance, A readout circuit for reading the state of the image data storage capacitance and driving the corresponding column electrode using the readout image data.
【The invention's effect】
[0015]
Therefore, the readout circuit functions as a buffer, so that the capacitance used as a dynamic storage element in the pixel can be refreshed as a column electrode. On the other hand, in the conventional arrangement, the integrated small capacitance in each pixel is detected by the sense circuit by using the sense circuit at the end of each column line instead of the readout circuit integrated in the pixel. Can be destroyed by column line capacitance, which can make the charge on the very difficult capacitance very small. Furthermore, by driving the column lines with readout circuits, the effect of the active matrix display on electrical noise can be reduced over conventional arrangements without such circuits.
[0016]
In practice, in this example, the provision of a readout circuit can reduce the size of the image data storage capacitance, or can be reduced by the capacitance present in the pixel for other reasons, such as the capacitance of the liquid crystal pixel electrode. Capacitor.
[0017]
Preferably, the readout circuit has a high input impedance, so that only a small amount of capacitance is discharged during reading, for example, less than 10%, preferably less than 2%, of the stored charge.
[0018]
An example of the present invention is an active matrix display device according to claim 1 or 2, having a row electrode and a readout line extending along a corresponding row of pixels, wherein the pixel is provided by a corresponding row electrode. A switch for connecting a corresponding column electrode to the data storage capacitance when selected, wherein the control circuit is controlled by a corresponding read line to read the capacitance of the corresponding column electrode.
[0019]
The pixel may have a drive circuit for driving a pixel display element, and the drive circuit may have an input connected to the image data storage capacitance. The drive circuit can drive LEDs, liquid crystal display electrodes, or other pixel display elements. In this case, the read circuit constitutes a switch for connecting the column electrode to the output of the drive circuit under the control of the read line.
[0020]
Each pixel may have multiple image data storage capacitances.
By way of example, having a plurality of row electrodes along each row, each row electrode selecting a switch to connect each image data storage capacitor to a data line, the select line connecting a column electrode corresponding to the data line The readout circuit may read data on the data line of the corresponding column electrode under the control of the corresponding readout line.
[0021]
A dedicated readout circuit may be connected to each image data storage capacitance.
[0022]
The present invention is a method of operating an active matrix display device having pixels with storage nodes, comprising storing image data in the storage nodes, operating the active matrix device in a static mode, and storing the stored image data. Displaying, periodically supplying a read signal to a read circuit in the pixel, reading the stored image data from the column electrode, and refreshing the image data stored in the storage node. Also about the method.
[0023]
The method may operate the active matrix display in a normal mode including regular addressing of pixels with fresh video information and display of video information.
BEST MODE FOR CARRYING OUT THE INVENTION
[0024]
FIG. 1 shows a simplified circuit diagram of a generally conventional form of an AMLCD comprising a matrix matrix array (N × M) of display pixels 10. The display elements each have a liquid crystal display element 18 and an associated TFT 12 that functions as a switching device and are addressed through a set of (M) row and (N) column address electrodes 14,16. Here, for the sake of simplicity, only a few display pixels are shown, and in actuality, pixels of several hundred rows and several hundred columns can be used. The drain of each TFT 12 is connected to a display element electrode arranged adjacent to each intersection of a row address electrode and a column address electrode, and at the same time, the gates of all TFTs associated with each row of display pixels 10 are connected to the same gate. The sources of all the TFTs associated with each of the sparsely displayed columns are connected to the address electrodes 14 in the same column. The electrodes 14, 16, the TFT 12, and the display element electrodes are all placed on the same insulating substrate, such as glass, using known thin film techniques including deposition of various conductive, insulating and semiconductor layers and photolithographic sparse graphic patterning. Manufactured. A second glass substrate (not shown) supporting a continuous transparent electrode common to all display elements of the array is spaced apart from the substrate 25 and the two substrates are surrounded by a liquid crystal material. Are sealed together around the periphery of the pixel array to define a defined space. Each display element electrode defines a light modulating LC display element with the overlap of the common electrode and the liquid crystal material in between.
[0025]
In operation, a select (gating) signal is supplied to each row address electrode 14 in order from row 1 to row M by a row drive circuit 30 comprising, for example, a digital shift register, and the data signal is synchronized with the select signal while It is supplied to the column electrodes by the drive circuit 35. When each row electrode 14 is addressed by a select signal, the pixel TFT 12 connected to that column is turned on, and each display element is charged according to the level of the data signal present at the associated column electrode. . After a row of pixels has been addressed, for example, at each row address period (TL) corresponding to the line period of the supplied video signal, the associated TFTs are driven to a field (frame) period to electrically disconnect the display elements. Are turned off in response to the end of the select signal for the rest of the display, thereby storing the applied charge to maintain its display output until the display element is addressed again in the next field period. Thus, each of the rows of pixels of the array from row 1 to row M are addressed in response to each of the successive row address periods TL to construct a display image from the array in one field period TF. , Where TF is equal to or slightly greater than M * TL, and then the operation is repeated for successive fields.
[0026]
The timing of the operation of the row drive circuit 30 and the column drive circuit 35 is controlled by the timing and control unit 40 by a timing signal obtained from an input video signal obtained from, for example, a computer or another source. The video input signal in this input signal is continuously supplied to the column driving circuit 35 through the bus 37 by the video signal processing circuit of the unit 40. The circuit comprises one or more shift register / sample-and-hold circuits, which sample the video information signal in synchronization with the row scan and apply the serial-to-parallel conversion to the row at the time addressing of the pixel array. I do. Successive fields of the video signal according to successive fields of the input video signal are written to the array by repeatedly specifying the rows of pixels of the array in successive field periods.
[0027]
For the transmissive mode of operation, the display element electrodes are made of a light transmissive conductive material, such as ITO, and the individual display elements operate to modulate light directed to one side, for example, from a backlight. As a result, a display image constructed by addressing every row of pixels in the array can be viewed from the other side. In the reflective mode of operation, the display element electrodes are made of a light-reflective conductive material, and light incident from the front of the device through the substrate supporting the common electrode is modulated by the LC material of each display element according to its display state. At the same time as being reflected from the substrate to generate a display image that can be viewed from the front.
[0028]
In accordance with known practice, the drive voltage supplied to the display element is periodically inverted, for example, after each field, to avoid degradation of the LC material. Polarity inversion can also be performed after each row to reduce the effects of flicker (row inversion).
[0029]
In this device, a significant amount of power is consumed in transferring the video signal from the video signal source to the display pixels. In display devices used in portable battery powered devices, such as notebook computers in mobile phones, it is of course desirable to minimize the power consumed by the display device during operation. If the pixel simply repeats the display of the same information, the addressing of the pixel with fresh video information can be stopped, so that if the pixel can store video information during an indefinite period, the power consumption can be reduced, No changes to the display output are required.
[0030]
An embodiment of an active matrix display device according to the present invention, in particular, an AMLCD and an active matrix LED will be described. Each of these embodiments uses a dynamic memory integrated into the pixel that uses the charge stored in the capacitance of one of the nodes in the pixel. A feature of these embodiments is that the readout circuit is integrated into the pixel, thereby allowing the state of the pixel to read out the column electrode. The capacitance used as a dynamic storage element in the pixel can be refreshed through the column electrode. Preferably, the readout circuit integrated into the pixel has a high output impedance, so that the readout circuit does not discharge the capacitance used during storage, even during a read operation.
[0031]
Three examples of pixel configurations are shown diagrammatically in FIGS. The switch 50 shown in these figures corresponds to the switching device 12 of the arrangement of FIG. 1 and similarly includes a TFT. The reading circuit included in the pixel 10 is denoted by 51. In each case, an auxiliary row electrode 52 is provided that extends parallel to the row electrodes 14 and is shared by all pixels 10 in each row. In FIG. 2, the display element 18 is originally capacitive (for example, LC of AMLCD) and is used as a storage node of a dynamic memory by itself. (Typically, in AMLCD, other storage capacitance is usually added in parallel with the LC, not shown). When the switch 50 controlled by the row electrode 14 has low impedance, the voltage is To the display element 18, which voltage is stored in the capacitance of the display element while the switch is in a high impedance state. The readout circuit 51 is connected between the display element 18 and the column electrode 14 and is controlled by an auxiliary column electrode 52. During a read operation, the column electrodes 16 are charged to a voltage determined by the state of the display element. When the read operation is performed, the display element 18 can be refreshed through the column electrode 16. The refresh operation can involve other circuits in the column drive circuit 35 that process signals generated during the read operation.
[0032]
In some active matrix display applications, it is desirable to have another circuit for driving the display element as shown in the embodiment of FIG. 3 having a display element labeled 18 '. An example of this is a display device in which the display element comprises an LED as shown, for example a polymer LED (PLED) or an organic LED (OLED), which requires a drive circuit, denoted 55, for generating a current. A data (video information) signal provided through the switch 50 is stored as a voltage on the switch 50 and a memory capacitor 56 connected between the readout circuit 51 and the drive circuit 55 to function to provide storage node capacitance, The drive circuit is operable to generate a drive current for the display element 18 ', the level of which corresponds to or is determined by the level of the stored signal. Apart from the addition of the drive circuit 55 to the display element, the basic read and refresh operations are the same in this embodiment as in the embodiment of FIG. In the arrangement of FIG. 3, both the display drive circuit 55 and the readout circuit 51 are shown integrally in a pixel.
[0033]
In some cases, this can be simplified by combining the function of the display drive circuit 55 with the readout circuit 5. One example is shown in the embodiment of FIG. In this case, a separate readout circuit is not required, but instead, a second switch 58 is inserted between the output of the display element drive circuit 55 and the column electrode 16, and the operation of the second switch 58 , Through an auxiliary row electrode 52. The read operation is started when the second switch 58 is switched to the low impedance state, at which time the circuit 55 driving the display block 18 'charges the column electrode 14 to a voltage depending on the state of the pixel.
[0034]
Generally, when displaying a still image, it is necessary to execute the read and refresh operations in one row at a time. However, if a region (ie, multiple rows) of the display array has a flat background, the region can be refreshed with a single read and refresh operation. This reduces the power consumed by reducing the plurality of voltage transitions required for the column electrodes 14. In the case of an AMLCD driven during row inversion, the read and refresh operations for a region displaying a flat field are performed by two read and refresh operations, one for each polarity.
[0035]
FIG. 5 shows in more detail an example of an AMLCD pixel circuit using a configuration of the kind shown in FIG. Although an n-channel TFT is shown in this example, a p-channel TFT (or a combination of n and p-channel) can be used when the polarity of the driving voltage is appropriately adjusted. The TFTs T2 and T3 form a read circuit 51. In this example, the pixel has a storage capacitor 60 connected between the display element 18 and the reference line 61, which is shared by other pixels in the same row in the form of other auxiliary row electrodes. . When displaying a still image in the low power mode, the TFTs T2 and T3 are used as one of two voltages of the column electrode 16 to detect the state of the pixel. The pixels are refreshed through the column electrodes 16 and the LC is driven with an alternating polarity each time the pixels are refreshed. As described herein, the circuit can store one bit of data in a pixel. The AMLCD can be operated in a normal mode, where the display array is continuously transmitted from an external source to the display and sampled into the pixels 10 using a known matrix drive architecture. In this mode, T3 is not used and T2 is held off by supplying an appropriate voltage to the auxiliary row electrode 52.
[0036]
When a still image is displayed in the low power mode, a driving mode in which a part of the voltage is applied between LC through a common electrode or through a storage capacitor 60 connected between the display element electrode and the line 61 is preferably used. Can be These particular driving schemes facilitate read and refresh operations.
[0037]
Consider the case where other voltages across the LC are coupled through the storage capacitor line 61 in more detail. 6a and 6b show typical voltage levels that appear during operation of the device, respectively. Vsat and Vth indicate the LC display element saturation voltage level and the LC display element threshold voltage level, respectively. Vcol is the voltage of the column electrode 16 corresponding to the supplied data signal. FIG. 6a shows how the voltage across the LC of the image element 18 changes in four consecutive fields 1-4 for a given pixel in a particular row. When the magnitude of the voltage across LC is Vth, the pixel is at maximum brightness and when it is at Vsat, the pixel is black. The shaded area represents the range of voltages across the LC material when displaying different gray scales in normal mode operation. The polarity of the voltage across the LC is reversed field by field to extend the life of the LC. FIG. 6b shows the corresponding voltage of the display element electrode in relation to the voltage of the column electrode, in which case the column electrode voltage range lies between a minimum of 0 and a maximum of Vcol. The other electrode coupled to the display element electrode through the storage capacitor line 61 will be ± ΔV,
ΔV = Vcap. Cs / (Cs + CLC)
And Vcap is the swinging voltage on the storage capacitor line 61, which is + Vcap for odd fields (for a particular row), -Vcap for even fields (for a particular row), and Cs and CLC are storage capacitors, respectively. 60 and the capacitance of the LC display element 16.
[0038]
When displaying a still image in the low power mode, the LC is driven at ± Vth (“bright” pixels) or ± Vsat (“dark” pixels). As can be seen from FIG. 6b, the corresponding voltages on the display element electrodes are (i) + ΔV for odd fields and −ΔV for even fields for bright pixels, and Vcol + ΔV for odd fields for dark pixels. And -ΔV in even fields.
[0039]
The detection of the state of the pixel is performed by returning the voltage of the display element electrode to the initial value sampled from the column electrode to the pixel before coupling ± ΔV from the capacitance line 61. This is done by switching the voltage on the capacitance line, which means that the voltage on the display element electrode returns to 0 or Vcol. For a bright pixel, the voltage of the display element electrode returns to 0 in odd fields and returns to Vcol in even fields. For dark pixels, the voltage of the display element electrode returns to Vcol in odd fields and returns to 0 in even fields.
[0040]
The pixel sensing and refresh operation as shown in FIG. 5 is shown in FIG. 7, which shows a possible driving waveform and two adjacent dark pixels of successive rows n and n + 1 connected to the same column electrode 16. The related timing is shown. In this example, the polarity of the LC drive voltage is inverted for each row (row inversion), but this is not a necessary form. In FIG. 7, Vcap (n) and Vcap (n + 1) indicate waveforms supplied to the capacitor driving line 61 for the pixel rows n and n + 1, respectively, and Vs (n) and Vs (n + 1) indicate the pixel row n And n + 1, respectively, showing the select signal waveforms provided to the row electrode 14 associated with the pixel row n and n + 1, respectively. And Vpix (n) and Vpix (n + 1) are voltage waveforms appearing at the nodes 65 of the pixels (FIG. 5) of the pixel rows n and n + 1, respectively. The detection and refresh operation involves the following steps.
1) Switch the capacitor line 61 to restore the pixel voltage to 0 or Vcol.
2) Precharge the column electrode 16 to Vcol (in FIG. 7, when the precharge control signal PC goes high, precharge occurs).
3) Turn on T2 to detect the state of the pixel on the column electrode. When Vpix = Vcol, T3 is turned on and the column electrode is discharged to VSS (0 V). When Vpix = 0, T3 is turned off and the column electrode voltage is maintained at Vcol. This means that the column electrode voltage has been inverted with respect to Vpix.
4) Return the capacitor line 61 to the previous level.
5) Write the inverted data back to the pixel by turning on T1.
6) Switch capacitor line 61 to couple to another pixel voltage appropriate to drive LC.
If desired, Vss can take on values other than 0V.
[0041]
FIG. 8 shows a second example of a pixel circuit having the same configuration as that of FIG. 2 and applied to the AMLCD. In this case, the state of the pixel of the column electrode 16 being read is detected by using an inverter constituted by TFTs (p-type and n-type) T4 and T3, thereby precharging the column electrode before the read operation. Avoid requests. This has the advantage that the number of transitions on the column electrodes can be reduced depending on the image and whether field conversion or line conversion is used.
[0042]
In the two examples already described with reference to FIGS. 5 and 8, the still image stored in the low power mode has no gray scale (ie, the stored image is 1 bit / pixel). Gray scale can be introduced by using the same readout circuit that detects multiple levels. This can be performed by dividing the read time into a plurality of stages and stepping the voltage of the capacitor line 61. During one of these steps, the voltage on the display element 18 of the pixel exceeds the threshold voltage, and when it rises above the threshold voltage, the readout circuit can invert the voltage on the column electrode. The point at which inversion occurs depends on the initial voltage of the display element, so that this causes a read operation. In this case, another circuit is required for the column drive circuit 35 to generate an appropriate voltage for refreshing the pixel. Another way to achieve gray scale is to subdivide each pixel into multiple (areaed) sub-pixels, where each of the sub-pixels remains driven at dark or maximum brightness.
[0043]
Even though the examples already described are applicable to situations where the capacitor line drive mode is used, the same principles apply to the common electrode drive mode.
[0044]
FIG. 9 shows a third example of the pixel circuit having the same configuration as that of FIG. In this circuit, the TFT T2 forms a second switch 58, and the TFTs T3 and T4 form a drive circuit 55. The display element can be an LC display element or a current driven display element such as an LED.
[0045]
FIG. 10 shows a circuit having a plurality of capacitors, each storing 1-bit data, wherein a plurality of bits specify a gray scale level.
[0046]
The plurality of data storage capacitors 70 are connected to corresponding columns 16 through TFTs 12 connected to a common row address line 14. Auxiliary row electrodes 52 control read circuit 51 for each of data storage capacitors 70. Pixel drive circuit 72 is represented linearly by a box 72 having an input from each of data storage capacitors 70.
[0047]
In use, data can be provided to data storage capacitor 70 in parallel with column 16. By providing a signal to the auxiliary row electrode 52, data can be recalled from column 16 so that the data can be sequentially rewritten and refreshed.
[0048]
Another multi-bit arrangement is shown in FIG. 11, which has multiple address lines 14 for each row and a single column line 16 for each column. A selection line 76 is provided for each row to control a selection transistor 74 that connects the column line 16 to the TFT 12 via the data line 77.
[0049]
In use, one of the plurality of address lines 14 is enabled and the corresponding data storage capacitor 70 is selected. The read line 52 may be enabled to allow the read circuit 51 to read the data of the selected data storage capacitor 70 on the column line 16. The select line 76 can also enable the select TFT 74 to write the data on the column line 16 to the selected data storage capacitor 70.
[0050]
An example of the read circuit 51 connected to the data storage capacitor 70 is shown in FIG. Data storage capacitor 70 controls a first TFT 80 connected in series to column 16 through a read TFT 82. The read TFT 82 is controlled by the read line 52. When the read line 52 switches on the read TFT 82, the data stored in the data storage capacitor 70 is read in column 16.
[0051]
The data of the plurality of data storage capacitors 70 is connected to the drive circuit 72 by a single data line 84 as shown in FIG. 13, with the parallel connection of the data storage capacitors 70 to drive the circuit 72 as described above. be able to. In this circuit, data is transferred to the drive circuit 72 by addressing the individual TFTs 12 one after another and connecting the corresponding data storage capacitor 70 to the drive circuit 72.
[0052]
Another embodiment is shown in FIG. 14, which performs a sequential charge redistribution digital-to-analog conversion using the pixel capacitance 18 itself. The features of this circuit are described in detail in U.S. Pat. Nos. 5,448,258 and 5,923,311 and are incorporated herein by reference. For current purposes, a capacitor 70 is connected through each switch 12 to a data line 84, which drives the pixel capacitance 18, as shown in FIG.
[0053]
In stationary mode, some of the pixels in the array can be operated simultaneously using data stored in the pixels and otherwise using data provided by an external signal source. This can be done without modifying the pixel circuit by simply dividing the display using appropriate signals. This approach can minimize power consumption.
[0054]
For example, part of the display shows a moving image, and the rest of the display shows a still background. The external video source need only supply data to the display in the area of the image representing the moving image, thereby saving power.
[0055]
The present invention is applicable to various active matrix display devices, and the same pixel circuit as described above can be used for display devices other than AMLCD and AMLED. In this case, for example, an electrochromic type It is desirable to store still images in display devices of the electrophoretic and electroluminescent type. One example of an active matrix LED is described in European Patent Publication No. 115205, the contents of which are incorporated herein as background material.
[0056]
The present invention is not limited to the above embodiment, and many modifications and variations are possible.
[Brief description of the drawings]
[0057]
FIG. 1 is a simplified linear diagram of a typical known AMLCD.
FIG. 2 shows different pixel circuit configurations in each embodiment of the active matrix display device according to the present invention.
FIG. 3 shows different pixel circuit configurations in each embodiment of the active matrix display device according to the present invention.
FIG. 4 shows different pixel circuit configurations in each embodiment of the active matrix display device according to the present invention.
FIG. 5 illustrates an example of a typical pixel circuit in one embodiment in more detail.
FIG. 6 illustrates various possible voltage levels appearing in an example of an AMLCD using a particular drive configuration.
FIG. 7 shows an example of a driving waveform during operation in an example of an AMLCD.
FIG. 8 shows another example of a typical pixel circuit in an embodiment of an AMLCD according to the present invention in detail.
FIG. 9 shows another example of a typical pixel circuit in another embodiment of the AMLCD according to the present invention in detail.
FIG. 10 shows another example of a pixel circuit having a plurality of data storage capacitors.
FIG. 11 shows another example of a pixel circuit having a plurality of data storage capacitors.
FIG. 12 shows a read circuit.
FIG. 13 shows another example of a pixel circuit having a plurality of data storage capacitors.
FIG. 14 shows another example of a pixel circuit having a plurality of data storage capacitors.

Claims (10)

A plurality of pixels arranged in a matrix and a column electrode extending along a column of the corresponding pixels, wherein the pixels read the image data storage capacitance and the state of the image data storage capacitance and use the read image data. And a readout circuit for driving a corresponding column electrode. 2. The active matrix display device according to claim 1, wherein said readout circuit has a sufficiently high input impedance such that charges stored in said image data storage capacitance are not significantly discharged during readout. 3. An active matrix display device according to claim 1, comprising a row electrode and a readout line extending along a corresponding row of pixels, the active matrix display device corresponding to the pixel when selected by a corresponding row electrode. An active matrix display device having a switch connecting a corresponding column electrode to the data storage capacitance, wherein the control circuit is controlled by a corresponding read line to read the capacitance of the corresponding column electrode. 4. The active matrix display device according to claim 3, wherein the pixel has a driving circuit for driving a pixel display element, and the driving circuit has an input connected to the image data storage capacitance. 5. The active matrix display of claim 4, wherein said readout circuit comprises a drive circuit and a switch connecting an output of said drive circuit to said corresponding column electrode under control of a sulfur readout line. apparatus. 6. The active matrix display device according to claim 1, wherein each pixel has a plurality of image data storage capacitances. A plurality of row electrodes along each row, wherein each row electrode selects a switch to connect each image data storage capacitor to a data line, and the selection line switches to connect a corresponding column electrode to the data line. 7. The active matrix display device according to claim 6, wherein said read circuit reads data on a data line of a corresponding column electrode under control of a corresponding read line. 7. The active matrix display device according to claim 6, further comprising a dedicated readout circuit connected to each of the image data storage capacitors. A method of operating an active matrix display having pixels having storage nodes, comprising:
Storing image data in the storage node;
Operating the active matrix device in stationary mode;
Display the stored image data,
A read signal is periodically supplied to a read circuit in the pixel to read stored image data from a column electrode;
Refreshing image data stored in the storage node. 10. The method of claim 9, comprising operating the active matrix display in a normal mode including regular addressing of pixels using fresh video information and displaying video information.

Images