KR100888461B1 - Active matrix display devices - Google Patents

Abstract

The active matrix display device comprises a plurality of pixels 10 arranged in rows and columns and column electrodes 16 extending along corresponding columns of the pixels 10. The pixel includes capacitances 18 and 70 for storing image data and readout circuitry for reading the charge stored on the capacitances 18 and 70 and for driving the column electrode with the readout charges.

Description

Active Matrix Display Devices {ACTIVE MATRIX DISPLAY DEVICES}

The present invention relates to an active matrix display device comprising an array of display pixels, and more particularly to an active matrix liquid crystal display device and an active matrix electroluminescent display device, although not exclusively.

Active matrix display devices, and more specifically active matrix liquid crystal display devices (AMLCDs), are now being used in a growing variety of product areas, among which laptop and notebook computer screens, desktop computer monitors, PDAs, electronic organizers ( electronic organizers and mobile phones are probably the most familiar.

The structure and general operation of a typical active matrix display device is described in US-A-5130829, in which case an AMLCD is incorporated herein by reference, for example. For simplicity, such display devices comprise an array of pixels, arranged in rows and columns, generally in the form of thin film transistors (TFTs), each comprising an electro-optical display element and an associated switching device. The pixels are connected to a set of row and column address electrodes, each pixel located adjacent to the intersection between the corresponding electrodes of each set, through which the pixels are sequentially arranged for a selection (scanning) signal to select a row. Is applied to each row electrode, and a data (video information) signal is supplied to the pixels of the selected row synchronously with the row selection through the column address electrodes, and is determined by addressing the display output of the individual pixels of the relevant row. The data signal is derived by appropriately sampling the input video signal in a column address circuit connected to the column address electrode. Each row of pixels is addressed in turn in order to construct a display from the entire array in one field (frame) period, and the array of pixels is repeatedly addressed in this manner in successive fields. Due to the losses incurred in pixels, it is necessary to refresh the pixels regularly with video information. In the case of an AMLCD, the polarity of the data signal voltage applied to the display element needs to be inverted periodically to prevent degradation of the LC material. This can be done for example after each field (so-called field inversion) or likewise each row (so-called line or row inversion) is addressed.

Much of the power consumption of an active matrix display device is associated with transmitting video information from a video signal source to pixels of the display device. This component of power can be reduced if the pixels of the display device can store video information for an infinite period of time. In such a case, addressing the pixel with new video information may be stopped when no change is required in the display output (luminance) state of the pixel.

Therefore, integrating memory into the pixels of an active matrix display device can reduce power when still image display is allowed, since data needs to be transferred to the display pixels as the image changes, thereby reducing the need for external circuitry and into the display pixels. Less power is consumed in driving the capacitance associated with the connection of the < RTI ID = 0.0 >

One approach is to integrate a static memory cell into the pixel and use the state of the memory to control the connection of the pixel electrode to the appropriate drive source. However, a major drawback of static memory is the complexity in the number of transistor and bus lines needed for power and control signals.

Another known approach for AMLCD displays is to use pixels (with one TFT per pixel) as dynamic 1 bit / pixel memory. Sensing the state of the pixel is achieved by adding a sense amplifier to the column electrode that can detect small voltage changes when the pixel is connected to the column electrode. The pixels can then be refreshed as required by the dynamic nature of the memory. The problem with this approach is that the magnitude of the signal sensed on the column electrode is determined by the ratio of pixel and thermal capacitance, which can be very small in an AMLCD with a predetermined pixel pitch and resolution. Another problem is that in order to limit the deterioration of the material, it is common to drive the LC material being used in AMLCDs with alternating polarity voltages, thus requiring a complex external sensing and refresh circuit to drive the heat.

An example of this kind of AMLCD is described in US patent (US-A-4430648), the contents of which are incorporated herein by reference. Here, periodic refreshing of the voltage on the pixel to maintain an image on the display is achieved by incorporating the sense and refresh circuitry into the column addressing circuitry of the display. During the refresh operation, charge is transferred from the pixels in one row of the display device onto the corresponding, associated column electrode. The sensing circuit then detects this charge and is used to determine the state of the pixel. This information is then written back to the same pixel by the refresh circuit. Due to the relatively large value of the thermal capacitance compared to the pixel capacitance, the signal to be detected by the sensing circuit is relatively small, which makes the design of the sensing circuit difficult and affects the performance of the sensing circuit in the operation of the display device. In particular, the display device may be sensitive to a source of electrical noise. In addition, as the pixels in the display device are refreshed, the columns of the display device are driven in accordance with the video information stored by the refresh circuit. The charging and discharging of the thermal capacitance will contribute to the power consumption of the display device.

The US patent (US-A-6169532), the contents of which are also incorporated herein by reference, discloses an AMLCD and an active matrix electroluminescent display device that similarly uses dynamic memory pixels in conjunction with a sense amplifier connected to a column electrode. Explain the example.

A display device with some memory in the pixel circuit can also be operated in normal mode, without the need to use memory in the pixel function. The integrated memory (which can be limited to only 1 bit / color due to layout limitations) is then used in the low power mode for displaying still images.

European Patent (EP-A-0797182), the contents of which are hereby incorporated by reference, describes various examples of dynamic memory circuits having an in-pixel low impedance driver circuit used in AMLCDs. do.

 However, there is a problem in merging dynamic memory into pixels. The integration of reliable dynamic memory into the pixels of an active matrix display device, for example, to limit the number of elements required, such as transistors, to avoid excessive complexity or adversely affect the pixel openings, is considered to be an important issue. do. In addition, the refresh of the dynamic storage element in the pixel also needs to be considered along with the appropriate drive voltage (or in-pixel drive circuit as in the above case) required for the particular type of display device.

The present invention provides an active matrix display device that provides or allows enhancements on known devices. Various new concepts, inventive concepts, and specific embodiments are disclosed herein, particularly with reference to the accompanying drawings, but are not exclusive.

An active matrix display device according to a first aspect of the invention comprises: a plurality of pixels arranged as rows and columns; And a column electrode extending along the column; The pixel here includes a readout circuit for reading out the image data storage capacitance and the state of the image data storage capacitance and for driving the corresponding column electrode in accordance with the read image data.

The readout circuit thus functions as a buffer, so that the capacitance being used as a dynamic storage element in the pixel can be refreshed through the column electrode. In contrast, in a prior art configuration in which there is no read circuit integrated in a pixel but with a sense circuit at the end of each column line, the small capacitance integrated in each pixel detects the effect of being able to be very small charge on the capacitance. It can be swamped by the capacitance of the column line making it very difficult to detect at. Also, by driving the column lines with readout circuits, the sensitivity of the active matrix display device to electrical noise can be reduced on prior art configurations without such circuits.

Indeed, in embodiments it may also be possible to reduce the size of the image data storage capacitance or provide a readout circuit to replace the discrete capacitor with a capacitance present within the pixel for other reasons, such as the capacitance of the liquid crystal pixel electrode. Can be.

Preferably, the read circuit has a high input impedance such that the capacitance is discharged very little during the read operation, ie only 10% or less of the stored charge, preferably 2% or less.

Embodiments of the present invention include a row electrode and a read electrode extending along a row of pixels, the pixel including a switch connecting the column electrode to the capacitance when the switch is selected by the row electrode and the read circuit being on the column electrode. Controlled by the read line to read the data stored on the capacitance to.

The pixel may comprise a driving circuit for driving the pixel display element, which has its input coupled to the image data storage capacitance. The drive circuitry can drive LEDs, liquid crystal display electrodes or other pixel display elements. In this case the readout circuit may consist of a switch which connects the output of the drive circuit to the column electrode under the control of the readout line.

Each pixel may include a plurality of image data storage capacitances.

In an embodiment, the display may include a plurality of address lines along each row, each address line selecting a corresponding switch connecting each image data storage capacitance to the data line, wherein the selection line connects the data line to the column electrode. A switch to connect is controlled, wherein the readout circuit reads data on the data line onto the column electrode under the control of the read line.

Alternatively, dedicated readout circuitry can be coupled to each image data storage capacitance.

The invention also relates to a method of operating an active matrix display device having a pixel element comprising a storage node, the method comprising; Storing image data on the storage node and operating the active matrix device in a stationary mode; and displaying the stored image data; and reading in the pixel element to cause the reading circuit to read the stored image data to the column electrode. Periodically applying a read signal to the circuit and refreshing the image data stored on the storage node.

The method may further include a method of operating the active matrix display device in a normal mode comprising regularly addressing pixel elements with new video information and displaying video information.

Other features and advantages of the present invention will become apparent by reading the following description of the preferred embodiments given with reference to the accompanying drawings and by way of example only.

1 is a simplified schematic diagram of a typical known AMLCD.

2, 3 and 4 schematically illustrate different pixel circuit configurations in each embodiment of an active matrix display device in accordance with the present invention.

5 illustrates in more detail an example of a typical pixel circuit in one embodiment.

6A and 6B illustrate various possible voltage levels seen in an exemplary AMLCD device utilizing a particular drive structure.

7 illustrates exemplary drive waveforms during operation in an exemplary AMLCD.

8 illustrates in detail another example of a typical pixel circuit in an embodiment of an AMLCD in accordance with the present invention.

9 illustrates in detail another example of a typical pixel circuit in another embodiment of an AMLCD in accordance with the present invention.

10 illustrates another example of a pixel circuit having a plurality of data storage capacitors.

FIG. 11 shows another example of a pixel circuit having a plurality of data storage capacitors. FIG.

12 is a readout circuit diagram.

13 illustrates another example of a pixel circuit having a plurality of data storage capacitors.

14 illustrates another example of a pixel circuit having a plurality of data storage capacitors.

Like reference numerals are used throughout the drawings to indicate the same or similar parts.

Referring to FIG. 1, a simplified schematic circuit diagram of an AMLCD in general form, including a matrix matrix array (M × N) of display pixels 10 is shown. Each display pixel has a liquid crystal display element 18 and an associated TFT 12 that acts as a switching device and is addressed through a set of (M) rows and (N) column address electrodes 14 and 16. Only a few display pixels are shown here for simplicity and there may actually be a matrix of hundreds of pixels. The drain of each TFT 12 is connected to each display element electrode located adjacent to the intersection of each matrix address electrode, while the gates of all the TFTs associated with each row of display pixels 10 are the same row address electrode 14. Are connected to each column of display pixels, and the source of all the TFTs is connected to the same column address electrode 16. The electrodes 14, 16, TFT 12 and display element electrodes are all housed on the same insulating substrate, eg made of glass, and are known to include deposition and photolithographic patterning of various conductive, insulating and semiconducting layers. It is manufactured using thin film technology. The second glass substrate (not shown), which houses a continuous transparent electrode common to all display elements in the array, is arranged spaced apart from the substrate 25, and the two substrates are enclosed spaces containing liquid crystal material. Are sealed together around the periphery of the pixel array. Each display element electrode sharing an overlap with the common electrode and the liquid crystal material between these two electrodes define a light-modulated LC display element.

In operation, a select (gating) signal is applied from each row to the M row in turn by each row address electrode by the row drive circuit 30, including, for example, a digital shift register, and the data signal is applied to the column drive circuit 35. Is applied to the column electrode 16 in synchronization with the selection signal. As soon as each row electrode 14 is addressed with a selection signal, the pixel TFT 12 connected to this row electrode is turned on, thereby causing each display element to have a level of data signal present on its associated column electrode. To be charged accordingly. After a row of pixels is addressed in each row address period T _L corresponding to, for example, the line period of an applied video signal, its associated TFT selects for the remainder of the field (frame) period to electrically insulate the display element. When the signal ends, it is turned off, thereby ensuring that the applied charge is stored to maintain its display output until the row of pixels is addressed again in subsequent field periods. The rows of each pixel in the array from one row to M rows are addressed in this manner in each successive row address period T _L in order to compose the display image from the array in one field period Tf, Where Tf is equal to or slightly larger than M × T _L , after which the operation is repeated for successive fields.

The timing of the operation of the row and column drive circuits 30 and 35 is controlled by the timing and control unit 40 in accordance with a timing signal derived from an input video signal, for example obtained from a computer or other source. The video information signal in this input signal is supplied to the column drive circuit 35 in series via the bus 37 by the video signal processing circuit in the unit 40. The circuit includes one or more shift registers / samples and hold circuits that sample the video information signal synchronously with row scanning to provide proper deserialization for the rows in the time addressing of the pixel array. Successive fields of video information following successive fields of the input video signal are written into the array by repeatedly addressing the rows of pixels of the array in successive field periods.

For a transmission mode of operation, the display element electrode is made of a light transparent conductive material such as ITO and the individual display elements serve to modulate light directed to one side, for example, from the backlight, thus addressing all rows of pixels in the array. Can be viewed from the other side. For the reflective mode of operation, the display element electrode is made of a light reflective conductive material and the light entering the front of the device through the substrate containing the common electrode is modulated by the LC material at each display element and is shown to the viewer from the front In order to produce a, it is reflected back through the substrate, according to its display state.

According to a known practice, the polarity of the driving voltage applied to the display element is periodically reversed, for example after every field, in order to avoid deterioration of the LC material. Polarity inversion can also be performed after every row (row inversion) to reduce the flicker effect.

In this device, a significant amount of power is consumed in the transmission of video information from a video signal source to display pixels. When the display device is used in portable, battery-powered, equipment, such as a notebook computer or mobile phone, it is of course desirable to minimize the electrical power consumed by the display device during operation. If a pixel continues to display only the same information and no change is required in its display output, addressing the pixel with new video information can be stopped, so if the pixel can store video information for an indefinite period of time, the power consumed can be reduced. have.

Embodiments of active matrix display devices, in particular AMLCDs and active matrix LED display devices, according to the invention will now be described. Each embodiment utilizes a dynamic memory integrated into a pixel using charge stored on the capacitance of one of the nodes within the pixel. The characteristic of this embodiment is that the readout circuit is also integrated in the pixel, which causes the state of the pixel to be read onto the column electrode. The capacitance being used as the dynamic storage element in the pixel can then be refreshed through the column electrode. The read circuit integrated in the pixel preferably has a high input impedance so as not to discharge the capacitance used for the memory even during the read operation.

Three exemplary pixel configurations are shown schematically in FIGS. 2, 3 and 4. The switch 50 shown in this figure corresponds to the switching device 12 in the configuration of FIG. 1 and may similarly comprise a TFT. The readout circuit included in pixel 10 is referred to by numeral 51. In each case, a supplementary row electrode 52 is provided that extends parallel to the row electrode 14 and is shared by all pixels 10 in each row. In FIG. 2, display element 18 is originally capacitive (eg, LC in AMLCD) and is being used as a storage node of dynamic memory by itself. (Additionally, additional storage capacitance in AMLCDs is generally added parallel to the LC, although not shown here.) The column electrode 16 when the switch 50, which is controlled by the row electrode 14, has a low impedance. Is transferred from the display element 18 to the display element 18, which is stored on the capacitance of the display element while the switch is in a high impedance state. The readout circuit 51 is connected between the display element 18 and the column electrode 16 and is controlled by the auxiliary row electrode 52. During the read operation, the column electrode 16 is charged to a voltage determined by the state of the display element. Once the read operation has been performed, it is then possible to refresh the display element 18 via the column electrode 16. The refresh operation may include additional circuitry in the column drive circuit 35 to process the signal generated during the read operation.

In some active matrix display applications, it is desirable to include additional circuitry to drive the display element, as shown in the embodiment of FIG. 3 with the display element 18 '. Examples thereof are indicated in the drawings of a polymer LED (PLED) or organic LED (OLED) device, which requires a driving circuit, shown here by reference number 55, for which the display element can supply current, for example. As is a display device comprising an LED. The data (video information) signal supplied through the switch 50 is a memory capacitor 56 connected between the switch 50 serving to provide storage node capacitance and the read circuit 51 and the drive circuit 55. Stored as a voltage on the phase, the drive circuitry is operable to provide a drive current to the display element 18 'having a level that corresponds to or is determined by the level of the stored signal. Besides the addition of the drive circuit 55 to the display element, the basic read and refresh operations are the same as in the embodiment of FIG. In the configuration of FIG. 3, both the display driving circuit 55 and the reading circuit 51 are shown integrated in the pixel.

In some cases, it is possible to combine the functionality of the display drive circuit 55 with the readout circuit 51 to simplify this. An example of this is shown in the embodiment of FIG. 4. In this case, a separate read circuit is not required, but instead a second switch 58 is inserted between the output of the display element drive circuit 55 and the column electrode 16, which second switch 58 is provided. The operation of is controlled via the auxiliary row electrode 52. The read operation commences when the second switch 58 is switched into a low impedance state, at which time the circuit 55 driving the display element 18 ′ is applied to the column electrode 16 up to a voltage depending on the state of the pixel. To charge.

In general, when displaying still images, it is necessary to perform read and refresh operations one row at a time. However, if an area (ie multiple rows) of the display array has a plain background, it is possible to refresh this area in a single read and refresh operation. This reduces the power consumed by reducing the number of voltage transitions required on the column electrode 16. In the case of an AMLCD driven by row inversion, the read and refresh operations for the area displaying the flat field will be performed in two read and refresh operations, once for each polarity.

FIG. 5 shows in more detail an example of an AMLCD pixel circuit employing a configuration of the kind as illustrated in FIG. 2. Although an n-channel TFT is shown in this example, it is equally possible to use a p-channel TFT (or a combination of n and p-channel) if the polarity of the driving voltage is properly adjusted. The TFTs T2 and T3 form the read circuit 51, while the TFTs T1 consist of a switch 50. In this example, the pixel comprises a storage capacitor 60 connected between the reference line 61 and the display element 18, which are shared by other pixels in the form of the same row and other auxiliary row electrodes. When displaying a still image in the low power mode, the TFTs T2 and T3 are used to sense the state of the pixel as one of two voltages on the column electrode 16. The pixel is then refreshed through the column electrode 16 in such a way that the LC is driven with alternating polarity every time the pixel is refreshed. As described herein, the circuit allows one bit of data per pixel to be stored. The AMLCD can also be operated in a normal mode in which the display array is continuously transmitted from an external source to the display device and updated with video data sampled onto the pixel 10 using known row and column drive structures. In this mode, T3 is not used and T2 remains in its off state by applying an appropriate voltage to the auxiliary row electrode 52.

When displaying a still image in the low power mode, a drive structure is used in which part of the voltage across the LC is applied through either the common electrode or the storage capacitor 60 connected between the display element electrode and the line 61. It is preferable. This particular drive structure facilitates read and refresh operations.

The case where the additional voltage across the LC is connected via the storage capacitor line 61 will now be considered in more detail. 6A and 6B illustrate typical voltage levels respectively seen in the operation of the device. Vsat and Vth indicate LC display element saturation and threshold voltage levels, respectively. Vcol is the voltage on the column electrode 16 corresponding to the applied data signal. FIG. 6A shows how the voltage across the LC in display element 18 varies over four consecutive fields, ie fields 1-4, for a given pixel in a particular row. When the magnitude of the voltage across the LC is Vth, the pixel is in a state of maximum brightness, and the pixel is black when the magnitude of the voltage across the LC is Vsat. The shaded areas indicate the range of voltages across the LC material to display different gray scales in the normal mode of operation. The polarity of the voltage across the LC is inverted every field to improve the lifetime of the LC. 6B shows the corresponding voltage on the display element electrode relative to the voltage on the column electrode, where the column electrode voltage range is between the minimum value of 0 and the maximum value of Vcol. The additional voltage connected to the display element electrode via the storage capacitor line 61 is ± ΔV, where;

ΔV = VcapC _s / (C _s + C _LC )

And Vcap is the voltage oscillating on the storage capacitor line 61, which varies by + Vcap in the odd field (for a particular row) and -Vcap in the even field (for a particular row), and C _s and C _LC are Capacitance of storage capacitor 60 and LC display element 18, respectively.

When displaying a still image in low power mode, the LC is driven to either Vth ("light" pixels) or ± Vsat ("black" pixels). From FIG. 6B the corresponding voltage on the display element electrode is; (Iii) For light pixels, it is + ΔV in odd fields, Vcol-ΔV in even fields, and (ii) for black pixels, Vcol + ΔV in odd fields and -ΔV in even fields. Can be.

Sensing the state of the pixel is accomplished by first returning the voltage on the display element electrode to ± ΔV from the capacitor line 61 to an initial value that is sampled from the column electrode into the pixel. This is done by switching the voltage on the capacitor line, which means that the voltage on the display element electrode returns to either 0 or Vcol. For a light pixel, the voltage on the display element electrode returns to zero in the odd field and to Vcol in the even field. For black pixels, the voltage on the display element electrode returns to Vcol in odd fields and to zero in even fields.

The sensing and refreshing operation of the pixels as shown in FIG. 5 involves the associated timing and possible drive waveforms for two adjacent black pixels in consecutive rows n and n + 1, connected to the same column electrode 16. Is further illustrated in FIG. In this example, the polarity of the LC drive voltage is inverted every row (row inversion), although this is not a necessary characteristic. In FIG. 7, Vcap (n) and Vcap (n + 1) are waveforms applied to the capacitor drive line 61 for pixel rows n and n + 1, respectively. Vs (n) and Vs (n + 1) are select signal waveforms applied to the row electrodes 14 associated with pixel rows n and n + 1, respectively, and V _R (n) and V _R (n + 1). Are waveforms applied to the auxiliary row electrodes 52 associated with pixel rows n and n + 1, respectively, and Vpix (n) and Vpix (n + 1) are pixel rows n and pixel rows n + 1, respectively. Is a voltage waveform that appears at node 65 at pixel (FIG. 5). The sense and refresh operations include the following steps.

1) switching capacitor line 61 to restore the pixel voltage to either 0 or Vcol.

2) pre-charging the column electrode 16 to Vcol (pre-charging occurs when the pre-charge control signal PC is high in FIG. 7).                 

3) turning on T2 to sense the state of the pixel onto the column electrode;

When Vpix is Vcol, T3 is turned on and the column electrode is discharged to V _SS (0V). When Vpix is 0, T3 is off and the column electrode voltage is maintained at Vcol. This means that the column electrode voltage is inverted compared to Vpix.

4) switching the capacitor line 61 back to the previous level.

5) turning on T1 to write the inverted data back into the pixel.

6) switching capacitor line 61 to connect an additional pixel voltage suitable for driving the LC.

It should be understood that V _ss can take a value other than 0V if necessary.

A second example, applied to the pixel circuit and AMLCD having the same configuration as in FIG. 2, is shown in FIG. In this case, the inverter configured by the TFTs (p and n type) T4 and T3 is used to sense the state of the pixel on the column electrode 16 during the read operation, which is performed before the read operation. The need for pre-charging is avoided. This has the advantage that the number of transitions on the column electrode can be reduced, depending on the image and whether field or line reversal is being used.

5 and 8, in the two examples described above, the still image stored in the low power mode does not include any gray scale (ie, the stored image is 1 bit / pixel). It is possible to introduce gray scales using the same readout circuit to detect multiple levels. This can be achieved by dividing the read time into several stages and stepping the voltage on the capacitor line 61. During one of these steps, the voltage on the display element 18 of the pixel will exceed the threshold, which may invert the voltage on the column electrode. The point at which reversal occurs depends on the initial voltage on the display element, which consists of a read operation. In this case, additional circuitry is required in the column drive circuit 35 to generate an appropriate voltage to refresh the pixel. An alternative way to achieve gray scale is to subdivide each pixel into a number of {area-ratioed} sub-pixels, where each sub-pixel is driven with either black or maximum luminance.

Although the example described above is applicable to the situation where a capacitor line drive structure is used, the same principle applies to a common column drive structure.

In this case, a third example of the pixel circuit having the same configuration as that of FIG. 4 is shown in FIG. In this circuit, the TFT T2 is constituted by the second switch 58, and the TFTs T3 and T4 are constituted by the drive circuit 55. As shown in FIG. The display element can be an LC display element or a current-driven display element such as an LED.

10 shows a circuit having a plurality of capacitors each storing bits of data, the plurality of bits designating a gray scale level.

The plurality of data storage capacitors 70 are connected to the corresponding plurality of columns 16 through the TFTs 12 connected to the common row address line 14. The auxiliary row electrode 52 controls the readout circuit 51 for each data storage capacitor 70. The pixel drive circuit 72 is schematically represented by a box 72 with an input from each data storage capacitor 70.

When in use, data may be supplied to the data storage capacitor 70 in parallel via column 16. Applying a signal to the auxiliary row electrode 52, the data can be read back up on column 16 so that the data can be subsequently rewritten to refresh the data.

An alternative multi-bit configuration is shown in FIG. 11, which has a plurality of address lines 14 for each row and a single column line 16 for each column. Select line 76 is provided on each row to control select transistor 74 connecting column line 16 to TFT 12 via data line 77.

In use, one of the plurality of address lines 14 is capable of selecting the corresponding data storage capacitor 70. Read line 52 may enable read circuit 51 to read data on selected data storage capacitor 70 onto column line 16. Alternatively, the select line 76 may enable the TFT 74 to select data on the column line 16 to be written to the selected data storage capacitor 70.

An example read circuit 51 connected to the data storage capacitor 70 is illustrated in FIG. 12. The data storage capacitor 70 controls the first TFT 80 which is connected in series to the column 16 via the readout TFT 82. The read TFT 82 is controlled by the read line 52. When the read line 52 switches on the read TFT 82, the data stored on the data storage capacitor 70 is read onto the column 16.                 

  As illustrated above, in addition to the parallel connection of the drive circuit 72 and the data storage capacitor 70, the data on the plurality of data storage capacitors 70 may be transferred by a single data line 84 as illustrated in FIG. 13. It may be connected to the drive circuit 72. In this circuit, data is sequentially transmitted to the driving circuit 72 by addressing the individual TFTs 12 in order to connect the corresponding data storage capacitor 70 with the driving circuit 72.

Another embodiment is illustrated in FIG. 14, which performs series charge redistribution digital / analog conversion using pixel capacitance 18 itself. The characteristics of this circuit are described in more detail in US patents US 5448258 and US5923311, which are incorporated herein by reference. For this purpose, note that the capacitor 70 is connected to the data line 84 through each switch 12 as in FIG. 13, which in turn drives the pixel capacitance 18.

It is possible to simultaneously operate some pixels of the array in a still mode using data stored within the pixels and other pixels using data provided by an external signal source. This can be achieved without the need to drive the display with an appropriate signal and change the pixel circuitry. This approach can minimize power consumption.

For example, part of the display may show a moving picture while the rest of the display shows a still background. The external video source only saves power by supplying data for the image area showing the moving picture on the display.

The present invention is applicable to various kinds of active matrix display devices, and pixel circuits similar to the circuits described above can be used to display still images in, for example, electrochromic, electrophoretic and electroluminescent type display devices. Storage may be used in display devices other than AMLCDs and AMLEDs. Examples of active matrix LED display devices are described in European patent (EP-A-1116205), the contents of which are incorporated herein as background material.

Many other variations and modifications will be apparent to those skilled in the art from this disclosure. Such changes and modifications may include other features that are already known in the art and that may be used in place of or in addition to the features already disclosed herein.

As mentioned above, the present invention relates to an active matrix display device comprising an array of display pixels, and although not particularly exclusively, is applicable to active matrix liquid crystal display devices and active matrix electroluminescent display devices.

Claims (10)

delete delete delete As an active matrix display device, A plurality of pixels arranged as rows and columns; And column electrodes extending along corresponding columns of pixels; Wherein the pixel includes a readout circuit for reading the image data storage capacitance and the state of the image data storage capacitance and for driving the corresponding column electrode in accordance with the read state, The readout circuitry has an input impedance high enough so that the charge stored on the image data storage capacitance is weakly discharged during readout, The active matrix display device comprises a read line and a row electrode extending along a corresponding row of pixels, wherein the pixel connects the corresponding column electrode to the data storage capacitance when a switch is selected by the corresponding row electrode. And the read circuit is controlled by a corresponding read line to read the capacitance onto the corresponding column electrode, And said pixel comprises drive circuitry for driving a pixel display component, said drive circuitry having its input coupled to said image data storage capacitance. 5. The active matrix display device of claim 4, wherein the readout circuit comprises a switch for connecting the drive circuit and the output of the drive circuit to the corresponding column electrode under control of the readout line. As an active matrix display device, A plurality of pixels arranged as rows and columns; And column electrodes extending along corresponding columns of pixels; Wherein the pixel includes a readout circuit for reading the image data storage capacitance and the state of the image data storage capacitance and for driving the corresponding column electrode in accordance with the read state, The readout circuitry has an input impedance high enough so that the charge stored on the image data storage capacitance is weakly discharged during readout, The active matrix display device comprises a read line and a row electrode extending along a corresponding row of pixels, wherein the pixel connects the corresponding column electrode to the data storage capacitance when a switch is selected by the corresponding row electrode. And the read circuit is controlled by a corresponding read line to read the capacitance onto the corresponding column electrode, Wherein each pixel comprises a plurality of image data storage capacitances. 7. The apparatus of claim 6, comprising a plurality of row electrodes along each row, wherein each row electrode selects each switch connecting a respective image data storage capacitor to a data line, the selection line selecting the data on the corresponding column electrode. A switch connecting a line, wherein the readout circuit reads data on the data line onto the corresponding column electrode under control of the readout line. 7. The active matrix display device of claim 6, comprising dedicated readout circuitry coupled to each image data storage capacitor. delete delete

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