JP5386409B2 - Active matrix display device and electronic apparatus having the same - Google Patents

Description

  The present invention relates to an active matrix display device having a plurality of pixels arranged in a matrix of rows and columns, and an electronic apparatus having the active matrix display device.

  In the conventional active matrix display device, data is written to the pixels by the driver in the same manner in any display mode of moving images or still images. In this case, the same data is always written to the pixels while the still image is displayed. Accordingly, it has been proposed to provide a memory for each pixel and to write the data stored in the memory to display the pixel at the time of displaying a still image, thereby stopping the driving of the driver and reducing power consumption. This technology is generally known as MIP (Memory in Pixel) technology.

  In general, in the MIP technique, a dynamic random access memory (DRAM) or a static random access memory (SRAM) is used to hold data stored in the memory of each pixel. While the SRAM is composed of a sequential circuit using transistors, the DRAM is composed of one transistor and one capacitor, so the DRAM is more advantageous in terms of reducing the circuit area and the pixel pitch. However, the DRAM requires a refresh operation in order to hold a minute charge stored in the capacitor. An example of a pixel circuit using DRAM is described in, for example, International Publication No. 2004/090854 (A1) pamphlet (Patent Document 1).

International Publication No. 2004/090854 (A1) Pamphlet

  However, a pixel circuit using a conventional DRAM requires alternating common electrodes for the DRAM self-refresh operation. The common electrode is an electrode common to the entire surface provided on the surface facing the TFT side where the pixel electrode, the source line, and the gate line are provided, and is also referred to as a “counter electrode”. Thus, since the common electrode is an electrode common to the entire surface of the display device, power consumption due to alternating common electrodes becomes a problem.

  In view of this problem, an object of the present invention is to provide an active matrix display device that realizes low power consumption while having a pixel built-in memory circuit, and an electronic apparatus having the active matrix display device.

  In order to achieve the above object, an active matrix display device having a plurality of pixels arranged in a matrix of rows and columns, each of the plurality of pixels having a first terminal and a second terminal. A display element having the second terminal connected to a constant potential; a control switch for controlling supply of image data to the first terminal of the display element; a first terminal and a second terminal; A storage capacitor that holds the image data supplied to the display element via the control switch, the first terminal of the display element being connected to the first terminal of the display element; And a storage circuit that stores a voltage state at a terminal of the storage capacitor, and the display device supplies a voltage that is switched in two or more stages to the second terminal of the storage capacitor in synchronization with a refresh operation of the storage circuit. Supply voltage It comprises means, active matrix display device is provided.

  As described above, since the second terminal of the display element, that is, the common electrode is maintained at a constant potential, low power consumption can be realized while having the pixel built-in memory circuit.

  In a preferred embodiment, the voltage supply means switches the value of the voltage supplied to the second terminal of the storage capacitor to another value at the start and end of the refresh operation. Specifically, the voltage supply means switches the value of the voltage supplied to the second terminal of the storage capacitor between the first voltage value and the second voltage value at the start of the refresh operation, Switching between the second voltage value and the third voltage value at the end of the refresh operation. The second voltage value is larger than the first voltage value and smaller than the third voltage value. In an alternative embodiment, the voltage supply means further includes the memory circuit further comprising: a first terminal of the display element when the voltage supplied to the second terminal of the storage capacitor switches between two values. The voltage value is switched at the end of the sampling period for sampling the voltage state at.

  In a preferred embodiment, the voltage supply means controls the voltage source to generate the voltage to be supplied to the second terminal of the storage capacitor, and to switch the voltage value in two or more stages. And a power supply control unit. In this embodiment, the voltage supply unit may further include a voltage step storage unit that stores a voltage step in which the voltage supplied to the second terminal of the storage capacitor is switched in two or more multistages. The power supply control unit controls the voltage source according to the voltage step.

  In a preferred embodiment, the voltage supply means is connected to the plurality of pixels by a common electrode line, and supplies the voltage to the second terminal of the storage capacitor via the common electrode.

  In a preferred embodiment, the memory circuit may be a DRAM.

  In a preferred embodiment, the active matrix display device may be a liquid crystal display device or an OLED display device.

  In order to achieve the above object, the active matrix display device includes a television receiver, a desktop or laptop personal computer (PC), a mobile phone, a wristwatch, a personal digital assistant (PDA), a desktop PC, The present invention may be applied to other electronic devices such as a car navigation device, a portable game machine, or an aurora vision.

  According to the embodiment of the present invention, it is possible to provide an active matrix display device that realizes low power consumption while having a pixel built-in memory circuit, and an electronic apparatus having the active matrix display device.

1 illustrates a configuration of an active matrix display device according to an embodiment of the present invention. 1 illustrates a configuration of a pixel circuit according to an embodiment of the present invention. 3 is a timing chart illustrating a first example of the operation of the pixel circuit illustrated in FIG. 2. 3 is a timing chart illustrating a second example of the operation of the pixel circuit illustrated in FIG. 2. 2 illustrates a configuration of a voltage supply unit according to an embodiment of the present invention. 1 shows an electronic device according to one embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[Configuration of display device]
FIG. 1 shows a configuration of an active matrix display device according to an embodiment of the present invention. The display device 1 of FIG. 1 includes a display panel 10, a source driver 20, a gate driver 30, a voltage supply unit 40, and a controller 50.

  The display panel 10 includes a plurality of pixels 100 arranged in a matrix of rows and columns. The source driver 20 supplies image data to each of the pixels 100 via data lines (generally called “source lines”) Data_1 to Data_m. The gate driver 30 controls driving of the pixel 100 via a write line (generally also referred to as a “gate line”) Write_1 to Write_n. The voltage supply unit 40 is connected to each of the pixels 100 via the voltage supply lines CS_1 to CS_n, and supplies a predetermined voltage to each pixel according to the driving state of the pixel. The controller 50 synchronizes the source driver 20, the gate driver 30, and the voltage supply unit 40 and controls their operations.

  Each pixel 100 is located in an intersection region of the data line Data_i (1 ≦ i ≦ m) and the write line Write_j (1 ≦ j ≦ n) in the display panel 10, and a display element (for example, a liquid crystal cell, an organic EL, Or at least one storage circuit. In the still image display mode, each pixel operates based on data stored in its own storage circuit instead of image data transmitted via the data line Data_i. Therefore, in the still image display mode, the source driver 20 can be stopped, while the display panel 10 can continuously display still images.

[Pixel circuit configuration]
FIG. 2 illustrates a configuration of a pixel circuit of an active matrix display device according to an embodiment of the present invention. The pixel 100 in FIG. 2 includes a pixel capacitor Cpix having a display element Cl and a storage capacitor Cs, a drive control switch Q11, and a memory circuit 200.

  The display element Cl transmits or emits light when a potential difference occurs between both ends thereof. In FIG. 2, the display element Cl is represented as a capacitive element, but may be a diode such as an OLED. One terminal of the display element Cl is connected to the common electrode COM, and the other terminal is connected to the data line Data_i via the drive control switch Q11. The terminal on the side connected to the data line Data_i of the display element Cl is generally called a “pixel electrode”.

  The drive control switch Q11 has its control terminal connected to the write line Write_j, and is turned on or off according to the potential of the write line Write_j. When the drive control switch Q11 is turned on, data on the data line Data_i is written into the display element Cl. At this time, when it is a liquid crystal cell, the display element Cl can transmit light by changing the orientation of liquid crystal molecules due to a potential difference between the pixel electrode and the common electrode.

  The storage capacitor Cs has a first terminal connected to the pixel electrode and a second terminal connected to the voltage supply line CS_j connected to the voltage supply unit 40 (FIG. 1). In this example, a storage capacitor (CS) line to which the second terminal of the storage capacitor Cs is connected in the conventional pixel circuit is used as the voltage supply line. The CS line does not necessarily need to be independent for each row, and can be shared for rows that simultaneously perform a self-refresh operation. As a matter of course, the voltage supply line may be provided as a dedicated line separately from the CS line.

  The memory circuit 200 includes first, second, and third transistors Q12, Q13, and Q14, and a sampling capacitor C11. The sampling capacitor C11 has a first terminal connected to the data line Data_i, and a second terminal connected to the pixel electrode via the first transistor Q12. The control terminal of the first transistor Q12 is connected to the sampling line Sample_j. The second transistor Q13 and the third transistor Q14 are connected in series and disposed between the pixel electrode and the data line Data_i. The control terminal of the second transistor Q13 is connected to the second terminal of the sampling capacitor C11. The control terminal of the third transistor Q14 is connected to the refresh line Refresh_j. Thus, in this example, the memory circuit 200 is configured as a DRAM.

  Here, it is assumed that the display device according to the present embodiment is a normally black liquid crystal display. With respect to such a device, the self-refresh operation of the pixel circuit shown in FIG. 2 will be described below by taking inversion driving at the time of white display as an example.

[Example 1 of self-refresh operation]
FIG. 3 is a timing chart showing a first example of the self-refresh operation of the pixel circuit shown in FIG. The common electrode COM is separated from the CS line CS_j and is always at a constant voltage V _COM (hereinafter referred to as “common voltage”). In the initial state (˜t ₁₁ ), the CS line CS_j as the voltage supply line is supplied with the first predetermined voltage Vcs1 by the voltage supply unit 40, and is referred to as a voltage at the pixel electrode (hereinafter referred to as “pixel voltage”). ) Vpix is to take the lowest voltage of _{-V ML} with respect to the common voltage _{V COM.} At this time, the drive control switch Q11 and the first, second, and third transistors Q12, Q13, and Q14 are off.

First, during the sampling period Ts from time t ₁₁ to t ₁₂ , the sampling line Sample_j is driven to a high potential state by the controller 50 so that the voltage Vpix at the pixel electrode is sampled by the memory circuit 200. As a result, the first transistor Q12 is turned on, and the second terminal of the sampling capacitor C11 is connected to the pixel electrode. During this period Ts, the data line Data_i is in the low potential state, and the sampling capacitor C11 holds the sampling voltage Vs substantially equal to the pixel voltage Vpix.

Also, during this period Ts, the second predetermined voltage Vcs2 (Vcs2> Vcs1) is supplied to the CS line CS_j by the voltage supply unit 40. Thus, the pixel voltage Vpix is increased by capacitive coupling between the storage capacitor Cs and the display device Cl by ΔV = (Vcs2-Vcs1) × Cs / (Cs + Cl), -V with respect to the common voltage _{V COM} L (= −V _ML + ΔV; | V _ML |> | V _L |). After the sampling period Ts, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is returned to the first voltage Vcs1 at the start of the subsequent precharge period Tpc.

During the precharge period Tpc from time t ₁₂ to t _13, the data voltage V _H supplied by the source driver 20 appears on the data line Data_i. The write line Write_j is driven to a high potential state by the gate driver 30 so that data is written to the display element Cl. As a result, the drive control switch Q11 is turned on, and the pixel electrode is connected to the data line Data_i. Thus, the pixel voltage Vpix is equal to the data voltage _{V H} on the data line DATA_I. Thereafter, at the end of the precharge period Tpc, the data line Data_i is returned to the low potential state (= −V _L ) again.

Between subsequent time _{t 13} the refresh period Tr of _{t 14,} the refresh line Refresh_j the storage circuit 200 is driven to a high potential state by the controller 50 to be refreshed. Accordingly, the third transistor Q14 is turned on, and the conductive terminal of the second transistor Q13 is connected to the data line Data_i to be in a low potential state. On the other hand, the sampling voltage Vs held in the sampling capacitor C11 in the sampling period Ts appears at the control terminal of the second transistor Q13. However, since the sampling voltage Vs is −V _L with respect to the common voltage V _COM , there is a sufficient potential difference between the conductive terminal and the control terminal of the second transistor Q13 to turn on the second transistor Q13. It does not occur and the second transistor Q13 remains off.

After the end of the refresh period Tr, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is raised again to the second voltage Vcs2. Accordingly, the pixel voltage Vpix is increased by ΔV = (Vcs2−Vcs1) × Cs / (Cs + Cl) due to capacitive coupling between the display element Cl and the storage capacitor Cs, and V _MH (= V with respect to the common voltage V _COM ). _H + ΔV; V _MH > V _H ).

Thus, when the series of self-refresh operation is terminated, the voltage Vpix of the pixel electrode is inverted from an initial state the common voltage V _COM as the intermediate potential.

  Next, the case where the next self-refresh operation is started in this state will be described.

During the sampling period Ts from time t ₂₁ to t ₂₂ , the sampling line Sample_j is driven to a high potential state by the controller 50 so that the voltage Vpix at the pixel electrode is sampled by the memory circuit 200. As a result, the first transistor Q12 is turned on, and the second terminal of the sampling capacitor C11 is connected to the pixel electrode. During this period Ts, the data line Data_i is in the low potential state, and the sampling capacitor C11 holds the sampling voltage Vs equal to the pixel voltage Vpix.

Further, during this period Ts, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is lowered to the first voltage Vcs1. Thus, the pixel voltage Vpix is lowered by [Delta] V = the capacitive coupling between the storage capacitor Cs and the display element Cl (Vcs2-Vcs1) × Cs / (Cs + Cl), the _{V H} with respect to the common voltage _{V COM.} After the sampling period Ts, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is returned to the second voltage Vcs2 at the start of the subsequent precharge period Tpc.

Between the time _{t 22} of the precharge period Tpc of _{t 23,} the data line DATA_I, the data voltage _{V H} to be supplied by the source driver 20 appears. The write line Write_j is driven to a high potential state by the gate driver 30 so that data is written to the display element Cl. As a result, the drive control switch Q11 is turned on, and the pixel electrode is connected to the data line Data_i. Thus, the pixel voltage Vpix is equal to the data voltage _{V H} on the data line DATA_I. Thereafter, at the end of the precharge period Tpc, the data line Data_i is returned to the low potential state (= −V _L ) again.

Between subsequent time _{t 23} the refresh period Tr of _{t 24,} the refresh line Refresh_j the storage circuit 200 is driven to a high potential state by the controller 50 to be refreshed. Accordingly, the third transistor Q14 is turned on, and the conductive terminal of the second transistor Q13 is connected to the data line Data_i to be in a low potential state. On the other hand, the sampling voltage Vs held in the sampling capacitor C11 in the sampling period Ts appears at the control terminal of the second transistor Q13. Since the sampling voltage Vs is _{V H} with respect to the common voltage _{V COM,} the second transistor Q13 is turned on by the potential difference between the conductive terminal and the control terminal, the pixel electrode and the second and third transistors Q13 and Q14 To the data line Data_i. As a result, the pixel voltage Vpix becomes equal to the voltage −V _{L on the} data line Data_i.

After the end of the refresh period Tr, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is again lowered to the first voltage Vcs1. Thus, the pixel voltage Vpix is lowered by [Delta] V = the capacitive coupling between the storage capacitor Cs and the display element Cl (Vcs2-Vcs1) × Cs / (Cs + Cl), the lowest _{-V ML} with respect to the common voltage _{V COM} Take the voltage.

  Thus, when a series of self-refresh operations are completed, the voltage Vpix at the pixel electrode is inverted again with respect to the common electrode COM and returns to the initial state.

[Example 2 of self-refresh operation]
FIG. 4 is a timing chart showing a second example of the self-refresh operation of the pixel circuit shown in FIG. Like the first embodiment described with reference to FIG. 3, the common electrode COM is separated from the CS line CS_j, always to be in a constant common voltage V _COM. Further, in the initial state _{(~t 11),} CS line CS_j as the voltage supply line is supplied to the first predetermined voltage Vcs1 by the voltage supply unit 40, the pixel voltage Vpix is -V with respect to the common voltage _{V COM} The minimum voltage of _ML is taken, and the drive control switch Q11 and the first, second and third transistors Q12, Q13 and Q14 are turned off.

First, during the sampling period Ts from time t ₁₁ to t ₁₂ , the sampling line Sample_j is driven to a high potential state by the controller 50 so that the voltage Vpix at the pixel electrode is sampled by the memory circuit 200. As a result, the first transistor Q12 is turned on, and the second terminal of the sampling capacitor C11 is connected to the pixel electrode. During this period Ts, the data line Data_i is in the low potential state, and the sampling capacitor C11 holds the sampling voltage Vs substantially equal to the pixel voltage Vpix.

Also, during this period Ts, the second predetermined voltage Vcs2 (Vcs2> Vcs1) is supplied to the CS line CS_j by the voltage supply unit 40. Thus, the pixel voltage Vpix is increased by capacitive coupling between the storage capacitor Cs and the display device Cl by ΔV = (Vcs2-Vcs1) × Cs / (Cs + Cl), -V with respect to the common voltage _{V COM} L (= −V _ML + ΔV; | V _ML |> | V _L |). Here, unlike the first example, the voltage supplied to the CS line CS_j by the voltage supply unit 40 does not return to the first voltage Vcs1 after the sampling period Ts, and the second voltage continues to the CS line CS_j. Voltage Vcs2 is supplied.

During the precharge period Tpc from time t ₁₂ to t _13, the data voltage V _H supplied by the source driver 20 appears on the data line Data_i. The write line Write_j is driven to a high potential state by the gate driver 30 so that data is written to the display element Cl. As a result, the drive control switch Q11 is turned on, and the pixel electrode is connected to the data line Data_i. Thus, the pixel voltage Vpix is equal to the data voltage _{V H} on the data line DATA_I. Thereafter, at the end of the precharge period Tpc, the data line Data_i is returned to the low potential state (= −V _L ) again.

Between subsequent time _{t 13} the refresh period Tr of _{t 14,} the refresh line Refresh_j the storage circuit 200 is driven to a high potential state by the controller 50 to be refreshed. Accordingly, the third transistor Q14 is turned on, and the conductive terminal of the second transistor Q13 is connected to the data line Data_i to be in a low potential state. On the other hand, the sampling voltage Vs held in the sampling capacitor C11 in the sampling period Ts appears at the control terminal of the second transistor Q13. However, since the sampling voltage Vs is −V _L with respect to the common voltage V _COM , there is a sufficient potential difference between the conductive terminal and the control terminal of the second transistor Q13 to turn on the second transistor Q13. It does not occur and the second transistor Q13 remains off.

After the end of the refresh period Tr, the third predetermined voltage Vcs3 (Vcs3> Vcs2) is supplied to the CS line CS_j by the voltage supply unit 40. Accordingly, the pixel voltage Vpix is increased by ΔV = (Vcs3−Vcs2) × Cs / (Cs + Cl) due to capacitive coupling between the display element Cl and the storage capacitor Cs, and V _MH (= V with respect to the common voltage V _COM ). _H + ΔV; V _MH > V _H ).

Thus, as in the first embodiment, when the series of self-refresh operation is terminated, the voltage Vpix of the pixel electrode is inverted from an initial state the common voltage V _COM as the intermediate potential.

  Next, the case where the next self-refresh operation is started in this state will be described.

During the sampling period Ts from time t ₂₁ to t ₂₂ , the sampling line Sample_j is driven to a high potential state by the controller 50 so that the voltage Vpix at the pixel electrode is sampled by the memory circuit 200. As a result, the first transistor Q12 is turned on, and the second terminal of the sampling capacitor C11 is connected to the pixel electrode. During this period Ts, the data line Data_i is in the low potential state, and the sampling capacitor C11 holds the sampling voltage Vs equal to the pixel voltage Vpix.

Further, during this period Ts, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is lowered to the second voltage Vcs2. Thus, the pixel voltage Vpix is lowered by [Delta] V = the capacitive coupling between the storage capacitor Cs and the display element Cl (Vcs3-Vcs2) × Cs / (Cs + Cl), the _{V H} with respect to the common voltage _{V COM.} The voltage supply unit 40 continues to supply the second voltage Vcs2 to the CS line CS_j after the sampling period Ts.

Between the time _{t 22} of the precharge period Tpc of _{t 23,} the data line DATA_I, the data voltage _{V H} to be supplied by the source driver 20 appears. The write line Write_j is driven to a high potential state by the gate driver 30 so that data is written to the display element Cl. As a result, the drive control switch Q11 is turned on, and the pixel electrode is connected to the data line Data_i. Thus, the pixel voltage Vpix is equal to the data voltage _{V H} on the data line DATA_I. Thereafter, at the end of the precharge period Tpc, the data line Data_i is returned to the low potential state (= −V _L ) again.

Between subsequent time _{t 23} the refresh period Tr of _{t 24,} the refresh line Refresh_j the storage circuit 200 is driven to a high potential state by the controller 50 to be refreshed. Accordingly, the third transistor Q14 is turned on, and the conductive terminal of the second transistor Q13 is connected to the data line Data_i to be in a low potential state. On the other hand, the sampling voltage Vs held in the sampling capacitor C11 in the sampling period Ts appears at the control terminal of the second transistor Q13. Since the sampling voltage Vs is _{V H} with respect to the common voltage _{V COM,} the second transistor Q13 is turned on by the potential difference between the conductive terminal and the control terminal, the pixel electrode and the second and third transistors Q13 and Q14 To the data line Data_i. As a result, the pixel voltage Vpix becomes equal to the voltage −V _{L on the} data line Data_i.

After the refresh period Tr ends, the voltage supplied to the CS line CS_j by the voltage supply unit 40 is lowered to the first voltage Vcs1. Thus, the pixel voltage Vpix is lowered by [Delta] V = the capacitive coupling between the storage capacitor Cs and the display element Cl (Vcs2-Vcs1) × Cs / (Cs + Cl), the lowest _{-V ML} with respect to the common voltage _{V COM} Take the voltage.

  Thus, as in the first example, when a series of self-refresh operations are completed, the voltage Vpix at the pixel electrode is inverted again with respect to the common electrode COM and returns to the initial state.

  The operation of this example is that the voltage of the CS line CS_j is switched between three levels of Vcs1, Vcs2, and Vcs3, while in the first example, it is switched between two levels of Vcs1 and Vcs2. This is different from the operation of the first example. The operation of this example has a more complicated circuit configuration than the operation of the first example, but the frequency of switching the potential of the CS line CS_j is less frequent, and an advantage that a more stable operation is ensured as a whole circuit. Have

[Configuration of voltage supply unit]
Next, the configuration of the voltage supply unit 40 for realizing the operation described with reference to FIGS. 3 and 4 will be described.

  FIG. 5 is a block diagram showing a configuration of voltage supply unit 40 according to an embodiment of the present invention. The voltage supply unit 40 in FIG. 5 controls the power supply 42 according to a control signal from the controller 50 and a power supply 42 that generates a predetermined voltage supplied to each pixel via each of the voltage supply lines CS_1 to CS_n. The power supply control unit 44 and a voltage step storage unit 46 that stores pre-programmed voltage steps are included.

  The power source 42 is a variable voltage source that can switch the supply voltage in two or more stages. The power supply control unit 44 receives a control signal instructing to supply a predetermined voltage to each pixel during the self-refresh operation of the pixel built-in storage circuit 200 from the controller 50, and is programmed in advance in the voltage step storage unit 46. The supply voltage of the power source 42 is switched according to the voltage step. The voltage step can be determined at the time of manufacturing the display device 10 according to the application and environment in which the display device 10 is used, and consequently the performance required for the display device 10.

  Alternatively, the voltage step storage unit 46 may not be provided. When the potential of the voltage supply line CS_j is switched between two levels as described with reference to FIG. 3, the power supply controller 44 responds to a control signal from the controller 50 to The supply voltage may be switched between two levels. In this case, the voltage step storage unit 46 is not necessarily used.

  Alternatively, the voltage step storage unit 46 may be provided in the controller 50 instead of the voltage supply unit 40. In this case, the controller 50 supplies a control signal corresponding to the voltage step stored in the voltage step storage unit 46 to the power supply control unit 44, and the power supply unit 44 responds to the control signal with the power supply 42. Switch the supply voltage.

  As described above, the active matrix display device according to one embodiment of the present invention separates the common electrode COM from the CS line CS_j, and uses the CS line CS_j as a power supply line, so that the storage capacitor has two or more stages. By supplying the voltage for switching to, the refresh operation of the pixel built-in memory circuit can be performed while keeping the potential of the common electrode COM constant. As a result, the power consumption can be reduced as compared with the conventional device that requires the alternating common electrode COM for the refresh operation of the pixel built-in memory circuit.

[Application example of display device]
FIG. 6 is an example of an electronic device having an active matrix display device according to an embodiment of the present invention. 6 is represented as a laptop personal computer (PC), for example, a television receiver, a mobile phone, a wristwatch, a personal digital assistant (PDA), a desktop PC, a car navigation device, It may be a portable game machine or other electronic equipment such as Aurora Vision.

  The electronic device 300 includes the display device 1 including the display panel 10 that can display an image or the like. The display device 1 is a display device described with reference to FIGS. 1 to 5 and can suppress power consumption by using a pixel built-in memory circuit when displaying a still image. It is useful for battery-powered portable devices such as PDAs, portable audio players, and portable game machines, and electronic devices such as monitors that display advertisements such as posters.

  In addition, since the display device 1 can perform the refresh operation of the pixel-embedded memory circuit while keeping the potential of the common electrode COM constant, it is particularly applied to an electronic device having a capacitive touch panel. Useful for. The electrostatic capacity method is to provide an electrostatic sensor on the entire surface of the display panel, and identify a contact position of the object by detecting a change in electric charge due to a discharge phenomenon that occurs when an object approaches the display panel surface. . This system is not only excellent in durability and transparency, but also enables multi-touch, and is expected to be increasingly demanded in the future. However, conventionally, in a display device having a memory circuit with a built-in pixel, a touch panel is disposed immediately above the surface on which the common electrode COM is provided, so that the electrostatic sensor is influenced by the alternating common electrode COM. There was a possibility that malfunction occurred on the touch panel. On the other hand, when the display device 1 according to the embodiment of the present invention is used, such a problem does not occur because the potential of the common electrode COM is always constant.

  Although the best mode for carrying out the invention has been described above, the present invention is not limited to the embodiment described in the best mode. Modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Active matrix type display apparatus 10 Display panel 20 Source driver 30 Gate driver 40 Voltage supply part 42 Power supply 44 Power supply control part 46 Voltage step memory | storage part 50 Controller 100 Pixel 200 Memory circuit 300 Electronic device C11 Sampling capacitor Cl Display element Cpix Pixel capacity Cs Retention capacity CS_j Power supply line (CS line)
Q11 Drive control switch V _COM common voltage Vpix Pixel voltage

Claims (9)

An active matrix display device having a plurality of pixels arranged in a matrix of rows and columns,
Each of the plurality of pixels is
A display element having a first terminal and a second terminal, the second terminal being connected to a constant potential;
A control switch for controlling supply of image data to the first terminal of the display element;
A first terminal and a second terminal, the first terminal being connected to the first terminal of the display element and holding the image data supplied to the display element via the control switch Holding capacity,
A storage circuit having at least one transistor and a sampling capacitor and storing a voltage state at a first terminal of the display element;
The pixel includes a sampling period for sampling a voltage state in the memory circuit , a precharge period for writing the image data to the display element after the end of the sampling period, and a memory circuit after the precharge period ends. A refresh operation having a self- refresh period for inverting the voltage state of
The display device includes voltage supply means for supplying a voltage that switches between two or more multi-stages to the second terminal of the storage capacitor,
The voltage supply means switches the value of the voltage supplied to the second terminal of the storage capacitor to another value at least at the start of the sampling period and at the end of the self- refresh period. apparatus. The voltage supply means changes the value of the voltage supplied to the second terminal of the storage capacitor from the first voltage value to the second voltage value or from the third voltage value at the start of the sampling period. Switching to a voltage value of 2, and switching from the second voltage value to the third voltage value or from the second voltage value to the first voltage value at the end of the refresh period,
The active matrix display device according to claim 1, wherein the second voltage value is larger than the first voltage value and smaller than the third voltage value.   The voltage supply means further switches the value of the voltage at the end of the sampling period when the voltage supplied to the second terminal of the storage capacitor switches between two values. Active matrix display device. The voltage supply means includes
A voltage source for generating the voltage to be supplied to the second terminal of the storage capacitor;
4. The active matrix display device according to claim 1, further comprising: a power supply control unit that controls the voltage source so that the voltage value is switched in two or more multistages. 5. The voltage supply unit further includes a voltage step storage unit that stores a voltage step in which the voltage supplied to the second terminal of the storage capacitor is switched in two or more multistages,
The active matrix display device according to claim 4, wherein the power control unit controls the voltage source according to the voltage step.   The voltage supply means is connected to the plurality of pixels by a common electrode line, and supplies the voltage to the second terminal of the storage capacitor via the common electrode. The active matrix display device described.   The active matrix display device according to claim 1, wherein the memory circuit is a DRAM.   The active matrix display device according to any one of claims 1 to 7, which is a liquid crystal display device or an OLED display device.   An electronic apparatus comprising the active matrix display device according to claim 1.

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