JPH11282550A - Constant voltage control circuit, semiconductor device and portable electronic device containing the circuit and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the stop of operation of an operation circuit that is caused by the variance of the constant voltage level and to less reduce power consumption by performing the change control of the 1st voltage to prevent this voltage from reaching the operation stop voltage level of the operation circuit when it's detected that the 2nd voltage is equal to the operation stop voltage level of a monitor means. SOLUTION: The voltage Vregm drops in response to the gradual drop of the voltage Vreg that is caused by the temperature variance, etc. As the voltage Vregm is lower than the voltage Vreg, an operation monitor circuit 30 reaches its stop voltage level before the voltage Vreg reaches the operation stop voltage level of a crystal oscillation circuit. When the circuit 30 stops its operation, an operation stop signal is outputted to a constant voltage generation circuit 10 via a differentiation circuit 50 and an up-down counter 60 to make a decoder 70 set its output line at an H level. Thus, the voltage Vreg outputted from the circuit 10 rises up by one step. Then the voltage Vreg is controlled and settled down to its steady state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a constant voltage control circuit,
The present invention relates to a semiconductor device and a portable electronic device including the same, and more particularly to a timepiece IC including a constant voltage control circuit for controlling a constant voltage supplied to an oscillation circuit.

[0002]

2. Description of the Related Art A constant voltage circuit of this type includes, for example, a circuit shown in FIG. FIG. 18 shows an example of a general crystal oscillation circuit 410 and a constant voltage generation circuit 400.

[0005] The crystal oscillation circuit 410 includes a crystal oscillator X′t.
a, an oscillation inverter INV100, and a high resistance Rf forming a feedback circuit. The feedback circuit includes, in addition to the resistor Rf, capacitors C _D and C _G for phase compensation, and the oscillation inverter INV 1
The drain output 00 is fed back to the gate of the oscillation inverter INV100 as a gate input whose phase is inverted by 180 degrees.

The oscillation inverter INV100 includes a pair of P-type field effect transistors (hereinafter referred to as PMOS) QP1.
00, N-type field effect transistor (hereinafter referred to as NMOS) QN100, and each PMOS QP100, NMOS QN
It is configured such that 100 gates function as an input side and a drain functions as an output side. And each transistor QP
100 and QN100 have their drains connected to each other, and their sources connected to the ground voltage Vdd side and the negative constant voltage Vreg side, respectively.

In the crystal oscillation circuit 410, when a constant voltage Vreg is applied to the oscillation inverter INV100, the output of the oscillation inverter INV100 is inverted by 180 degrees and fed back to the gate. This allows
PMOS QP1 constituting the oscillation inverter INV100
00 and the NMOS QN 100 are alternately turned on and off, the oscillation output of the crystal oscillation circuit 410 gradually increases, and the crystal oscillator X′tal performs a stable oscillation operation.

In this crystal oscillation circuit, the absolute value | Vsto | of the oscillation stop voltage is obtained by setting the threshold voltage of the NMOS QN100 to Vthn.
0, assuming that the threshold voltage of the PMOS QP100 is Vthp0,
Equation 1 can be expressed.

| Vsto | = K · (| Vthp0 | + Vthn0) Here, the constant K is 0.8 to 0.9, and | Vthp0 | indicates an absolute value of Vthp0. Thus, the oscillation stop voltage Vs
to depends on the threshold voltage Vthn0 of the NMOS and the threshold voltage Vthp0 of the PMOS.

On the other hand, the constant voltage generating circuit 400 includes an operational amplifier OP100, a control PMOS QP101 of a minus (hereinafter referred to as-) input terminal, a control NMOS QN101 of a plus (hereinafter referred to as +) input terminal, and an output NMOS QN101.
102.

The operation of this circuit will be described. When a constant current flows through the control PMOS QP 101, the signal line 4
01, a voltage α | Vthp1 | (α: constant) dependent on the threshold voltage | Vthp1 | of the control PMOS QP101 is generated. The signal line 402 is connected to the same potential α | as the signal line 401 by the operational amplifier OP100 and the output NMOS QN102.
Vthp1 |. Furthermore, the control NMOS QN1
01 flows from the constant current source TN to the control NMOS QN between the signal line 402 and the output line 403.
A potential difference of αVthn1 depending on the threshold voltage Vthn1 of 101 is generated. Therefore, between the output line 403 and the ground potential Vdd, a constant voltage α (| Vtn) depending on | Vthp1 | + Vthn1
hp1 | + Vthn1).

Therefore, the output voltage Vreg of the constant voltage generation circuit 400 is equal to the threshold voltage Vthp1 of the control PMOS QP101.
And the threshold voltage Vthn1 of the control NMOS QN101. That is, the constant voltage | Vreg | is | Vthp1 | + Vt
Crystal oscillation circuit 410 which is proportional to hn1 and is an operation circuit
Is supplied with a constant voltage Vreg depending on | Vthp1 | + Vthn1.

Conventionally, in order to reduce the power consumption of the oscillation circuit, a constant current source T for operating a constant voltage generation circuit is conventionally used.
The current values of N and TP have been reduced as much as possible within a range where the constant voltage generation circuit can operate. Therefore, in order to reduce the power consumption of the oscillation inverter, ensure the oscillation operation (|
Vreg |> | Vsto |), and it is necessary to lower the constant voltage | Vreg | as much as possible.

However, when the constant current from the constant current source for operating the constant voltage generating circuit is reduced, there arises a problem that the amount of change in the constant voltage Vreg increases when the constant current fluctuates due to a temperature change. .

Here, the current values of the constant current sources TN and TP for operating the control NMOS QN101 and the control PMOS QP101 have temperature dependence. That is, the constant current sources TN, TP
For example, as shown in FIG. 17, when a depletion type PMOS (DPMOS) is used, the drain current (constant current) ID fluctuates due to a temperature change.

The amount of change in the constant voltage Vreg with respect to a temperature change includes the amount of change in the constant current value ID and the control NMOS QN1.
The sum of the absolute value of the threshold voltage Vthp1 of the control PMOS QP101 and the amount of change in the absolute value of the threshold voltage Vthp1 of the control PMOS QP101.
Regarding the variation of the oscillation stop voltage Vsto with respect to the temperature,
Since the oscillation stop voltage Vsto depends on the above equation 1, NM
This is the change in the threshold voltage of OSQN100 and PMOSQP100. Here, the temperature coefficient of the constant voltage Vreg is expressed by the constant current source T
The amount of change in the constant current at N and TP and the threshold voltage (| Vthp
1 | + Vthn1) and depends on the amount of change, and the oscillation stop voltage Vsto
Is dependent on the variation of the threshold voltage (| Vthp0 | + Vthn0).

As an example, when the constant voltage | Vreg | has a larger negative gradient with respect to temperature in absolute value, the constant voltage | Vreg |
FIG. 19 shows the relationship between | and the oscillation stop voltage | Vsto | between temperature and voltage.

FIG. 19 is a graph showing the constant voltage Vreg and the oscillation stop voltage Vsto with the horizontal axis representing temperature and the vertical axis representing voltage. To ensure the oscillation operation, | Vreg |> | Vsto | must be ensured even at a high temperature (point A shown in FIG. 19) in the operation guarantee temperature range. Here, the operation assurance temperature range is generally from −10 ° C. to 60 ° C., and the point A is a heat-resistant temperature of a wristwatch or the like.

Therefore, in other low temperature regions, the constant voltage |
Vreg | must be made higher than necessary. That is, conventionally, the difference in temperature gradient between the constant voltage Vreg and the oscillation stop voltage Vsto becomes large, and | Vreg |> | Vsto | must always be satisfied in order to guarantee the oscillation operation on the high temperature side (or low temperature side). On the low (or high) side,
Since Vreg | had to be set higher than the guarantee of the oscillation operation, wasteful power was consumed as a result.

Therefore, the constant voltage Vreg and the oscillation stop voltage Vs
constant voltage while maintaining the relation of | Vreg |> | Vsto |
It is difficult to make | Vreg | as low as possible, and it was not possible to further reduce the power consumption of the oscillation circuit.

The conventional constant voltage Vreg is the absolute value | Vthp1 | of the threshold voltage of the control PMOS QP1 in FIG.
By changing the sizes and thresholds of the NMOS and the PMOS, such as lowering the threshold voltage Vthn1 of the control NMOS QN1, respectively, two or three types may be produced and selected and used on a test pad of the IC.

However, even in this case, the constant voltage Vreg Is the PMO
Since the threshold voltages Vthp1 and Vthn1 vary depending on the threshold values of the SQP101 and the NMOS QN101 in the semiconductor manufacturing process, | Vthp1 | or Vthn1
Fluctuates and Vreg during mass production of IC There is a problem that the value of fluctuates greatly.

The adjustment of the constant voltage Vreg by the threshold voltage is limited to 0.1 V in terms of process capability. If the constant voltage Vreg is changed depending on the threshold voltage by this adjustment, the adjustment of the oscillation inverter INV100 is performed. Short current I
There was a problem that the value of s changed significantly.

Furthermore, since low-voltage specifications are becoming mainstream in the semiconductor device from the viewpoint of low power consumption, constant voltage generation circuits used together with oscillation circuits and semiconductor devices equipped with these are also required. Since a minute change in the power greatly affects the oscillation operation, a constant voltage generation circuit capable of finely adjusting the constant voltage supplied to the oscillation circuit has been particularly required.

The present invention has been made in order to solve the above-mentioned technical problems, and has as its object the following:
The constant voltage V which depends on the variation of the threshold value and the temperature characteristic in manufacturing the NMOS and the PMOS in the constant voltage generating circuit.
Even if reg fluctuates, the operation of the operation circuit due to the fluctuation of the constant voltage is prevented, and the fine adjustment of the constant voltage Vreg enables a further reduction in power consumption. Provided is a portable electronic device provided with the electronic device.

[0024]

According to a first aspect of the present invention, a constant voltage control circuit is connected to an operation circuit that operates at a constant voltage, and varies so as not to reach an operation stop voltage of the operation circuit. A constant voltage control circuit for controlling the constant voltage, wherein at least one first
And a second voltage that fluctuates with the first voltage and that is lower than the absolute value of the first voltage. The constant voltage generator generates and outputs a constant voltage, and a monitor that monitors the fluctuation of the second voltage. Means, when the monitor means detects that the second voltage has reached an operation stop voltage of the monitor means,
Control means for changing and controlling the first voltage of the constant voltage generation means so that the first voltage does not reach the operation stop voltage of the operation circuit.

According to the first aspect of the present invention, since the second potential is lower than the absolute value of the first potential, the fluctuation of the second voltage is monitored by the monitoring means, and the first voltage operates. When the voltage drops to near the operation stop voltage of the circuit, the second voltage reaches the operation stop voltage of the monitor before the first voltage reaches the operation stop voltage of the operation circuit. Therefore, it is possible to prevent the first voltage from reaching the operation stop voltage and stop the operation circuit, and to operate at the lowest constant voltage while guaranteeing the operation of the operation circuit, thereby achieving ultra-low power consumption.

A constant voltage control circuit according to a second aspect of the present invention is a constant voltage control circuit connected to an operation circuit that operates at a constant voltage and controls the fluctuating constant voltage, and is supplied to the operation circuit. Constant voltage generating means for generating and outputting a first voltage to be output, monitoring means for monitoring the first voltage,
Control means for changing and controlling the first voltage of the constant voltage generating means based on the detection result of the monitoring means,
The monitor means is configured to stop operation before the operation circuit stops.

According to the second aspect of the present invention, even if the first voltage is supplied to the monitoring means and the operation circuit, the operation of the monitoring means can be stopped before the operation circuit stops. Therefore,
Since the change of the first voltage by the control means is also performed before the operation circuit stops operating, the lowest voltage can be set as a constant voltage within a range higher than the operation stop voltage, contributing to lower power consumption. it can.

According to a third aspect of the present invention, in the constant voltage control circuit according to the second aspect, the operation circuit has a first transistor, and the monitor means sets the absolute value of the threshold value of the first transistor. A second transistor having a threshold absolute value higher than the threshold value.

According to the third aspect of the present invention, a transistor having a higher threshold value is more likely to stop at a lower voltage. here,
The absolute value of the threshold value of the first transistor of the operation circuit is set higher than the absolute value of the threshold value of the second transistor of the monitor. For this reason, the operation of the monitor means stops before the operation circuit stops, and the lowest voltage can be set to a constant voltage within a range higher than the operation stop voltage, which can contribute to lower power consumption.

According to a fourth aspect of the present invention, in the constant voltage control circuit according to the second aspect, the operation circuit has a first transistor, and the monitor means has a current amplification factor of the first transistor. A second transistor having a smaller current amplification factor.

According to the fourth aspect of the invention, a transistor having a small current amplification rate is easily stopped quickly. Here, the current amplification factor of the first transistor of the operation circuit is smaller than the current amplification factor of the second transistor of the monitoring means. For this reason, even if the same first voltage is applied, the operation of the monitor means is stopped before the operation circuit is stopped because the current amplification factor of the monitor means is low. The voltage can be a constant voltage,
It can contribute to lower power consumption.

According to a fifth aspect of the present invention, in the constant voltage control circuit according to the second aspect, the monitor means includes a logic element having more input stages than logic elements formed in the operation circuit. And

According to the fifth aspect of the present invention, a logic element having a larger number of input stages is more likely to stop earlier even at the same voltage.
For this reason, even if the same first voltage is input to the monitor means and the operation circuit, the operation of the monitor means is stopped before the operation circuit is stopped because the monitor means includes a logic element having a larger number of input stages. The lowest voltage can be a constant voltage within a range higher than the stop and operation stop voltage, which can contribute to lower power consumption.

According to a sixth aspect of the present invention, in the constant voltage control circuit according to the first aspect, the monitor means stops operating when the operation is stopped based on a reference signal and the second voltage being monitored. A monitor circuit for outputting a signal is provided.

According to the present invention, when the second voltage reaches the operation stop voltage, the operation stop signal is output, whereby the operation stop of the monitor circuit can be detected.

According to a seventh aspect of the present invention, in the constant voltage control circuit according to any one of the second to fifth aspects, the monitor means is based on a reference signal and the first voltage being monitored. A monitor circuit for outputting an operation stop signal when the operation is stopped.

According to the present invention, when the first voltage reaches the operation stop voltage, the operation stop signal is output to detect the operation stop of the monitor circuit.

According to a eighth aspect of the present invention, in the constant voltage control circuit according to the sixth aspect of the present invention, the control means may include at least one of the first and second control circuits based on the operation stop signal output from the monitor circuit. First pulse generation means for outputting a pulse, second pulse generation means for generating a second pulse having a predetermined period, and the first voltage based on one shot of the first pulse Pulse control means for outputting a signal for increasing the voltage to the constant voltage generating means, and outputting a signal for sequentially decreasing the first voltage to the constant voltage generating means based on the second pulse having a constant period. And having
The method is characterized in that the first voltage is controlled so as to sequentially decrease in a fixed cycle and to increase by stopping the operation of the monitor circuit.

According to the eighth aspect of the present invention, monitoring is performed so as to follow the temperature fluctuation, and once the temperature is reduced to a certain value, monitoring for the temperature fluctuation is performed. Thus, the first voltage is set so as to supply the highest constant voltage when the power is turned on, and during the normal operation, the first voltage is sequentially lowered by the second pulse generating means at a constant cycle, and the operation stop signal of the monitor means is turned off. Can be set by the pulse control means so as to be raised by the first pulse generation means. Therefore, it is possible to secure the lowest voltage as close as possible to the operation stop voltage while guaranteeing the operation so as not to reach the operation stop voltage. Therefore, even in an operation circuit to which a constant voltage is supplied, the lowest constant voltage can be selected while satisfying the operation guarantee with respect to the constant voltage and the operation oscillation stop voltage. Can operate the operation circuit.

According to a ninth aspect of the present invention, in the constant voltage control circuit according to any one of the first, sixth, and eighth aspects, the operation circuit and the monitor means are circuits having the same manufacturing process. There is a feature.

According to the ninth aspect of the present invention, since the manufacturing process is the same for the operation circuit and the monitor means, the elements inside each circuit, for example, have substantially the same temperature characteristics and the like. The fluctuation and the lower fluctuation of the second voltage can be substantially the same, and the second voltage can be monitored instead of the first voltage.

According to a tenth aspect of the present invention, in the constant voltage control circuit according to any one of the first to ninth aspects, when the power supply is turned on, the control means operates at the first cycle in the first cycle. A monitor cycle control unit for changing a voltage and changing the first and second cycles so as to change the first voltage in a second cycle longer than the first cycle during a normal operation; It is characterized by having.

According to the tenth aspect, when the power is turned on, the highest constant voltage is supplied and started, and the operation is started. During normal operation, the constant voltage value is sequentially increased at a constant cycle. Decrease by one step. Then, when the monitoring means detects that the operation has stopped, the constant voltage is increased and the steady state is reached after this detection. Here, during a period from power-on to a steady state, the period is shortened by supplying the first voltage at a first cycle shorter than the normal second cycle, thereby shortening the period for initialization. Throughput can be improved.

A constant voltage control circuit according to the present invention is connected to an operation circuit operating at a constant voltage, and supplies a constant voltage to the operation circuit; A monitor means for reaching an operation stop voltage for stopping the operation, and a control means for controlling the operation circuit so as not to reach the operation stop voltage based on the stop of the operation of the monitor means.

According to the eleventh aspect of the present invention, since the operation of the monitor is stopped before the operation of the operation circuit, the operation of the operation circuit can be prevented from being stopped beforehand, and the operation of the operation circuit can be guaranteed.

According to a twelfth aspect of the present invention, there is provided a semiconductor device, comprising: an operation circuit; and a constant voltage control circuit according to any one of claims 1 to 11, which forms a supply voltage to the operation circuit.
Are formed on the same substrate.

According to the twelfth aspect of the present invention, the voltage supplied to the operation circuit fluctuates due to external factors such as temperature characteristics and variations in elements during manufacturing. By doing so, it is possible to control the voltage even if such fluctuations may occur. still,
In the case where the operation circuit is an oscillation circuit, for example, in addition, it is possible to always establish a state where the absolute value of the constant voltage is larger than the absolute value of the operation stop voltage. Need not be increased unnecessarily, wasteful power consumption can be eliminated, and the power consumption of the semiconductor device can be reduced.

The thirteenth aspect of the present invention is the first aspect of the present invention.
1 defines a portable electronic device including any one of the constant voltage control circuits.

According to the portable electronic device, fine adjustment of the constant voltage can be performed, fine adjustment of 0.1 V or less can be easily performed, the life of the battery used can be extended, and the portable electronic device can be used. The convenience of the electronic device can be improved, and a portable electronic device with optimal low power consumption and low power supply voltage can be realized.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an oscillation circuit will be specifically described below with reference to the drawings.

[First Embodiment] (Overall Configuration of System) FIG. 1 shows a constant voltage control circuit of this embodiment. As shown in FIG. 1, the constant voltage control circuit 1 of this embodiment has an operation circuit connected to an output terminal A for outputting a constant voltage Vreg, and the constant voltage Vreg supplied to the operation circuit is
This is a circuit for controlling the constant voltage Vreg to a desired constant voltage value even when it fluctuates due to various factors. In this example, a crystal oscillation circuit 90 as shown in FIG. 5 is used as an example of the operation circuit to be controlled, but the operation circuit is not limited to such a crystal oscillation circuit. .

In FIG. 1, a constant voltage control circuit 1 includes a constant voltage generating circuit 10 as a constant voltage generating means for generating a constant voltage Vreg and a voltage Vregm slightly lower than the voltage Vreg.
Monitoring means 20 for monitoring a change in voltage Vregm;
Control means 22 for changing and controlling the voltage Vreg of the constant voltage generation circuit 10 based on the detection result of the monitor means 20;
Having.

The constant voltage generation circuit 10 includes a crystal oscillation circuit 90
A constant voltage Vreg, which is a first voltage supplied to the power supply, and a second voltage which varies with the constant voltage Vreg and becomes | Vreg |> | Vregm |
And a voltage Vregm. still,
The difference between the voltage | Vreg | and the voltage | Vregm | is when the operation monitor circuit 30 is stopped, and before the Vreg is switched, a range where the oscillation circuit 90 does not stop, for example, 10 to several tens
mv. If this difference is too small, the monitor will detect it in a certain period, and may stop during this period.

The monitoring means 20 monitors the fluctuation of the voltage Vregm which fluctuates with the voltage Vreg. The monitoring means 20 controls the voltage Vregm based on the operation position detection timing signal (reference clock) CK and the monitoring result of the voltage Vregm before the voltage Vreg reaches the operation stop voltage of the crystal oscillation circuit 90 before the voltage Vregm reaches the operation stop voltage. The operation monitor circuit 30 which stops operation when it reaches the point and outputs an operation stop signal X
Having. Here, the operation monitor circuit 30 is preferably formed by the same manufacturing process as that of the crystal oscillation circuit 90.

The control means 22 is a differentiating circuit which is a first pulse generating means for outputting at least one first pulse (up) based on the operation stop signal X output from the operation monitoring circuit 30. 50 and the second of the predetermined period φn
And a second pulse generating means 24 for generating a pulse (down), and a signal for increasing the voltage Vreg based on the first pulse are output to the constant voltage generating circuit 10, and a voltage Vreg is generated based on the second pulse. And pulse control means 26 for outputting to the constant voltage generating circuit 10 a signal for sequentially lowering.

The differentiating circuit 50 has a function of outputting the first pulse that can be counted up to the up-down counter 60, for example, only once when the operation stop signal X switches from H to L.

The second pulse generator 24 includes a timing signal generator 80 for generating a predetermined timing signal.
And a monitor cycle controller 82 for changing and controlling the cycle φn of the predetermined cycle timing signal generated and output by the timing signal generator 80 based on the power-on ON timing of the power supply 84.

The pulse control means 26 outputs the first pulse (u
p), an up-down counter 60 that counts a second pulse (down) having a period φn, and converts the output of the up-down counter 60 so as to output n serial signals, for example, 8 or 16 serial signals. And a decoder 70 for performing the operation.

The up-down counter 60 receives a first pulse (up) as an input signal for up and a second pulse (down) as an input signal for down. Thus, for example, if it is 4 bits,
When the first pulse (up) is input and “0000” comes, it becomes “0001”, and then the second pulse (d
When (own) is input, it returns to “0000”. The first pulse (up) and the second pulse (up) are devised by shifting the phase.
At the same time.

Next, the operation of the constant voltage control circuit will be described.

When the power is turned on, the constant voltage generating circuit 10 supplies the highest constant voltage Vreg to the crystal oscillation circuit 90 to start monitoring.

At the time of normal operation after the operation is started, the timing signal generator 80 and the monitor cycle controller 82 output a second pulse (down) having a constant cycle φn to the up / down counter 60. Then, based on the counter value of the up / down counter 60, if the decoder 70 has, for example, eight output lines, the decoder 70 sets any one of the output lines to the selected state at a predetermined period φn. , To the constant voltage generating circuit 10. As a result, the voltage Vre output from the constant voltage generation circuit 10 is
g gradually decreases the constant voltage value of eight stages (or 16 stages) by one step every predetermined period φn.

When the output of the decoder 70 is, for example, eight lines, eight types of constant voltage values of the voltage Vreg can be prepared and can be varied in eight steps. 16 constant voltage values can be prepared and can be varied in 16 steps. The division number of 8 or 16 is determined by the Vt of the MOS transistor in the constant voltage generation circuit 10.
From the viewpoint of production variation of h, 8, 16 and the like are particularly preferable, but may be more.

In the operation monitor circuit 30, the crystal oscillation circuit 9
0, the constant voltage Vreg supplied to the crystal oscillation circuit 90 so as to follow the constant voltage Vreg accompanying the temperature fluctuation shown in FIG.
The voltage Vregm which is several tens mv lower than that is monitored.

Here, due to external factors such as temperature fluctuation, etc.
For example, when the voltage Vreg gradually decreases, the voltage Vregm also decreases in conjunction with this. Then, the voltage Vregm becomes the voltage Vreg.
The operation monitor circuit 30 reaches the operation stop voltage before the voltage Vreg reaches the operation stop voltage of the crystal oscillation circuit 90 because the voltage is several tens mv lower than that. The operation monitor circuit 30
Is desirably formed by the same manufacturing process as that of the crystal oscillation circuit 90. It is desirable that the operation monitor circuit 30 has a circuit configuration in which the operation is stopped before the crystal oscillation circuit 90 due to a drop in the power supply voltage.

When the operation monitor circuit 30 stops, the operation monitor circuit 30 outputs an operation stop signal X, and the differentiation circuit 50
Is based on the operation stop signal X, the first pulse (u
p) is output to the up-down counter 60. Then, based on the counter value of the up-down counter 60, if the decoder 70 has, for example, eight output lines, the decoder 70 generates a constant voltage signal so that any one of the output lines is set to the H level. Output to the circuit 10.

As a result, the voltage Vreg output from the constant voltage generating circuit 10 increases by one stage. Thereafter, the step of decreasing the voltage Vreg and the step of increasing the voltage Vreg are repeatedly performed to control the constant voltage Vreg, and as a result, the constant voltage Vreg settles in a steady state.

As described above, since the operation monitor circuit 30 is stopped first before the crystal oscillation circuit 90 is stopped, the operation of the crystal oscillation circuit 90 is stopped without stopping the operation, and the constant voltage Vreg is minimized. Since operation can be performed at a low voltage (constant voltage), ultra-low power consumption can be achieved.

(Operation Monitor Circuit) This operation monitor circuit 3
An example of 0 is shown in FIG. In the figure, an operation monitor circuit 30 includes a reference clock CK which is a predetermined timing signal.
Divider 32 for dividing the frequency of the signal, and level shifter 34 as a voltage converter for converting the voltage of the divided timing signal
And inverters INV2 and INV3 for converting the voltage-converted signals into signals that invert each other, and a clock detection circuit 40 that outputs an operation stop signal X when the operation is stopped.

The frequency dividing section 32 includes a flip-flop FF1
And a NAND gate NAND1 connected to this output
And an inverter INV1 connected to one of the two outputs of the NAND gate NAND1. In the frequency dividing section 32, for example, as shown in FIG. 3A, when the operation monitor circuit 30 is operating and the monitor is ON, when the reference clock CK is input at the frequency 2K,
The output of the flip-flop FF1 is output at the frequency 1K after dividing the frequency by. Further, the voltage Vregm is supplied to the frequency divider 32, and when the operation monitor circuit 30 is in the monitor OFF state where the operation is stopped, the output of the flip-flop FF1 is maintained at the H level (or the L level). That is, when the output is stopped when the output Q of the flip-flop FF1 is H, H is output, and when the output Q is stopped when the output Q is L, L is output. Note that the frequency dividing unit 32 may have a configuration including only the flip-flop FF1.

Here, the flip-flop FF1
Is an element which is most easily stopped among semiconductor elements and hardly operates depending on the power supply voltage.
In 0, a flip-flop is used. In addition, there is also an effect of reducing the current and suppressing the driving ability. It is to be noted that, as the logic element whose operation is easily stopped, in addition to the flip-flop, a logic element in which transistors are basically connected in series, for example, a multi-input or multi-input NAND gate is preferable. In this case, since a plurality of NchTrs are arranged in series,
It is preferable that the transistor is hard to move and the number of series transistors is large.

The voltage of the signal output from the frequency divider 32 is increased by the level shifter 34, and the signal is output from the inverter INV2,
The input A1 of the clock detection circuit 40 via INV3,
The signals are input to A2 as mutually inverted signals.

(Clock Detection Circuit) Here, the details of the clock detection circuit 40 will be described with reference to FIG. As shown in FIG. 2, the clock detection circuit 40 continues to output an H level signal from the output XO by continuously supplying input signals that are mutually inverted at a certain period to the two inputs A1 and A2. Regardless of the input signal A1, A
2 (when the clock stops running), the output XO
It has a function of detecting, for example, outputting an L-level signal. FIG. 4 shows a specific example of the clock detection circuit 40.

In the figure, the clock detection circuit 40
An NMOS QN50 having an input A1 connected to a gate, an NMOS QN51 connected in series with the NMOS QN50 and an input A2 connected to a gate, an inverter INV4 connected to a drain of the NMOS QN51, and an NMOS QN51.
C2 and a high resistance R1 connected between the drain of the NMOS and the ground VDD maintained at the ground potential;
A capacitor C1 interposed between the connection point between the drain of the OSQN50 and the source of the NMOS QN51 and the ground VDD.
And

The operation of the clock detection circuit 40 is performed as follows. That is, when the voltage Vreg drops sequentially, the voltage Vregm also drops in conjunction with it (the reason will be described later). In such a normal operation, the flip-flop FF1, which is hard to operate, performs a frequency division operation, and the output of FF1 is HLHL. Therefore, during the operation of the operation monitor circuit 30, H (L) is input to A1 and L (H) is input to A2.

When H is input to A1 and L is input to A2, the NMOS QN50 is turned on and the NMOS QN51 is turned off. At this time, the capacitor C1 is charged with the electric charge from the voltage VSS. Next, when L is input to A1 and H is input to A2, the NMOS QN50 is turned off and the NMOS QN51 is turned on, and charges from the voltage VSS are stored in the capacitor C2.

As described above, when the clock is input, the potential of the voltage VSS is always charged in the capacitor C1 or C2. Therefore, the input potential of the inverter INV4 is always at the L level, and the output of the inverter INV4 is at the H level. , And the output XO signal continuously outputs H, for example. As described above, if the input signals of A1 and A2 are mutually inverted, the output XO is H.

Next, when the voltage Vregm further decreases and reaches the operation stop voltage (operation stop voltage of the operation circuit) of the flip-flop FF1, the flip-flop FF1 stops the frequency dividing operation, and the output of the flip-flop FF1 becomes A constant potential, for example, L is continuously output. Therefore, no clock is input to the inputs A1 and A2 of the clock detection circuit 40. Then, when no clock is input, one of them, for example, the NMOS QN 51 is turned off. Then, the charge of VSS stored in the capacitor C2 is transferred to the inverter IN
Since a discharge path is provided to the input side of V4, the charge of the capacitor C2 cannot be held, and the charge is released based on the time constant CR. Therefore, after a lapse of time, the high resistance R
1, the potential is always maintained at the H level side, and the output XO
Becomes L.

In this way, the output XO of the clock detection circuit 40 becomes H when the clock comes. When it is detected that the clock does not come, if it outputs H, for example, it switches to L when it first outputs H. It is possible to detect the distinction between the operation of 30 and the operation stop.

Accordingly, the clock detection circuit 40 outputs an operation stop signal indicating that the operation monitor circuit 30 has stopped to the differentiating circuit 50 of FIG.

(Monitor Period Control Unit) Further, the monitor period control unit 82 of FIG. 1 will be briefly described. The monitor cycle control section 82 has a function of changing and controlling the cycle of the predetermined cycle timing signal generated and output by the timing signal generation section 80 based on the power-on ON timing of the power supply 84. FIG. 7 shows how the constant voltage Vreg changes with respect to the time T from when the power is turned on until the steady state is reached.

[0082] That is, as shown in FIG. 7, the power-on t ₁
At the time of the initial state from t to the steady state t ₂ , the period is φ _n2
The output is performed at (first cycle), and when a steady state is reached after a predetermined time has elapsed, change control is performed so that the cycle is output at φ _n1 (second cycle). In this case, the period of φ _n1 is φ
Preferably, the period is longer than _n2 . In this way, the period t ₁ ~t ₂ can be shortened to reach a steady state from the power-on, it is possible to improve the throughput.

As a result of the inventor's intensive studies, the maximum value φ _n1max of the monitor period φn1 in the normal _state is 100 to 2
00 [sec], min of the monitor cycle φn1 at normal time
The value φ _n1min is 10 [sec] (in the case of an IC operating with a current consumption of 100 _nA or less), the max value φ _n2max of the initial monitoring period φn2 is a period that quickly settles to an appropriate _Vreg value, and the initial Monitor cycle φ
It has been found that the min value φ _{n2min of} n2 is preferably set to about 1 to 2 sec [sec].

Therefore, the monitor cycle control unit 82
It is preferable that _n1max , _φn1min , _φn2max , and _φn2min be freely changed as necessary.

The timing of switching between the monitor cycles φn2 and φn1 may be such that a timer (not shown) is built in the monitor cycle control unit 82 and switched after a predetermined time has elapsed, or the voltage Vreg is monitored to monitor the steady state. It is good also as a structure which switches when reaching.

(Constant Voltage Generation Circuit) FIG. 5 shows the constant voltage generation circuit 10 and the crystal oscillation circuit 90. The crystal oscillation circuit 90 is a crystal oscillation circuit used for a quartz wristwatch. FIG. 5 shows a constant voltage generating circuit 1
0 will be described.

The constant voltage generation circuit 10 includes a crystal oscillation circuit 90
Constant voltage Vreg to be supplied to the operation monitor circuit 30
A circuit for forming the monitor voltage Vregm in the above-described embodiment, and is capable of lowering the constant voltage Vreg to the minimum oscillating voltage in the entire temperature range that guarantees the oscillation operation of the crystal oscillation circuit. , An operational amplifier OP1, an operational amplifier OP2, a selection circuit 10P, an output NMOS QN2 of the operational amplifier OP1, and an output NMOS of the operational amplifier OP2
QN4, constant current sources TN1, TN2, TP, and NMOS QN
1 and the NMOS QN3.

In the constant voltage generating circuit shown in FIG.
By P, one input voltage to the operational amplifier OP2, that is, a constant voltage control PMOS for controlling the constant voltage Vreg,
A plurality of constant voltage control PMOSs formed with different current amplification factors β (gate length, gate width)
Among them, the optimum constant voltage control PMOS can be selected.

Further, for example, the gate width of the NMOS QN3 is
The voltage width of several tens of mV between the voltage Vreg and the voltage Vregm is formed by changing the size of the NMOS QN1 so as to be larger than the gate width.

The operational amplifier OP1 has a + input terminal receiving a voltage formed by the constant voltage control NMOS QN3, and a − input terminal receiving a voltage formed by the selection circuit 10P. The gate input voltage of the NMOS QN4 is controlled by receiving the output of the operational amplifier OP1.

The operational amplifier OP2 has a positive input terminal and a negative input terminal, and the positive input terminal is a constant voltage control NMOS QN1.
Receive the voltage formed by The negative input terminal receives a voltage formed by the selection circuit 10P including the PMOS QPs 30 to 37 that are turned on and off by the plurality of PMOS QPs 10 to 17. This is a so-called differential amplifier that amplifies and outputs the potential difference between the voltage applied to the + input terminal and the voltage applied to the − input terminal.

The output NMOS QN2 is connected to the operational amplifier OP2.
Is received at the gate, and the drain is connected to the output line of Vreg of the constant voltage generating circuit. The power supply voltage Vss is applied to the source and the back gate of the output NMOS QN2.

Selection circuit 10 including PMOS QPs 30 to 37
P is a constant voltage Vreg formed by the constant voltage generation circuit.
Is controlled by controlling the input voltage to the − input terminals of the operational amplifiers OP1 and OP2. The gates and drains of the constant voltage control PMOS QPs 30 to 37 are commonly connected to the negative input terminals of the operational amplifiers OP1 and OP2. That is, the drains and gates of the constant voltage control PMOS QPs 30 to 37 are electrically connected to the power supply voltage Vss, and the source side is the selection control PMOS QP 1
0 to 12 are connected respectively.

Here, the constant voltage control PMOS QPs 30 to 3
7 are formed with different current amplification factors β, respectively. The current amplification factors β30 and PMMO of the PMOS QP30 are different from each other.
..., PMOS QP37
Is, for example, β37>β36>.
It is formed so as to have a relationship of> β30. The control of the current amplification factor can be performed by changing the gate width and the gate length at the time of design, performing layout, and forming elements based on the layout. For this layout,
In particular, it can be formed without any problems in layout rules,
PM for constant voltage control without any problems in the semiconductor manufacturing process
An OS can be formed.

Then, the constant voltage control PMOSs QP30, QP
,..., QP37 are connected in series with selection control PMOSs QP10 to Q17 which receive selection signals SEL0 to SEL7 at their gates, respectively. The ground voltage Vdd is applied to each source of the selection control PMOSs QP10 to Q17.

The selection signals SEL0 to SEL7 are output from the decoder 70 shown in FIG. 1, and the PMOs for controlling the constant voltages of the different current amplification factors β30, β32,.
This signal is for selecting one PMOS from SQPs 30 to 37. To form the selection signals SEL0-7,
This can be performed using the up-down counter 60 described above. This up / down counter 60
The constant voltage control PMOS QP 30 in the constant voltage generation circuit 10
37 is a circuit for generating selection signals SEL0 to SEL7 for selecting an optimal constant voltage control PMOS. Therefore, when the selection signal SEL0 is at a low level, the PMOS QP30 is selected, when SEL1 is at a low level, the PMOS QP31 is selected,.
37 can be selected. Also, the selection signals SEL0 to SEL
Since each of EL7 is set to the high level, PMOSQP
30 to QP 37 can each be set to a non-selected state.

The constant voltage control PMOSs QP30 to Q37 are used to supply a current to any one of the constant voltage control PMOSs in order to form the constant voltage Vreg in an optimum state.

Since the input voltage to the + input terminals is fixed, the input voltage to the-input terminals of the operational amplifiers OP1 and OP2, that is, the difference voltage between the + input terminal and the-input terminal is selected. Output signals from the operational amplifiers OP1 and OP2, that is, the magnitudes of the constant voltages Vregm and Vreg can be controlled. That is, the ON / OFF of the constant voltage control PMOS QPs 30 to 37 is controlled by the input of the selection signals SEL0 to SEL7, and one constant voltage control PMOS formed with the optimum current amplification factor is selected.

The constant current sources TN1, TN2 and TP are, for example, depletion type PMOs as shown in FIG.
It is formed by S (DPMOS). In the element manufacturing process, the layout design and the control of the manufacturing apparatus are performed so that the MOS manufacturing conditions are the same so that the gate width, the gate length and other sizes, the impurity implantation concentration, and the like are the same, and the constant current source TN1 , TN2 and TP are preferably formed. Thereby, the constant current sources TN, T
P will have the same temperature characteristics.

Next, a method for selecting a constant voltage control PMOS will be described.

Since the selection signal SEL0 is at the low level and a low-level voltage is applied to the gate of the selection control PMOS QP10, the selection control PMOS QP10 is turned on. Therefore, the source of the constant voltage control PMOS QP30 is set to the high level. Thus, the constant voltage control PM whose gate and drain are electrically connected to the power supply Vss
Since the OSQP 30 is turned on, the constant voltage control PMOS QP3
0 can be selected.

On the other hand, at this time, the selection signals SEL2,.
, SEL7 is at a high level, so that the selection control P
The selection signals SEL2,... SEL7, that is, high-level signals are applied to the gates of the MOS QP11,.
7 turns off. Therefore, the selection control PMOS QP31,.
The QP 37 is not selected because it is electrically disconnected from both power supplies of the ground voltage source Vdd and the power supply voltage source Vss.

P for constant voltage control having different current amplification factors
A desired constant voltage control PMOS is set to 1 out of 8 MOSs.
You can select one. For example, β with a high current amplification factor
When the constant voltage control PMOS QP 37 having the voltage 37 is selected, the constant voltage Vreg of the output voltage of the operational amplifier OP2 is formed as follows.

That is, when a constant current flows through the constant voltage control PMOS QP 37, a voltage α | Vthp 37 | dependent on the absolute value | Vthp 37 | of the threshold voltage of the constant voltage control PMOS QP 37 is applied to the signal line 100. The signal line 101 has the same potential α | Vthp37 | as the signal line 100 due to the operation of the operational amplifier OP2 and the output NMOS QN2.

Then, when a constant current flows through the constant voltage control NMOS QN1, a signal line 101 and a signal line 102 are generated.
, The threshold voltage Vthn1 of the constant voltage control NMOS QN1
, A potential difference of αVthn1 is generated. Therefore, between the potential of the signal line 102, that is, between the output of the constant voltage Vreg and the ground voltage Vdd, α depending on the potential | Vthp37 | + Vthn1
A constant voltage Vreg of (| Vthp37 | + Vthn1) is generated. Similarly, a constant voltage Vregm is also generated on the signal line 104.

The constant voltage control NMOS QN1 and the constant voltage control PMOS QP30 to 37 operate with a current in the saturation region. Since there is no change in the threshold voltage of each of the constant voltage control NMOS QN1 and the constant voltage control
Focusing only on OSQPs 30 to 37, the absolute value | Vreg | of the constant voltage decreases as the current amplification factor increases,
The absolute value | Vreg | of the constant voltage increases as the current amplification factor decreases.

Therefore, when the constant voltage control PMOS QP 37 is selected, the absolute value of the constant voltage | Vreg | becomes the lowest. When the constant voltage control PMOS QP 30 is selected, the absolute value of the constant voltage
| Vreg | is the highest. Here, for example, the current amplification factor β
The difference between β30 and β31,..., Β36 and β37 can each be set to about 1.2 to 1.5 times.

Then, the constant voltage Vreg and the oscillation stop voltage Vs
In relation to to, the absolute value of the constant voltage | Vreg | is selected to be as low as possible within a range satisfying | Vreg |> | Vsto |, so that the power consumption of the oscillation circuit and the constant voltage generating circuit is significantly reduced. Can be smaller.

As described above, since the selection circuit 10P is provided, the optimum constant voltage Vreg can be formed, so that the fine adjustment of the constant voltage Vreg can be performed, and the power consumption can be reduced as much as possible. Can correspond to a low power supply voltage of a semiconductor device.

Therefore, by adjusting the input voltage to one terminal of the operational amplifier in the constant voltage generating circuit,
Fine adjustment of the constant voltage Vreg can be performed. For this reason, fine adjustment of 0.1 V or less is possible, and low power consumption which is optimal for application to portable electronic devices, watches, etc. without adversely affecting the semiconductor device even when the power supply voltage is reduced.
A semiconductor device with a low power supply voltage can be realized.

In the above description, the selection signals SEL0-SEL0
Although the method of selecting only one of the SELs 7 is adopted, the constant voltage | Vreg | can be controlled by changing the current amplification factors β30, β32,. A method of selecting a plurality of the SELs 7 may be used.

As described above, in the present embodiment, the description has been made assuming that there are eight types of constant voltage control PMOSs having different current amplification factors. However, the number can be freely set without any particular limitation. The number of selection signals can also be provided corresponding to the number of constant voltage control PMOSs. Further, the setting of the current amplification factor of the constant voltage control PMOS is set to β37.
>...>β36> β30, but the present invention is not limited to this, and the current amplification factor can be freely set. Further, the method for stopping the operation monitor circuit faster than that of the crystal oscillation circuit is not limited to the above, and the threshold value of the transistor in the operation monitor circuit may be changed to the threshold value of the transistor in the crystal oscillation circuit. A configuration in which the current amplification factor is set higher than the current amplification factor, or a configuration in which the current amplification factor of the transistor in the operation monitor circuit is set smaller than the current amplification factor of the transistor in the crystal oscillation circuit may be used.

[Embodiment 2] In FIG. 6, in the constant voltage generation circuit 10 shown in FIG. 5, the selection circuit 10P-1 includes eight upper constant voltage control PMOSs and a lower selection control N
The configuration is such that a total of 16 MOSs of 8 stages are used. That is, different from the first embodiment, the lower selection control MO
NMOS is used instead of PMOS for S. In this case, the same operation and effect as described above can be obtained.

[Third Embodiment] FIG. 8 shows that constant voltage generation circuit 10 shown in FIG.
And the selection circuit 20P is a PMO for constant voltage control.
The configuration is such that a total of 32 stages of S stages and 16 selection control PMOS stages are used. Also, the output of the decoder 70 needs to be 16 stages. In this case, since 16 types of constant voltage control PMOSs having different current amplification factors are used, fine adjustment of the constant voltage Vreg can be performed more finely.

Further, as shown in FIG. 9, the selection circuit 30P
And 16 stages of NMOS for constant voltage control and PMO for selection control
S may be configured to use a total of 32 S stages of 16 stages.

[Embodiment 4] FIG. 10 shows an operational amplifier O
A constant voltage generation circuit that controls the voltage supplied to the + input terminal of P2 is shown. The constant voltage generation circuit 110 of FIG.
Is formed with a plurality of constant voltage control NMOSs for controlling an input voltage to a + input terminal to an operational amplifier and having different current amplification factors, and an optimum constant voltage control among a plurality of constant voltage control NMOSs. In this case, an NMOS for use can be selected.

In the constant voltage generating circuit shown in FIG. 10, the operational amplifier OP2 has the + input terminal connected to the selection control NMOS QN10-2.
NMOS QN3 for constant voltage control, on / off controlled by 5
It receives the voltage formed by the selection circuit 10N including 0 to 45. Here, the constant voltage control NMOS QNs 10-25
Are formed with different current amplification factors, respectively. The current amplification factor βn2 of the constant voltage control NMOS QN25 is
5, the current amplification factor βn2 of the constant voltage control NMOS QN24
4,..., The current amplification factor βn10 of the constant voltage control NMOS QN10 is, for example, βn25>βn24>.
0 is formed.

Then, the constant voltage control NMOSs QN10, QN
11,..., Connected in series with the source of QN25,
In addition, selection control NMOSs QN30 to QN45 which receive selection signals SEL0N to 15N at respective gates are provided correspondingly. When any of the selection signals SEL0N is at a high level, the constant voltage control NMOS QN10 can be set to the selected state.

As described above, one desired constant voltage control NMOS can be selected from the 16 constant voltage control NMOSs on the + input side of the operational amplifier, and the constant voltage Vreg can be selected.
And the oscillation stop voltage, the minimum | Vreg | can be selected while satisfying the condition of | Vreg |> | Vsto |, so that the oscillation operation is performed with the constant voltage Vreg as low as possible while securing the operation margin. Can be performed.

Although the description has been given assuming that there are 16 types of constant voltage control NMOSs having different current amplification factors, the number can be freely set without any particular limitation. Also, the setting of the current amplification factor of the constant voltage control NMOS is set to βn2
Although described as 5> βn24 >>. Beta.n10, the present invention is not limited to this, and the setting of the current amplification factor can be freely set.

Fifth Embodiment A constant voltage generating circuit shown in FIG. 11 is a constant voltage control PMOS for controlling an input voltage to a negative input terminal of an operational amplifier and a constant voltage control for controlling an input voltage to a positive input terminal. A plurality of NMOSs, each having a different current amplification factor, and an optimum constant voltage control NMO from the plurality of constant voltage control PMOSs and NMOSs.
In this configuration, S and PMOS can each be selected.

This constant voltage generation circuit 120 is connected to the selection circuit 1
0N, 30P.

NM for constant voltage control in selection circuit 10N
The OSQNs 10 to 25 are formed with different current amplification factors, respectively, and the selection signals SEL0N to 15N are used as the constant voltage control NM.
One constant voltage control NMOS from OSQN10-25
Select FIG. 12 shows an arrangement of these NMOS QNs 10 to 25.

Constant voltage control PM in selection circuit 30P
The OSQPs 30 to 45 are formed with different current amplification factors, respectively, and the selection signals SEL0P to 15P are used as the constant voltage control PMs.
One PMOS for constant voltage control from OSQP30 to 45
Select

One of each of the constant voltage control NMOSs and PMOSs included in the selection circuits 30P and 10N is selected, and a current flows through each of the selected constant voltage control NMOSs and PMOSs. Can be controlled.

Here, the selection circuits 10N and 30P provide
Since the voltage of both terminals applied to the operational amplifier OP2 is controlled, the output voltage of the operational amplifier OP is selected by a combination of the constant voltage control NMOS and the PMOS.

That is, one desired constant voltage control NMOS can be selected from the 16 constant voltage control NMOSs on the + input side of the operational amplifier OP2, and the constant voltage control PM on the-input side can be selected.
A desired constant voltage control PMOS is set to 1 out of 16 OSs.
You can select one.

At this time, the selection range of the constant voltage Vreg can be widened. That is, since there are 16 × 16 combinations of the constant voltage control NMOS and PMOS, the optimum combination of the constant voltage control NMOS and PMOS can be realized by the value of the absolute value | Vsto | of the oscillation stop voltage. That is, since two systems are provided, the voltages supplied to both input terminals of the operational amplifier can be controlled respectively, and an optimum constant voltage Vreg can be formed. Therefore, fine adjustment of the constant voltage Vreg can be performed, and power consumption can be minimized.
Compatible with low power supply voltage of semiconductor devices.

There are 16 types of constant voltage control PMOS, NMO
Since there are 16 types of S, there are 16 × 16 patterns, and an optimal one can be selected from these. Therefore, although the number of elements of this constant voltage generation circuit is larger than that of the constant voltage generation circuits of the first and second embodiments, the selection range of the constant voltage Vreg is widened, so that the fine adjustment of the constant voltage Vreg is performed more precisely. It is possible to select a constant voltage Vreg that can cope with a recent reduction in power supply voltage.

In the above, the description has been given assuming that there are 16 types of constant voltage control PMOSs and NMOSs each having a different current amplification factor, but this number can be freely set without any particular limitation. Further, the current amplification factor of the constant voltage control NMOS can be freely set.

[Embodiment 6] FIG. 13 shows a constant voltage control circuit 131 of a type in which a voltage Vreg is inputted to a monitor means 131. In this case, the constant voltage control circuit 131 uses the monitoring means 131 and the V of the constant voltage generation circuit 134 based on the monitoring detection result of the monitoring means 131.
It has a control means 132 for controlling the reg value and a constant voltage generating circuit 134 for outputting only the voltage Vreg. An operation circuit 135 is connected to the constant voltage generation circuit 134, and the voltage Vreg is supplied to the operation circuit 135.
Operation monitor circuit 133 formed in monitor means 131
Is also provided.

What is important in this example is that the absolute value | V _th1 | of the threshold value of the second transistor (not shown) formed in the operation monitor circuit 133 is _calculated by the operation circuit 135.
It is set slightly higher than the absolute value | V _th2 | of the threshold value of the first transistor (not shown) formed therein. In this case, the higher the threshold value of the second transistor, the easier it is to stop at a lower voltage, so that the operation monitor circuit 133 stops at the first operation stop voltage and the operation circuit 135 stops the second operation stop lower than the first operation stop voltage. It will stop at the voltage.

As a result, as shown in the first to fourth embodiments, the low voltage Vregm need not be generated by the constant voltage generation circuit 134. That is, even if the voltage Vreg is directly monitored and the same voltage is supplied to each of the operation circuit 135 and the operation monitor circuit 133, the operation monitor circuit 133 stops before the operation circuit 135 stops at the second operation stop voltage. To stop at the first operation stop voltage, the operation monitor circuit 133
Can stop earlier.

Note that the first and second transistors are NM
Any of OS and PMOS may be used.

As a method of stopping the operation monitor circuit earlier than the operation circuit while supplying the voltage Vreg to each of the operation monitor circuit and the operation circuit, a method of changing the threshold value of the transistor as described above is used. Other methods include the following.

First, there is a method of setting the current amplification factor of the second transistor in the operation monitor circuit smaller than the current amplification factor of the first transistor in the operation circuit.
Also in this case, since the second transistor having a small current amplification factor stops quickly, even if the same voltage Vreg is applied,
Since the current amplification factor of the second transistor of the operation monitor circuit is low, the operation monitor circuit stops earlier. Since the current gain is represented by (channel width W / channel length L) = current gain, the channel width W or the channel length L of each transistor may be set as desired.

Further, a configuration may be adopted in which a logic element having more input stages than the logic element formed in the operation circuit is formed in the operation monitor circuit. Among these logic elements having a large number of input stages, flip-flops are preferred. Also in this case, the operation monitor circuit stops before the operation circuit.

As described above, if the operation monitor circuit is provided with a circuit that stops earlier with a certain power supply than the operation circuit, a circuit that has a function of stopping earlier even when the same power supply is turned on, or the like, Any configuration may be used.

As described above, according to the present embodiment, the generation circuit of Vregm becomes unnecessary, and the operation monitor circuit can be stopped first even under the same power supply conditions as the operation circuit.

[Embodiment 7] Next, an embodiment of a portable electronic device using the above-described constant voltage control circuit will be described with reference to FIG.
4 and FIG.

FIG. 14 shows an example of an electronic circuit used in a wristwatch. This wristwatch incorporates a power generation mechanism (not shown). When the user wears the wristwatch and moves his arm, the rotating weight of the power generating mechanism rotates, the kinetic energy at that time rotates the power generating rotor at high speed, and an AC voltage is output from the power generating coil 300 provided on the power generation status side. You. This AC voltage is rectified by the diode 302,
The secondary battery 301 is charged. The secondary battery 301 forms a main power supply together with the booster circuit 303 and the auxiliary capacitor 304.

In this embodiment, when the voltage of the secondary battery is low and less than the driving voltage of the timepiece, the voltage of the secondary battery is converted by the boosting circuit 303 into a high voltage that can be driven by the clock, and stored in the auxiliary capacitor 304. . Then, the clock circuit operates using the voltage of the auxiliary capacitor 304 as a power supply.

This timepiece circuit is configured as a semiconductor device including the constant voltage generation circuit according to any of the first to fifth embodiments and a crystal oscillation circuit connected to the constant voltage generation circuit, and is connected to the semiconductor device via a terminal. Crystal oscillator X'tal
Oscillating frequency preset by using
An oscillation output having a frequency of Hz is generated, and the oscillation output is frequency-divided to output drive pulses having different polarities every second. This drive pulse is applied to the drive coil 306 of the step motor connected to the clock circuit.
Is input to Thus, the step motor (not shown) rotates the rotor every time a drive pulse is supplied, drives the second hand, minute hand, and hour hand of a timepiece (not shown), and displays the time on the display panel in an analog manner.

Here, the clock circuit 330 of this embodiment is a power supply voltage circuit 2 driven by a voltage supplied from a main power supply.
20, a constant voltage generating circuit 210 according to any one of the first to fourth embodiments for generating a predetermined constant voltage Vreg lower than this value from this power supply voltage, and a constant voltage operation driven by this constant voltage Vreg. And a circuit section 240.

FIG. 15 is a more detailed functional block diagram of the clock circuit 330. As shown in FIG. Constant voltage operation circuit 23
Reference numeral 0 denotes a crystal oscillation circuit 200 partially including an externally connected crystal oscillator X′tal, a waveform shaping gate 201, and a high-frequency frequency dividing circuit 202.

The power supply voltage circuit section 220 includes the level shifter 2
03, the medium / low frequency dividing circuit 204, and other circuits 20
5 is included. In the clock circuit of the present example, the power supply voltage circuit 220 and the constant voltage generation circuit 210 are connected to the power supply voltage operation circuit 24 driven by the voltage supplied from the main power supply.
0.

The crystal oscillation circuit 200 includes a crystal oscillator X't
A sine wave output having a reference frequency fs = 32768 Hz is output to the waveform shaping gate 201 using al. The waveform shaping gate 201 shapes the sine wave output into a rectangular wave, and then outputs the sine wave output to the high frequency dividing circuit 202. High frequency dividing circuit 202
Divides the reference frequency 32768 Hz to 2048 Hz, and outputs the divided output to the middle / low frequency dividing circuit 204 via the level shifter 203. Medium / low frequency divider 2
04 is the signal divided to 2048 Hz,
Hz, and input to other circuits 205. The other circuit 205 includes a driver circuit that energizes and drives the coil in synchronization with the frequency-divided signal of 1 Hz.
The clock driving step motor is driven in synchronization with the frequency division signal of Hz.

In the timepiece circuit of the present embodiment, in addition to the power supply voltage operation circuit section 240 in which the entire circuit is driven by the power supply voltage Vss supplied from the main power supply, the constant voltage Vre
The reason why the constant voltage operation circuit unit 230 driven by g is provided is as follows.

That is, in such a timepiece circuit, it is necessary to reduce the power consumption in order to secure a stable operation for a long time. Normally, the power consumption of a circuit increases in proportion to the frequency of the signal and the capacity of the circuit, and further increases in proportion to the square of the power supply voltage. Here, focusing on the clock circuit, in order to reduce the power consumption of the entire circuit, the power supply voltage supplied to each part of the circuit may be set to a low value, for example, Vreg. The constant voltage generation circuit 210 has a minimum constant voltage V within a range that compensates for the oscillation operation of the crystal oscillation circuit 200.
reg can be formed.

Next, focusing on the signal frequency, the clock circuit is roughly divided into a crystal oscillation circuit 200 having a high signal frequency, a waveform shaping gate 201, a high frequency frequency dividing circuit 202, and a circuit 205 other than the above. be able to. As described above, the frequency of this signal is proportional to the power consumption of the circuit.

Therefore, the constant voltage generation circuit 210 of the present embodiment
From the power supply voltage Vss supplied from the main power supply, a lower constant voltage Vreg is generated and supplied to the circuit section 230 that handles high-frequency signals, that is, the crystal oscillation circuit 200, the waveform shaping gate 201, and the high-frequency frequency dividing circuit 202. ing. As described above, by lowering the drive voltage supplied to the circuit 230 that handles the high-frequency signal, the constant voltage generation circuit 21
The power consumption of the entire clock circuit can be effectively reduced without significantly increasing the burden of zero. In this embodiment, the reason why the level shifter 203 is provided between the high frequency divider 202 and the middle / low frequency divider 204 is as follows.
For the following reasons.

The output peak value of the high frequency frequency dividing circuit 202 is at the level of the constant voltage Vreg, and is smaller than the peak value of the voltage Vss of the main power supply. Therefore, even if the constant voltage Vreg level output of the high frequency divider 202 is directly input to the middle / low frequency divider 204 driven by the power supply voltage Vss, this input value is applied to the middle / low frequency divider 202 Does not exceed the logic level voltage of the first stage, the middle / low frequency dividing circuit 204 does not operate normally. Therefore, the level shifter 203 is used so that the middle / low frequency dividing circuit 204 operates normally.
The output peak value of the high frequency divider 202 is raised from the constant voltage level to the power supply voltage level.

As described above, since the clock circuit of the present example and the electronic circuit including the same include the constant voltage generating circuits of the first to fifth embodiments, regardless of manufacturing variations, the clock circuit of the oscillation inverter can be used. Since a minimum constant voltage can be supplied to the crystal oscillation circuit while the operation is secured with a margin, the power consumption of the electronic circuit and the clock circuit can be reduced. Therefore, in the watch or the portable electronic device as described above, not only can the oscillation operation be performed stably, but also the life of the battery can be extended, and the usability of the watch or the portable electronic device can be improved. Can be improved.

Further, by applying the above constant voltage generating circuit, by adjusting the input voltage to the terminal to the operational amplifier in the constant voltage generating circuit, the constant voltage Vreg is adjusted.
Fine adjustment of 0.1 V or less can be easily performed, and a portable electronic device, a clock, and the like with optimal low power consumption and low power supply voltage can be realized.

When an electronic apparatus including a constant voltage control circuit for generating only Vreg according to the sixth embodiment is configured, a portion corresponding to Vregm shown in FIGS.
It is sufficient that the operational amplifier OP shown in FIG. 18 uses only one type of circuit.

Although the apparatus and method according to the present invention have been described in accordance with certain specific embodiments thereof, those skilled in the art will recognize that they are described herein without departing from the spirit and scope of the invention. Various modifications can be made to the embodiment. For example, an IC or a semiconductor element in which an operation circuit and a constant voltage control circuit are integrally formed may be used. Also, an IC dedicated to the operation circuit and an IC dedicated to the constant voltage control circuit
May be formed on the same substrate.

Further, the operating circuit is not limited to the oscillation circuit, but may be a circuit including another high-frequency portion. In other words, any circuit having a characteristic that the operation stops when the voltage drops below a certain voltage is used. good. In addition, for the sake of convenience of the explanation using the oscillation circuit as the operation circuit, the constant voltage of the operation circuit is higher than the operation stop voltage of the operation circuit due to the relationship between the operation guarantee of the oscillation circuit and the characteristics of the temperature fluctuation of the constant voltage Vreg. A method of controlling a constant voltage that fluctuates within a range that satisfies the condition that the condition is satisfied, that is, a method of preventing a constant voltage from gradually decreasing to reach an operation stop voltage is adopted, but is not limited to this. Absent. That is, an operation circuit that does not stop operation when the potential becomes equal to or lower than a certain potential, but stops when the potential becomes equal to or higher than a certain potential, a configuration that prevents a constant voltage from gradually rising to reach an operation stop voltage, A circuit having characteristics may be used. In this case, the constant voltage control circuit can stop the operation monitor circuit earlier than the operation circuit by forming a voltage Vregn slightly higher than the voltage Vreg in the constant voltage generation means.

In addition, from the viewpoint that the constant voltage generation circuit is a circuit that forms one power supply that supplies the oscillation inverter of the crystal oscillation circuit, a constant current source that supplies current to the constant voltage generation circuit, By matching the temperature characteristics with the constant current source that supplies current to the circuit, the constant voltage V
A method of matching the temperature characteristics of reg and the oscillation stop voltage Vsto may be used.

Further, the constant voltage control NMOS QN1 and the PMOS QP1 in the constant voltage generating circuit may be operated in the current range in the saturation region so that the temperature characteristics of the constant voltage Vreg and the oscillation stop voltage Vsto match. .

Furthermore, as the constant current sources TN and TP, constant current sources having negative temperature characteristics as shown in FIGS. 16A and 16B can be used.

The constant current source shown in FIG.
It is composed of NMOS QNs 60-62. That is, the constant current sources include the NMOS QN60, the NMOS QN61 having the source and drain connected to the NMOS QN60, the NMOS QN60.
60 includes a drain and gate 60 and an NMOS QN 62 to which the gate is connected. And NMOS QN60, N
The MOS QN 61 has a gate and a drain connected to each other, and the drain of the NMOS QN 62 is connected to a load resistor R.

Here, NMOS QN60 and NMOS QN6
The NMOS QN 62 is formed under the same manufacturing conditions and the same layout rule. That is, the current amplification factors of the NMOS QNs 60 to 62 are, for example, β, the gate width and the gate length are the same, and the threshold voltage is, for example, Vthn. Therefore, N
The gate-source voltage VGSN 62 of the MOS QN 62 is a voltage corresponding to the series connection of the NMOS QN 60 and the NMOS QN 61, and is 2 Vthn, which is twice the threshold voltage Vthn.

By using such a constant current source, the constant voltage control NMOSs QN1 and PMOS QP1 can be operated in the saturation region.
And the oscillation stop voltage Vsto can be made the same in temperature characteristics. In addition, in the manufacturing process of the constant voltage generating circuit, it is not necessary to separately form a depletion PMOS (DPMOS). This is advantageous in the manufacturing process.

[0164]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an embodiment of a constant voltage control circuit according to the present invention.

FIG. 2 is a block diagram showing details of an operation stop monitor circuit of the constant voltage control circuit of FIG. 1;

FIG. 3A is a timing chart showing an output waveform in a frequency divider of the operation monitor circuit of FIG. 2;
FIG. 2B is a timing chart showing the relationship between the input and output of the clock detection circuit of FIG.

FIG. 4 is a circuit diagram showing details of a clock detection circuit of the operation stop monitor circuit of FIG. 2;

FIG. 5 is a circuit diagram showing details of a constant voltage generation circuit of the constant voltage control circuit of FIG. 1;

FIG. 6 is a circuit diagram showing further details of the circuit diagram of FIG. 5;

7 is an output φ of a frequency control unit of the constant voltage control circuit of FIG.
₆ is a timing chart showing changes over time of _n1 and _φn2 .

FIG. 8 is a circuit diagram showing an example of another embodiment of the constant voltage control circuit according to the present invention.

FIG. 9 is a circuit diagram showing an example of another embodiment of the constant voltage control circuit according to the present invention.

FIG. 10 is a circuit diagram showing an example of another embodiment of the constant voltage control circuit according to the present invention.

FIG. 11 is a circuit diagram showing an example of another embodiment of the constant voltage control circuit according to the present invention.

FIG. 12 is a circuit diagram showing an example of another embodiment of the constant voltage control circuit according to the present invention.

FIG. 13 is a block diagram showing an example of another embodiment of the constant voltage control circuit according to the present invention.

FIG. 14 is a block diagram showing a clock circuit including a constant voltage control circuit according to the present invention.

FIG. 15 is a block diagram showing an electronic device including the constant voltage control circuit according to the present invention.

FIG. 16 is a schematic diagram showing an example of a constant current source in a constant voltage generating circuit of the constant voltage control circuit according to the present invention, where (a) shows a constant current source TN, and (b) shows a constant current source TP. Show.

FIG. 17 is a schematic diagram showing an example of a constant current source TN in the constant voltage generation circuit of the constant voltage control circuit according to the present invention.

FIG. 18 is a circuit diagram schematically showing a conventional constant voltage generation circuit.

FIG. 19 is a graph showing temperature characteristics of Vreg and oscillation stop voltage Vsto of a conventional constant voltage generation circuit, where | Vreg |
It is a graph which shows about the relationship between temperature and voltage regarding |.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 constant voltage control circuit 10 constant voltage generation circuit 20 monitoring means 22 control means 30 operation monitoring circuit 36 level shifter 40 clock detection circuit 50 differentiation circuit 60 up / down counter 90 crystal oscillation circuit 330 clock circuit

Claims (13)

[Claims] 1. An operation circuit that operates at a constant voltage,
A constant voltage control circuit that controls the constant voltage that fluctuates so as not to reach an operation stop voltage of the operation circuit, wherein at least one first voltage supplied to the operation circuit and the first voltage Constant voltage generating means for generating and outputting a second voltage that varies together with the absolute value of the first voltage, monitoring means for monitoring a change in the second voltage, When the monitor means detects that the operation stop voltage of the monitor means has been reached, the first voltage of the constant voltage generation means is controlled so that the first voltage does not reach the operation stop voltage of the operation circuit. A constant voltage control circuit, comprising: control means for performing change control. 2. An operation circuit operating at a constant voltage,
A constant voltage control circuit that controls the constant voltage that fluctuates, a constant voltage generation unit that generates and outputs a first voltage supplied to the operation circuit; a monitoring unit that monitors the first voltage; And control means for changing and controlling the first voltage of the constant voltage generation means based on a detection result of the monitor means, wherein the monitor means stops operating before the operation circuit stops. A constant voltage control circuit characterized by the above. 3. The operation circuit according to claim 2, wherein the operation circuit has a first transistor, and the monitor has a threshold having an absolute value higher than the absolute value of the threshold of the first transistor. A constant voltage control circuit comprising two transistors. 4. The operation circuit according to claim 2, wherein the operation circuit includes a first transistor, and the monitoring unit includes a second transistor having a current amplification factor smaller than a current amplification factor of the first transistor. A constant voltage control circuit comprising: 5. The constant voltage control circuit according to claim 2, wherein said monitor means includes a logic element having a larger number of input stages than a logic element formed in said operation circuit. 6. The apparatus according to claim 1, wherein the monitor means includes a monitor circuit that outputs an operation stop signal when the operation is stopped based on a reference signal and the second voltage being monitored. Constant voltage control circuit. 7. The monitor circuit according to claim 2, wherein said monitor means outputs an operation stop signal at the time of operation stop based on a reference signal and said first voltage being monitored. A constant voltage control circuit comprising: 8. The apparatus according to claim 6, wherein the control unit includes: a first pulse generation unit configured to output at least one first pulse based on the operation stop signal output from the monitor circuit; A second pulse generating means for generating a second pulse having a predetermined cycle; and a signal for increasing the first voltage based on one of the first pulses is output to the constant voltage generating means. And a pulse control means for outputting a signal for sequentially lowering the first voltage to the constant voltage generation means based on the second pulse having a constant period, comprising: A constant voltage control circuit which controls so as to sequentially decrease at a constant cycle and increase by stopping operation of the monitor circuit. 9. The constant voltage control circuit according to claim 1, wherein the operation circuit and the monitor are circuits formed in the same manufacturing process. 10. The control device according to claim 1, wherein the control unit changes the first voltage at a first cycle when the power is turned on, and the first voltage during a normal operation. To vary the first voltage in a second cycle longer than the cycle of
A constant voltage control circuit, comprising: a monitor cycle control unit that controls switching between the first and second cycles. 11. A constant voltage generating means connected to an operation circuit operating at a constant voltage and supplying a voltage to the operation circuit; a monitoring means for reaching an operation stop voltage to stop operation before the operation circuit; Control means for controlling the operation circuit so as not to reach the operation stop voltage based on the stop of the operation of the monitor means. 12. A semiconductor device wherein an operation circuit and a constant voltage control circuit according to claim 1 for forming a supply voltage to said operation circuit are formed on the same substrate. . 13. A portable electronic device including the constant voltage control circuit according to claim 1.