JP2001298326A - Oscillation circuit, electronic circuit, semiconductor device, electronic equipment and clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit which can be driven with small power consumption. SOLUTION: An oscillation circuit 10 is provided with a control circuit 200 for controlling the source potential of an MOSFET 18 comprising a signal inverting amplifier 14 while utilizing a substrate bias effect. This control circuit 200 controls the threshold voltage of the MOSFET 18 to become low when turning on the power source of the oscillation circuit and controls the threshold voltage of the MOSFET 18 to become high after the oscillation of the oscillation circuit is stabilized. Thus, the stable oscillation and power consumption reduction of the oscillation circuit are enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an oscillation circuit, an electronic circuit, a semiconductor device, an electronic device, and a timepiece.

[0002]

2. Description of the Related Art Conventionally, watches, portable telephones, computer terminals, etc.
An oscillation circuit using a crystal oscillator is widely used. In such a portable device, it is necessary to save power consumption and extend the life of the battery.

[0003] From the viewpoint of saving power consumption, the present inventor analyzed the power consumption of a portable electronic device, particularly a semiconductor device equipped with an electronic circuit used in a wristwatch. As a result of this analysis, it has been confirmed that in such a semiconductor device, the power consumption of the oscillation circuit portion occupies a larger proportion than other circuit portions. That is, the inventor of the present invention has found that reducing power consumption in an oscillation circuit portion used in a portable electronic device is effective in extending the life of a battery.

An object of the present invention is to provide an oscillation circuit, an electronic circuit, a semiconductor device, an electronic device, and a timepiece that can be driven with low power consumption.

Another object of the present invention is to reduce the influence of variations in the threshold voltage of a transistor included in a signal inverting amplifier of an oscillation circuit, and to realize an oscillation circuit, an electronic circuit, a semiconductor device, an electronic device, and a semiconductor device capable of performing stable oscillation. To provide a clock.

[0006]

To achieve the above object, an oscillation circuit according to the present invention is an oscillation circuit including a signal inversion amplifier and a feedback circuit, wherein a back gate of a transistor constituting the signal inversion amplifier is provided. And a control circuit for controlling a back gate voltage between the sources.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An oscillation circuit according to the present embodiment has a signal inverting amplifier and a crystal oscillator, and inverts a phase of an output signal of the signal inverting amplifier and feeds back the signal to the signal inverting amplifier. And a control circuit for controlling a back gate voltage between a source and a source of the transistor constituting the signal inverting amplifier.

According to this embodiment, the source potential and the back gate potential of the transistor included in the signal inverting amplifier can be made different by actively utilizing the substrate bias effect. Therefore, the threshold voltage of the transistor can be controlled to reduce power consumption during the oscillation operation of the oscillation circuit.

Here, it is preferable to use a field effect transistor as a transistor constituting the signal inverting amplifier.

The transistor constituting the signal inverting amplifier includes a first transistor and a second transistor, and the control circuit adopts a configuration for controlling a back gate voltage of the second transistor. Is preferred.

Further, it is preferable to use a depletion type field effect transistor as the transistor.

Here, when the back gate of the second transistor is set to a predetermined potential,
The control circuit includes a rectifier element circuit connected to a source of the second transistor, a switching element forming a bypass circuit of the rectifier element circuit, and an on / off control of the switching element to form the second transistor. And a switching circuit that selectively switches and controls the back gate voltage in at least two stages.

When the source of the second transistor is set to a predetermined potential, the control circuit includes a rectifier circuit connected to a back gate of the second transistor and a rectifier element. A switching element forming a bypass circuit of the circuit, and a switching circuit that selectively switches and controls the back gate voltage of the second transistor by outputting an on / off control signal to the switching element over at least two stages. It is preferable to form so that

Thus, the threshold value of the second transistor can be selected stepwise by the on / off control of the switching element, and the oscillation circuit can be driven with low power consumption.

A power supply line of the signal inverting amplifier is connected to a first potential side and a second potential side different from the first potential, and the signal inverting amplifier is connected to the first potential side. It is preferable that an oscillation signal having a potential difference between the potential and the second potential is generated.

Thus, the signal inverting amplifier can oscillate stably with a sufficient signal amplitude.

Further, it is preferable that a potential difference between the first potential and the second potential is set to be larger than an absolute value of an oscillation stop voltage of the signal inverting amplifier.

Further, the rectifying element circuit includes a plurality of rectifying elements connected in series in a forward direction, and the switching element forms a bypass circuit of at least one rectifying element among the plurality of rectifying elements. It is preferable to adopt a configuration in which:

In this case, it is more preferable to provide a plurality of the switching elements and form a bypass circuit of the plurality of rectifying elements.

Thus, the voltage drop due to the rectifying element can be selected in multiple stages by the combination of the on / off control of each switching element, and the back gate voltage of the second transistor can be controlled in multiple stages. Therefore, the threshold value of the second transistor can be selected in multiple stages, and low power consumption driving of the oscillation circuit can be performed more effectively.

Here, as the rectifying element, for example, a diode or the like can be used.

Further, the control circuit sets the back gate voltage of the second transistor to a different value between a first period during which the oscillation circuit is activated and a second period during which the oscillation circuit performs stable oscillation operation. Is preferably controlled.

Further, the switching circuit includes a first circuit for activating the oscillation circuit until a given time elapses after the power is turned on.
Operating period detecting means for detecting as a second period during which the oscillation circuit stably performs an oscillating operation after the given period has elapsed, and an absolute value of a threshold voltage of the second transistor. And means for controlling switching of the back gate voltage in at least two stages so that the back gate voltage is large in the first period and small in the second period.

Thus, the oscillation circuit can be reliably started, and the power consumption of the oscillation circuit can be reduced during stable oscillation.

In particular, by employing such a configuration, in a state where the crystal oscillation circuit is oscillating stably, it is not necessary to completely discharge the power charged in the crystal resonator in each charge / discharge cycle. And a stable oscillation state can be maintained. Thus, the power consumption of the entire circuit can be reduced more effectively.

Further, the oscillation circuit is configured to reduce the back gate voltage so that the short-circuit current flowing through the signal inverting amplifier has a value satisfying a condition that the on-state current of the transistor constituting the signal inverting amplifier is larger. Preferably, the selection is performed, and the potential difference between the first potential and the second potential is set to be a minimum voltage.

Thus, the oscillation circuit can perform a more stable oscillation operation.

Further, the electronic circuit of the present embodiment includes the above-described oscillation circuit, and a constant voltage generation circuit that supplies the oscillation circuit with the second potential with respect to the first potential. The voltage generating circuit has one end connected to the first potential side and supplies a constant current, and is formed under the same manufacturing conditions as the second transistor, and has one end connected to the constant current source. And a constant voltage control transistor that outputs a reference voltage for generating a constant voltage of the second potential, the constant voltage control transistor being provided in the constant current path so that the reference voltage is connected to the constant voltage output line side. Input to one terminal,
An operational amplifier in which a given reference voltage is input to the other terminal; and a constant current path provided such that one end is connected to the constant voltage output line, and the output of the operational amplifier is input to the gate to thereby obtain a resistance value. And an output transistor for controlling the potential of the constant voltage output line to a constant voltage of the second potential.

By doing so, the temperature characteristic of the constant voltage output from the constant voltage generation circuit can be made similar to the temperature characteristic of the oscillation stop voltage of the oscillation circuit. As a result,
Even if the absolute value of the constant voltage is set to a small value under the constraint that the absolute value of the constant voltage exceeds the absolute value of the oscillation stop voltage, the oscillation operation of the oscillation circuit can be performed stably. Thus, the absolute value of the constant voltage can be reduced, and the power consumption of the oscillation circuit can be further reduced.

Further, by adopting such a configuration, the variation of the threshold voltage of the transistor of the signal inversion amplifier due to the management of the manufacturing process or the like can be compensated by the constant voltage control transistor. Therefore, the yield of the semiconductor device can be improved.

The semiconductor device according to the present embodiment includes the above-described oscillation circuit or electronic circuit. The electronic apparatus according to the present embodiment includes the above-described oscillation circuit, electronic circuit, or semiconductor device. And generating an operation reference signal from an oscillation output of the oscillation circuit.

The timepiece of the present embodiment includes the above-described oscillation circuit, electronic circuit or semiconductor device, and is characterized in that a timepiece reference signal is formed from the oscillation output of the oscillation circuit.

In the electronic device and the timepiece of the present embodiment, low power consumption can be achieved while ensuring stable operation of the circuit.

[0034]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

<Analysis of the Prior Art> Prior to the description of the embodiments of the present invention, the present inventor has conducted analysis of portable electronic devices, particularly an electronic circuit used in a wristwatch, from the viewpoint of saving power consumption. The results of power consumption analysis will be described.

According to this analysis, it was confirmed that, of the electronic circuits formed on the printed circuit board, the power consumption of the oscillation circuit portion occupied a larger proportion than other circuit portions.
That is, it has been found that reducing power consumption in an oscillation circuit portion of an electronic circuit used in a portable electronic device is effective in extending the life of a battery used.

Further, according to this analysis, when the power supply voltage itself is lowered for lower power consumption, the influence of the variation in the threshold voltage of the MOSFET included in the signal inverting amplifier increases, and the oscillation operation of the oscillation circuit may be defective. A problem has been identified that is more likely to cause problems.

The details will be described below.

Conventional Circuit FIG. 14 shows an example of a conventional crystal oscillation circuit 10 and a constant voltage generation circuit 100.

The crystal oscillation circuit 10 includes a signal inverting amplifier 14 and a feedback circuit. The feedback circuit includes the crystal oscillator 12, a resistor R
f, the capacitor C _D for phase compensation, is configured to include a C _G, the drain output of the signal inversion amplifier 14, the inverting amplifier as a gate input which is 180 degrees out of phase inversion 14
Feedback input to the gate of.

The signal inverting amplifier 14 includes a pair of P-type field effect transistors (hereinafter, referred to as PMOSFET) 1
6, an N-type field effect transistor (hereinafter referred to as NMOSFET) 18. And the signal inverting amplifier 14
Are respectively a first potential side and a second voltage of a lower voltage.
And is driven by receiving power supply by the potential difference between the two potentials. Here, the first potential is a ground voltage V
dd, and the second potential is set to a negative constant voltage Vreg.

In the crystal oscillation circuit 10 having the above configuration, when a constant voltage Vreg is applied to the signal inverting amplifier 14, the output of the signal inverting amplifier 14 is inverted by 180 degrees and fed back to the gate. Thereby, the PMOSFET 16 and the NMOS FE constituting the signal inverting amplifier 14 are
T18 is alternately turned on and off, the oscillation output of the crystal oscillation circuit 10 gradually increases, and finally the crystal oscillator 12 performs a stable oscillation operation.

First Point of View In the crystal oscillation circuit 10, the PMOSF is always used even after stable oscillation.
The ET 16 and the NMOSFET 18 are alternately turned on and off. At this time, in the conventional circuit, the PMOSFET 1
When the LED 6 is turned on, most of the energy charged in the crystal unit 12 is discharged as it is. Therefore, in the next charging cycle, the crystal unit 12 must be charged from the beginning.

That is, when the crystal oscillation circuit 10 is oscillating stably, a stable oscillation state is maintained without completely discharging the power charged in the crystal oscillator 12 in each charge / discharge cycle. be able to. However, in the conventional circuit, the crystal oscillator 1
The cycle of discharging the charging power of No. 2 as it is and charging it again was repeated.

The present inventor has found that this has been a major factor in increasing the power consumption of the entire circuit.

Second point of view Further, in the conventional circuit, the present inventor has found that the constant voltage Vreg supplied to the oscillation circuit 10 and the oscillation stop voltage Vs
It has been found that the difference in each temperature characteristic of “to” is a major factor that hinders the low power consumption of the oscillation circuit 10.

That is, the threshold voltage of the NMOSFET 18 is Vthn, and the threshold voltage of the PMOSFET 16 is Vtn.
Assuming that hp, the absolute value | Vsto | of the oscillation stop voltage of the crystal oscillation circuit 10 shown in FIG. 14 can be expressed by the following equation. | Vsto | = K · (| Vthp | + Vthn) (1)

The constant K is 0.8 to 0.9. As is clear from the above equation (1), the oscillation stop voltage Vsto is
The threshold voltage Vthn of the NMOSFET 18 and the PMO
It depends on the threshold voltage Vthp of the SFET 16.

On the other hand, the constant voltage generation circuit 100 includes a constant current source 110, an operational amplifier 112, and a constant voltage control NMOS.
It is configured to include an FET 114 and an output NMOSFET 116.

The constant current source 110 is provided on a constant current path 150 having one end connected to the ground potential Vdd side and the other end connected to the power supply Vss side, and constantly supplies a predetermined constant current ID to the constant current path 150. To supply. The NMOSFETs 114 and 116 are connected in series to the constant current path 150.

The constant voltage control NMOSFET 114
Is a constant current source 110 and a constant voltage signal output line 1
02 is provided. The gate of the constant voltage control NMOSFET 114 is short-circuited to the drain, and a reference voltage for generating a constant voltage is output to the signal line 101.

The operational amplifier 112 has its plus (hereinafter referred to as +) input terminal receiving the reference voltage via the signal line 101 and its minus (hereinafter referred to as-) input terminal having a predetermined reference voltage Vref. Is entered.
The operational amplifier 112 amplifies and outputs the difference voltage.

The output NMOSFET 116 is provided between the signal output line 102 and the power supply voltage Vss. And this NMOSFET 11
The resistance value of the gate 6 is controlled by inputting the output of the operational amplifier 112 to the gate. As a result, the potential of the output signal line 102 is feedback-controlled to the constant voltage Vreg having the second reference potential.

A constant current ID from the constant current source 110 is supplied to the constant voltage control NMOSFET 114. Accordingly, a potential difference of αVthn11 depending on the threshold voltage Vthn11 of the constant voltage control NMOSFET 114 is generated between the signal line 101 and the output line 102. Therefore, a potential difference of α (Vref + Vthn11) occurs between the output line 102 and the ground potential Vdd.

From this, the output voltage Vreg of the constant voltage generation circuit 100 is equal to the reference voltage Vref and the constant voltage control N
It is understood that the threshold voltage Vthn11 of the MOSFET 114 is affected. That is, the constant voltage | Vreg | is proportional to the voltage (Vref + Vthn11). Therefore, the crystal oscillation circuit 10 having the conventional configuration operates using the constant voltage Vreg depending on the voltage (Vreg + Vthn11) as a power supply.

However, such a constant voltage generating circuit 100
Is a threshold voltage Vthn1 of the constant voltage control NMOSFET 114 in a semiconductor manufacturing process as a manufacturing process thereof.
The value of 1 often varies. In the conventional circuit, for example, even if the threshold voltage Vthn11 increases due to this variation, the constant voltage output from the line
| Vreg | also increases at the same time. Therefore, the relation of | Vreg |> | Vsto | is always maintained between the constant voltage Vreg and the oscillation stop voltage Vsto. Therefore, in the conventional circuit, the oscillation circuit 10
This has the advantage that the oscillating operation can be ensured and the yield of IC can be improved.

However, for the low power consumption operation of the oscillation circuit 10, it is necessary to lower the constant voltage | Vreg | as much as possible while satisfying the condition of ensuring the oscillation operation (| Vreg |> | Vsto |). However, to lower the constant voltage | Vreg |
If the constant current ID supplied from the constant current source 110 is reduced, there arises a problem that the generated constant voltage Vreg greatly changes due to a change in the constant current due to a temperature change.

Hereinafter, this temperature characteristic will be described in detail.

In the constant voltage generation circuit 100, a constant current source 110 for operating a constant voltage control NMOSFET 114
Has a temperature dependency. That is, the constant current source 110 is, for example, a depletion type P
When configured using MOSFETs, the constant current ID
Can be expressed by the following equation. Here, the current amplification factor of the depletion PMOSFET constituting the constant current source is β, the absolute value of the threshold voltage is | Vth |
The source-to-source voltage is VGS. ID = (1/2) .beta. (VGS- | Vth |) ² ... (2)

In the PMOSFET, since the gate and the source are short-circuited to form a constant current, the VGS becomes 0V. Substituting this condition into equation (2) gives
The following equation is obtained. ID = (1/2) · β · (−Vth) ² (3)

As shown in the equation (3), the constant current ID
Does not depend on the power supply voltage Vss. However, the constant current ID
Is proportional to the temperature-dependent current amplification factor β and the square of the threshold voltage Vth. Therefore, it will be understood that the value of the constant current ID also varies with the temperature change.

FIG. 15 shows the temperature characteristics of the NMOSFET 114 included in the constant voltage generation circuit 100. In the figure, the vertical axis represents the constant current I supplied by the constant current source 110.
D, the horizontal axis represents the gate-source voltage V GS of MOSFET 114. Here, three types of curves A to C are shown. Curve A indicates that when the threshold voltage Vthn11 of the NMOSFET 114 is low, curve C indicates that the threshold voltage Vthn1
When 1 is high, the curve B indicates that the threshold voltage Vthn11 is A
9 shows a characteristic curve in the case of being intermediate between C and C. That is, as can be seen from these characteristic curves, VGS of the constant voltage control NMOSFET 114 is
Changes due to the fluctuation of the constant current ID supplied by.

Therefore, the constant voltage Vreg is applied to the constant current source 110
, The threshold voltage Vthn11 of the NMOSFET 114, and the reference voltage Vref.

On the other hand, the oscillation stop voltage Vsto varies depending on the temperature change of the threshold voltage Vthn of the NMOSFET 18 and the threshold voltage Vthp of the PMOSFET 16 because the oscillation stop voltage Vsto depends on the above-mentioned equation (1).

As described above, the temperature characteristics of the constant voltage Vreg are as follows.
It depends on the amount of change in the constant current ID and the amount of change in the voltage (Vref + Vthn11). On the other hand, the temperature characteristic of the oscillation stop voltage Vsto depends on the amount of change in the threshold voltage (| Vthp | + Vthn). Therefore, it will be understood that the temperature characteristics (temperature coefficients) of the constant voltage Vreg output from the constant voltage generation circuit 100 and the oscillation stop voltage Vsto of the oscillation circuit 10 are different.

FIG. 16 shows an example in which the constant voltage Vreg and the oscillation stop voltage Vsto have different temperature characteristics.
Here, the relationship between the constant voltage | Vreg | and the temperature of the oscillation stop voltage | Vsto | is shown. In the figure, the horizontal axis represents the temperature T, and the vertical axis represents each voltage V of the constant voltage Vreg and the oscillation stop voltage Vsto.
Are shown respectively.

In order to ensure the oscillating operation of the oscillating circuit 10, the highest temperature t in the guaranteed operating temperature range shown in FIG.
Also in a, the condition of | Vreg |> | Vsto | must be ensured. Here, the temperature ta is, for example, an upper limit temperature for a known heat resistance test of a wristwatch.

However, when such conditions are set, V
Since the temperature gradient between reg and Vsto is different, at the lowest temperature tb in the operation guaranteed temperature range, the constant voltage |
Vreg | is inevitably increased more than necessary, and as a result, there is a problem that wasteful power is consumed.

That is, in the conventional constant voltage generating circuit 100, since the difference between the temperature gradients of the constant voltage Vreg and the oscillation stop voltage Vsto is large, the above-mentioned | When the condition Vreg |> | Vsto | is always satisfied, | Vreg | on the low temperature side (or high temperature side)
However, this becomes a relatively large value with respect to the voltage that guarantees the oscillation operation, and as a result, power is wasted.

As a result of the above analysis, the present inventor has found that it is effective to make the constant voltage Vreg and the oscillation stop voltage Vsto have similar temperature characteristics in order to reduce the power consumption of the circuit. Was.

Third Point of Interest In order to reduce the power consumption of portable electronic devices and watches,
It is effective to lower the power supply voltage itself.

However, when the power supply voltage itself is lowered, the influence of the variation in the threshold voltage of the MOSFETs 16 and 18 included in the signal inverting amplifier 14 increases, and the possibility of causing a problem of the oscillation operation failure of the oscillation circuit 10 increases.

That is, if the power supply voltage itself is lowered, the ratio of the threshold voltage Vth of the MOSFETs 16 and 18 to the power supply voltage Vss becomes large, and it becomes difficult to secure the operation margin of the MOSFET. Therefore, in the manufacturing process of the semiconductor device, if a small error occurs in the impurity implantation when forming the MOSFET, there is a possibility that the yield of the product may be reduced due to the variation of the threshold voltage caused by this.

The inventor of the present invention intends to further reduce the power consumption by developing the oscillation circuit 10 with less oscillation operation failure even if the impurity implantation has a threshold voltage variation caused by a minute error. We focused on that it became possible.

An embodiment of the present invention based on the above points will be described below.

(1) First Embodiment First, a first embodiment will be described.

<Example 1> FIG. 1A shows an example of a crystal oscillation circuit according to the first embodiment. The members corresponding to the circuit shown in FIG. 14 are denoted by the same reference numerals, and description thereof will be omitted.

Oscillation Circuit The crystal oscillation circuit 10 of the present embodiment comprises a signal inverting amplifier 14
And a feedback circuit.

The signal inverting amplifier 14 is connected to a first potential side and a second potential side lower than the first potential side, and is configured to be supplied with power and driven by a potential difference between the two potentials. Here, the first potential is a ground potential Vdd, and the second potential is a second potential.
Is set to the negative power supply potential Vreg supplied from the constant voltage generation circuit 100 described above.

The signal inverting amplifier 14 is a PMOSFE
It is configured to include a T16 and an NMOSFET 18.
The PMOSFET 16 has a source and a drain connected to the ground (Vdd) and the output terminal 11, respectively, and has a gate to which a feedback signal is input.

The NMOSFET 18 has a drain connected to the output terminal 11 (here, the drain of the FET 16) and a source connected to the control circuit 200 described in detail below.
It is connected to the. Further, a feedback signal supplied from a feedback circuit is input to the gate of the NMOSFET 18.

The characteristic configuration of the present embodiment is that a control circuit 200 for controlling the back gate voltage between the back gate and the source of the FET constituting the signal inverting amplifier 14 is provided.

The control circuit 200 of the embodiment is configured to control the back gate voltage of one of the pair of MOSFETs 16 and 18 constituting the signal inverting amplifier 14.

Here, the NMOSFET 18 to be controlled by the back gate voltage is configured so that the constant voltage Vreg supplied from the constant voltage generating circuit 100 is applied to the back gate.

The control circuit 200 controls the NMOS FE
By controlling the potential of the source of T18 in multiple stages, the potential between the source and the backgate of the FET 18 is controlled as a backgate voltage. With this control, the threshold voltage Vthn of the MOSFET 18 is switched and controlled in multiple stages, and as a result, the oscillation circuit 10
It is possible to reduce power consumption at the time of oscillation driving of the device.

The substrate bias effect, which is the basis of the back gate control, will be described below.

Substrate bias The control circuit 200 utilizes the substrate bias effect to
The threshold voltage Vthn of the NMOSFET 18 constituting the signal inverting amplifier 14 is controlled.

When the power of the crystal oscillation circuit 10 is turned on, the back gate voltage expressed as the difference between the source potential and the back gate potential of the NMOSFET 18 is set to a low value close to zero. As a result, in a state where the threshold voltage Vthn of the NMOSFET 18 is set low, the oscillation circuit 10
Starts the oscillating operation.

After the oscillation of the crystal oscillation circuit 10 is stabilized, the control circuit 200 controls the back gate voltage of the NMOSFET 18 to be high. As a result, the oscillation circuit 10 performs an oscillation operation in a state where the threshold voltage Vthn of the NMOSFET 18 is set high.

When the back gate voltage, which is the potential difference between the source potential and the back gate potential of the MOSFET 18, is controlled, the threshold voltage Vthn of the MOSFET 18 changes, and the drain-source current characteristic with respect to the gate-source voltage in the subthreshold region changes. .

For example, when the potential of the back gate is made equal to that of the source,
The off-state current increases as the threshold voltage of the FET decreases. When the potential of the back gate is made different from that of the source, the threshold voltage of the NMOSFET increases and the off-current decreases.

The PMOSFET exhibits similar characteristics. For example, when the potential of the back gate is the same as that of the source, the absolute value of the threshold voltage of the PMOSFET decreases and the absolute value of the off-current increases. When the potential of the back gate is made different from that of the source, the absolute value of the threshold voltage of the PMOSFET increases and the absolute value of the off-current decreases.

By utilizing this characteristic, for example, MOSFET
Is formed so as to have a sub-threshold region characteristic by lowering the absolute value of the threshold voltage. That is, by setting the source and the back gate to the same potential, the absolute value of the threshold voltage of the MOSFET is reduced, and more current flows between the drain and the source. Thereby, MOSF
The speed of the switch control of the ET and the drive capability are improved, and the semiconductor device can operate at high speed.

Conversely, by applying a voltage to the back gate of the MOSFET, the absolute value of the threshold voltage of the MOSFET can be increased and the absolute value of the off-state current can be extremely reduced. Further, when the characteristics are changed to a state where the absolute value of the threshold voltage of the MOSFET is high, the standby current can be extremely reduced, and the power consumption of the semiconductor device can be reduced.

Here, the following expression (4) is given as an expression representing the substrate bias effect. Equation (4) expresses an increase in the absolute value of the threshold voltage for the enhancement-type MOSFET. Here, equation (4)
K represents a constant, φf represents Fermi potential of the substrate, C ₀ represents gate capacitance, and V _BG represents a potential difference (back gate voltage) between the back gate and the source. According to this equation (4),
It can be seen that the threshold voltage increases as the back gate voltage V _BG increases. {K ・ (2φf + V _BG )} ^1/2・ 1 / C ₀ (4)

Next, a specific example of the control circuit 200 will be described.

The control circuit 200 according to the embodiment includes a MOSFET
18 includes a rectifying element circuit 202 connected to the rectifying element circuit 202 and a bypass circuit 204 of the rectifying element circuit 202. The control NMOSFET 210 serving as a switching element provided in the bypass circuit 204 is turned on and off, so that the transistor 18 Is selectively set in at least two stages.

The rectifying element circuit 202 according to the embodiment has the FET1
8 and a diode 212 provided in a forward direction between the source 102 and the line 102 supplying the constant voltage Vreg. The bypass circuit 204 includes a control NMOSFET connected in parallel with the diode 212.
210. The FET 210 is configured such that a selection signal SEL1 is input to a gate thereof and is selectively turned on / off.

FIG. 1B shows an operation timing chart of the crystal oscillation circuit 10 of the embodiment.

When power is supplied to the crystal oscillation circuit 10, H
The level selection signal SEL1 is output and the control NMOS
The FET 210 turns on. As a result, the source of the FET 18 to be controlled is short-circuited to the output line 102. As a result, the potential difference between the source and the back gate of the FET 18 is controlled to zero, that is, the back gate voltage is controlled to zero.

As a result, the threshold voltage Vthn of the FET 18 constituting the signal inverting amplifier 14 is set small,
Since the off-leak current increases, a large amount of current flows between the source and the drain, and the absolute value | Vsta | of the oscillation start voltage decreases. Therefore, the signal inverting amplifier 14 easily starts its oscillating operation, and quickly rises to a stable oscillating state.

When the oscillating operation of the signal inverting amplifier 14 is stabilized, the selection signal SEL1 is switched to the L level. As a result, the FET 210 is turned off, so that the source of the FET 18 is connected to the line 102 via the diode 212.

As a result, the current flowing from the ground potential Vdd side to the signal inverting amplifier 14 flows from the source of the FET 18 through the diode 212 to the line 102.
Flows towards When the current passes through the diode 212, the source potential of the FET 18
At the absolute value by the forward voltage drop Vf. As a result, the threshold voltage Vthn of the NMOSFET 18 is set high, and the off-state current is reduced. That is, under the influence of the forward voltage drop Vf of the diode 212, the potential difference of the voltage applied between the source and the back gate of the NMOSFET 18 becomes the forward voltage drop Vf of the diode 212. As a result, the back gate voltage increases, the threshold voltage Vthn of the FET 18 is set high,
As a result, the off-leak current in the FET 18 decreases,
The source-drain current can be reduced. Thus, the discharge of the energy stored in the crystal resonator is effectively suppressed, and the oscillation circuit 10 can oscillate stably with low power consumption.

As described above, according to the present embodiment, when power is supplied to the crystal oscillation circuit 10, the signal inverting amplifier 14
The oscillation operation can be easily started by lowering the absolute value | Vsta | of the oscillation start voltage at the time of, and after the stable oscillation operation is started, the energy stored in the crystal unit 12 is efficiently used to reduce the power consumption. Thus, the oscillation operation can be continued.

Switching circuit Next, a switching circuit 300 for forming the selection signal SEL1
Will be described.

FIG. 2A shows a functional block diagram of the switching circuit 300, and FIG. 2B shows a timing chart thereof.

The switching circuit 300 according to the embodiment includes a frequency dividing circuit 31.
0, a clock timer setting circuit 320 and a power-on detection circuit 330.

The power-on detection circuit 330 comprises a capacitor C1, a resistor R1, and a CMOS signal inverting amplifier 306.

The capacitor C1 and the resistor R1 are connected in series, and have a ground voltage Vdd, a power supply voltage Vss
Is applied.

Therefore, as shown in FIG. 2B, when the power supplies VSS and Vreg are turned on, the crystal oscillation circuit 10 and the switching circuit 300 are activated. Simultaneously with the power-on, in the power-on detection circuit 330, a current flows from the ground potential Vdd side to the power supply potential Vss side via the capacitor C1 and the resistor R1. That is, immediately after the power is turned on, the potential of the line 105, which has been the ground potential Vdd, gradually decreases as the charging of the capacitor C1 proceeds, and approaches the potential of the power supply Vss.

Accordingly, the signal inverting amplifier 306 outputs a power supply voltage input detection signal having the potential of VSS from the line 106 immediately after the power is supplied, and when the potential of the line 105 falls below a predetermined reference value, the output potential of the line 106 is reduced. The output is switched from VSS to the ground potential Vdd.

The clock timer setting circuit 320
Is set when a power-on detection start signal of the potential Vss is input via the line 106. And
The H-level selection signal SEL1 is supplied to the
Output to the gate of 210.

As a result, the FET 210 is turned on, and the back gate voltage of the FET 18 constituting the signal inverting amplifier 14 is set to zero. Therefore, as described above, the oscillation circuit 10 quickly rises to a stable oscillation state.

As described above, when the crystal oscillation circuit 10 starts oscillating, the oscillation output output from the output terminal 11 is input to the frequency dividing circuit 310. At this time, assuming that the frequency of the oscillation output of the oscillation circuit 10 is, for example, 32 kHz, the frequency divider 310 divides this clock signal into a predetermined frequency, for example, 1 Hz, and divides the frequency-divided output into a clock timer set circuit. 320.

As described above, the clock timer set circuit 320 is set when the signal of the potential of VSS is input from the signal line 106, and is ready to receive the divided output output from the frequency dividing circuit 310. Is controlled. Therefore, when a clock signal divided at a frequency of 1 Hz is input from the frequency dividing circuit 310, the clock timer set circuit 320 counts the frequency-divided clock signal, and the count value reaches a predetermined value. At this point, the level of the selection signal SEL1 is switched from H level to L level.

As a result, the oscillation circuit 10 of FIG. 1A, in particular, the FET 210 included in the control circuit 200 is turned off, and the above-described back gate voltage of Vf is applied between the source and the back gate of the FET 18. As a result, as described above, the threshold voltage of the FET 18 is set high, so that the oscillation circuit 10 is controlled to switch to the low power consumption type stable oscillation state.

Modification FIG. 3A shows a modification of the oscillation circuit 10 of the first embodiment, and FIG. 3B shows an operation timing chart thereof. The oscillation circuit 10 according to this modification includes a control circuit 20
It is characterized in that the connection relationship between 0 and the NMOSFET 18 is changed.

In the oscillation circuit 10, the source of the FET 18 is connected to the line 102 to which the constant voltage Vreg is supplied.

Further, the rectifying element circuit 202 and the bypass circuit 204 constituting the control circuit 200 are connected to the FET 1
8 and the power supply potential VSS. The power supply potential VSS used here is a negative potential, and its absolute value | VSS | is set to a value larger than the absolute value | Vreg | of the constant voltage.

The control NMOSFET 210
By applying the selection signal SEL2 to the gate of the FET 18, the FET 210 is selectively turned on / off, and the back gate potential of the FET 18 is controlled to be switched in multiple stages. Accordingly, the same operation and effect as those of the first embodiment can be obtained.

Note that the selection signal SEL2 generated by the circuit shown in FIG.
May be further inverted using a signal inverting amplifier.

Further, in the above embodiment, the start of stable oscillation of the crystal oscillation circuit 10 is detected by counting the clock signal by the clock timer set circuit 320.
The case where the voltage level of the selection signal is switched has been described as an example. However, this clock timer set circuit 320
, The voltage level of the selection signal may be switched by the power-on detection circuit 330. For example, the size of the capacitor C1 and the resistance R1 of the power-on detection circuit 330 is adjusted, and the power-on detection circuit 33 is adjusted so as to obtain a time constant for securing a time until stable oscillation starts.
0 may be configured.

In the above embodiment, the case where the threshold voltage of one FET 18 included in the signal inverting amplifier is controlled has been described as an example. However, the present invention is not limited to this, and the present invention is not limited to this.
A configuration in which the threshold voltage is similarly controlled by controlling the back gate voltage of the ET 16 may be employed.

<Embodiment 2> FIG. 4 shows Embodiment 2 of the present invention.
1 shows a crystal oscillation circuit 10 according to the first embodiment. Members corresponding to the circuits shown in FIGS. 1, 3, and 14 are denoted by the same reference numerals, and description thereof will be omitted.

Oscillation Circuit 10 The feature of this embodiment is that the control circuit 200 can be used to control the threshold voltage Vthn of the NMOSFET 18 constituting the signal inverting amplifier 14 in three or more stages.

The control circuit 200 includes a rectifying element circuit 202 including two diodes 214 and 212 connected in series in the forward direction, a bypass circuit 204-1 for a series connection circuit of the diodes 214 and 212, and one of them. And a bypass circuit 204-2 for the diode 212 of FIG. Each bypass circuit 204-1 and 204-
2 is turned on / off using control NMOSFETs 216 and 210, respectively.

More specifically, the back gate of the NMOSFET 18 constituting the signal inverting amplifier 14 has a constant voltage V
reg is connected to the supply line 102, the source of which is connected to the anode end of the rectifier element circuit 202 and the bypass circuit 20.
4-1 is connected to one end.

The cathode of the rectifier circuit 202 and the other end of each of the bypass circuits 204-1 and 204-2 are connected to a line 102.

The selection signals SEL20 and SEL10 are applied to the gates of the transistors 216 and 210 functioning as the switching elements, respectively.

With the above configuration, the on / off control of the control NMOSFETs 210 and 216 is performed as a predetermined combination, so that the source potential of the NMOSFET 18, that is, the back gate potential, can be switched over three or more steps.

That is, by turning off both the FETs 216 and 210, the current flowing from the ground potential Vdd side to the power supply line 102 side via the signal inverting amplifier 14 becomes:
After passing through the diodes 214 and 212, a forward voltage drop 2Vf of two diodes is generated. Therefore, at this time, a back gate voltage having a value of 2 Vf is applied to the FET 18.

Further, the FET 210 is turned on, and the FET 1
6 is turned off, the aforementioned current flows through the diode 214,
Flow to the power supply line 102 via the bypass circuit 204-2
It is. Therefore, the voltage drop in the control circuit 200 is
Voltage drop V at Aether 214 _fOnly. Therefore, F
The back gate voltage of ET18 is V_fIs controlled.

Further, the FETs 216 are turned on, and
When 10 is turned off, all the above-mentioned currents are
Since the current flows through the power supply line 102 via the line 04-1, the voltage drop in the control circuit 200 becomes almost zero. Therefore, in this case, the back gate voltage of the FET 18 becomes zero.

As described above, according to the present embodiment,
Selection signals SEL10 and SE supplied to the control circuit 200
By controlling L20, the back gate voltage of the NMOSFET 18 can be arbitrarily selected from three types of voltages, 0, Vf, and 2Vf.
It is possible to selectively control the threshold value of T18 in three steps, and to realize optimal driving of the oscillation circuit 10.

Switching Circuit 300 FIG. 7A shows that the selection signal S is supplied to the oscillation circuit 10 of the second embodiment.
Switching circuit 300 for supplying EL10 and SEL20
FIG. 7B shows a timing chart thereof. The members corresponding to the circuits described above are denoted by the same reference numerals, and description thereof is omitted.

In order to select and switch the source voltage of the NMOSFET 18, the switching circuit 300 of this embodiment includes a logic circuit 350 which outputs the selection signals SEL10 and SEL20.
It is comprised including.

The logic circuit 350 is provided between the clock timer set circuit 320 and the crystal oscillation circuit 10 configured as shown in FIGS. The logic circuit 350 performs a logical operation on the output signal of the clock timer set circuit 320 to select the selection signal S.
EL10 and SEL20 are generated, and these selection signals SE are generated.
L10 and SEL20 through the signal lines 103 and 104 to the control N of the crystal oscillation circuit 10 shown in FIGS.
Input to the gates of the MOSFETs 210 and 216, respectively.

For example, when power is turned on, SEL10, SEL2
0 are both at the H level, and SEL1
It is sufficient that both 0 and SEL20 are at L level.

As described above, the oscillation circuit 10 of this embodiment is
Can select the back gate voltage from three types as described above. As described above, since the number of choices of the back gate voltage increases, it is possible to more flexibly cope with the variation in the characteristics in manufacturing the IC as compared with the first embodiment. For example, it is conceivable that the threshold voltage fluctuates due to manufacturing variations. Even in such a case, an optimum back gate voltage can be selected in correspondence with the threshold voltage.

Next, the criteria for selecting the back gate voltage will be described.

First, the negative constant voltage V of the output line 102
the value of _reg, short current I _s flowing through the signal inversion amplifier 14 is measured. Then, based on the measured value, the back gate voltage during stable oscillation is selected.

[0142] Figure 5 is a signal inversion method of measuring short current I _s flowing through the amplifier 14 is shown in FIG. 6, the oscillation-stopped voltage of the oscillation circuit 10, is shown the relationship between the short current I _s is I have. The relationship shown in FIG. 6 is obtained by taking, as an example, a case where the circuit shown in FIG.

The short-circuit current I of the signal inverting amplifier 14
_As shown in FIG. 5, when a voltage having a potential difference between the ground potential _Vdd and the constant potential _Vreg is applied to the signal inverting amplifier 14 with the common gate and the common drain of the FETs 16 and 18 short-circuited as shown in FIG. _Is measured by measuring the current between V _{dd and} V _reg that flows through.

In order to reduce the power consumption of the crystal oscillation circuit 10, a constant voltage V _reg supplied to the signal inverting amplifier 14 is used.
Of the oscillation circuit 10 must be larger than the absolute value of the oscillation stop voltage V _sto of the oscillation circuit 10, and the above-mentioned condition of making the absolute value of the constant voltage V _reg as small as possible has to be satisfied. .

That is, the value of the constant voltage V _reg applied from the constant voltage generation circuit 100 to the crystal oscillation circuit 10 is FE
It is necessary to set so that the short current Is can be supplied so that the voltage of T16 becomes equal to or higher than the ON voltage, and the absolute value of the constant voltage V _reg becomes the minimum value.

The absolute value | Vreg | of the constant voltage depends on NMOSFET 114 for constant voltage control. Further, the oscillation stop voltage | Vsto |
That is, it is necessary to select a value equal to or lower than the threshold voltage Vthn of the FET 18.

Therefore, in order to reduce power consumption, it is necessary to set the short-circuit current Is and the oscillation stop voltage | Vsto | within the range of region 1 shown in FIG. On the other hand, in order to select a back gate voltage that can realize the signal inverting amplifier 14 that satisfies this condition and that can cope with the constant voltage of the power supply in recent years, the signal inverting amplifier 14 must be in a range where the on / off operation of the MOSFET is compensated. in stable oscillation, moreover so as to be able to flow the least short current I _s to the signal inversion amplifier 14, it is necessary to select the back gate voltage.

That is, according to the above-described measurement result of the short-circuit current IS, the NMOSFET satisfying the condition is satisfied.
18 optimal back gate voltages are set to 0, Vf, 2V
By selecting from among f, the power consumption of the crystal oscillation circuit 10 can be reduced.

The measurement of the short-circuit current IS is as follows.
In the inspection step C, before the crystal unit 12 is mounted on the substrate, the test circuit is connected to the NMOSFET 18 included in the signal inverting amplifier 14 using a test circuit (not shown) and a test pad P connected to the test circuit. This is performed by supplying each of the back gate voltages. At this time, the short current Is flowing through the signal inverting amplifier 14 is
Is measured. Based on this measurement result, to identify the back gate voltage flows range a and the lowest short current I _s on-off operation is compensated for FET 18.

The IC test is performed on a wafer. The short-circuit current is measured for each IC chip using a test circuit and a test pad provided in each IC chip. At this time,
The test is performed by the signal inverting amplifier 14 and the control circuit 20.
This is performed with only 0 being active and the other elements being inactive.

Incidentally, one or more test pads P are provided according to the number of select signals and the logic of the test circuit. The test circuit has a combination of a voltage level of an input signal to the test pad P,
By combining the output voltage levels of the selection signals SEL10 and SEL20, the three types of back gate voltages are selected. The measurement of the short current I _s is the respective selection signals SEL10, SEL20 is performed in a state that is input as a union of different voltage levels. The ground voltage Vdd and the constant voltage Vreg are applied to the signal inverting amplifier 14 by applying the constant voltage Vreg using the monitoring pad MP connected to the output line 102.

After the measurement of the short current Is, the optimum back gate voltage among the voltages 0, Vf, and 2Vf is specified, and the selection signals SEL10 and SEL20 corresponding thereto are specified.
Specify the signal level of

During stable oscillation, the logic circuit 350 selects the specified level of the selection signals SEL10, SE
L20 is output.

At the time of startup, the logic circuit 350 selects the selection signals SEL10, SEL10 set at a level such that a lower back gate voltage is applied to the FET 18 than at the time of stable oscillation.
Outputs EL20.

In the crystal oscillation circuit 10 according to the second embodiment,
Although the number of diodes for controlling the back gate voltage of the NMOSFET 18 has been described as two, the present invention is not limited to this. Rectifier elements such as three or more diodes are connected in series to form a rectifier element circuit 202. May be formed.

Modification FIG. 8 shows a modification of the second embodiment. In the oscillation circuit 10 according to this modification, the source of the FET 18 is connected to the line 102 to which the constant voltage _Vreg is supplied.

Then, one end of the control circuit 200 is connected to an FET.
18 and a power supply V at the other end.
Connect to _ss supply line side.

Then, the control FETs 210, 216
Are selectively turned on and off to control the back gate potential of the FET 18 in multiple stages.

As a result, the same functions and effects as in the second embodiment can be obtained.

<Verification of Oscillation Operation> FIG. 9 shows the FET 18 included in the signal inverting amplifier 14 shown in the first and second embodiments.
3 shows the back gate control characteristic of the first embodiment. In the figure, the horizontal axis represents time, and the vertical axis represents the gate waveform and the drain waveform of the FET 18, respectively.

Assuming that the optimal back gate voltage is supplied to the FET 18 of the signal inverting amplifier 14, the crystal oscillation circuit 10 amplifies and outputs the gate input with the optimal driving capability of the signal inverting amplifier 14. At this time, the drain output of the FET 18 has a phase of 180 with respect to the gate input.
Inverted.

[0162] The drain capacitance C _D cuts the harmonic components, and outputs only the oscillation frequency component selectively acts as a filter for harmonic oscillation prevention. Resistance Rf, drain capacitance C _D, the crystal resonator 12, the feedback circuit including the gate capacitance C _G functions the phase of the drain waveform to reverse 180 degrees.

As described above, it has been confirmed that the signal inverting amplifier 14 of the crystal oscillation circuit 10 according to the first and second embodiments performs the oscillation operation with the threshold voltage of the FET 18 being optimally controlled by the back gate voltage. Was. It was confirmed that the oscillation circuits 10 shown in the first and second embodiments can not only achieve low power consumption but also obtain stable oscillation output characteristics.

<Embodiment 3> FIG. 10 shows a preferred embodiment of the constant voltage generating circuit 100 used in the crystal oscillation circuit 10 of the present invention. It should be noted that FIGS.
The same reference numerals are given to members corresponding to the circuit shown in FIG. 4 and description thereof is omitted.

The present embodiment is characterized in that the constant voltage generation circuit 100
And the NMOSFET 18 included in the signal inverting amplifier 14 are formed under the same manufacturing conditions. This allows
The threshold voltage Vthn1 of the constant voltage control NMOSFET 114
1 and the threshold voltage Vthn of the NMOSFET 18 have the same value in design.

That is, the constant voltage control NMOS FE
At the time of impurity implantation at the time of forming T114 and NMOSFET 18, by controlling the impurity concentration, both F
The ETs 114 and 18 can be formed under the same manufacturing conditions.

The temperature coefficient of the first constant voltage Vreg is (Vref +
Vthn11), and the temperature coefficient of the absolute value | Vsto | of the oscillation stop voltage depends on | Vthp | + Vthn. In this embodiment,
As described above, the threshold voltage Vthn11 is equal to the threshold voltage Vt.
Since it has a strong correlation with hn, the temperature coefficient of the first constant voltage Vreg can be expressed as (Vref + X · Vthn) (where X is a coefficient). Therefore, the first constant voltage Vreg,
The temperature characteristics of the absolute value | Vsto | of the oscillation stop voltage can be made the same.

The constant voltage generating circuit 100 supplies the negative first constant voltage Vreg having such characteristics to the NMOSFET 1
8 sources. The NMOSFET 18 has its back gate having an absolute value equal to the first constant voltage Vre.
g second negative constant voltage V _ss (| V _ss |
> | Vreg |), the threshold voltage Vt
hn is configured to be controlled. Thus, the threshold voltage Vthn of the constant voltage control NMOSFET 114 is
11 and the threshold voltage Vthn of the NMOSFET 18 can be offset.

That is, the threshold voltage Vthn of the NMOSFET 18 depends on the voltage applied to the source of the NMOSFET 18 and the voltage applied to the back gate.
Here, the back gate voltage V of the NMOSFET 18
_BG is as shown in equation (5). V _BG = | V _ss | − | Vreg | (5)

As described above, | Vreg | = | Vref | + Vth
Since it is n11, the above equation (5) can be rewritten as the following equation (6). V _BG = | V _ss | − | Vref | −Vthn11 (6)

Therefore, the constant voltage control NMOSFET
The variation of the threshold voltage Vthn11 of the NMOS 114
It is understood that the threshold voltage Vthn of the NMOSFET 18 fluctuates due to the influence on the back gate voltage V _BG of the ET 18.

However, the NMOSFET 18 and the constant voltage control NMOSFET 114 are NMOSFETs formed under the same manufacturing conditions. Therefore, the threshold voltage Vthn11 of the constant voltage control NMOSFET 114 is
, The variation of the threshold voltage Vthn of the NMOSFET 18 can be canceled. For example, when the threshold voltage Vthn11 of the constant voltage control NMOSFET 114 is high, the back gate voltage V _BG
, The threshold voltage Vthn of the NMOSFET 18 decreases. The NMOSF for constant voltage control
If the threshold voltage Vthn11 of ET114 is low, the rise in the back gate voltage V _BG is increased, the N
The threshold voltage Vthn of the MOSFET 18 increases.

FIG. 11 shows a comparative example. In this comparative example, when the source of the NMOSFET 18 is set to the same potential as the back gate, and when the source potential and the back gate potential are different from each other as in the present embodiment, the threshold voltage of the NMOSFET 18 is reduced in terms of manufacturing. Or fluctuate. That is, as a comparative example, an example in which the substrate bias effect is applied and an example in which the substrate bias effect is not applied are shown. 11, the horizontal axis represents the threshold voltage Vthn11 of the constant voltage control NMOSFET 114, and the vertical axis represents the NMOSFET 18 included in the signal inverting amplifier 14.
Of the threshold voltage Vthn.

In FIG. 11, a dotted line A indicates a comparative example in which the substrate bias effect is not applied (N in the circuit of FIG. 14).
MOSFET 18 and NMOSFET 11 for constant voltage control
4 is shown. The solid line B represents the NMOSFET 18 and the constant voltage control NMOSF in the circuit of FIG.
The relationship with ET114 is shown.

As shown in Comparative Example A, when the substrate bias effect is not used, the threshold voltage Vthn of the NMOSFET 18 fluctuates according to the manufacturing variation at the time of impurity implantation in the manufacturing process.

However, in Comparative Example B using the substrate bias effect, it is possible to correct a variation in the threshold voltage in the MOS manufacturing process. Therefore, the NM
Variations in the threshold voltage Vthn in the OSFET 18 are reduced, and the oscillation circuit 10 with stable characteristics is obtained.

In particular, according to the oscillating circuit 10 and the constant voltage generating circuit 100 of this embodiment, the variation in the threshold voltage at the time of manufacturing the IC is automatically canceled without increasing the number of elements, and the stable oscillating operation is achieved. The oscillation circuit 10 that performs the above operation can be realized.

In the circuit shown in FIG. 10, the same operation and effect can be obtained even if the oscillation circuit 10 shown in FIGS. 1A, 2A, 3A, 4 and 8 is used instead of the oscillation circuit 10 shown in FIG. Needless to say, it can be performed.

<Application Example> Next, FIG. 12 shows an example of an electronic circuit used in a wristwatch.

This wristwatch incorporates a power generation mechanism (not shown). When the user wears the wristwatch and moves his arm, the rotating weight of the power generating mechanism rotates, the kinetic energy at that time rotates the power generating rotor at high speed, and an AC voltage is output from the power generating coil 400 provided on the power generation status side. You.

This AC voltage is rectified by the diode 404 and charges the secondary battery 402. This secondary battery 402
Together with the booster circuit 406 and the auxiliary capacitor 408 constitute a main power supply.

When the voltage of the secondary battery 402 is low and less than the driving voltage of the timepiece, the booster circuit 406 converts the voltage of the secondary battery 402 into a high voltage that can be driven by the clock, and stores the voltage in the auxiliary capacitor 408. Then, the clock circuit 440 operates using the voltage of the auxiliary capacitor 408 as a power supply.

The clock circuit 440 includes the oscillation circuit 10 and the constant voltage generation circuit 100 described in any of the above embodiments.
As a semiconductor device. This semiconductor device uses a quartz oscillator 12 connected via a terminal to set a preset oscillation frequency, here 32768 Hz.
Oscillation output of frequency is generated, this oscillation output is divided,
A drive pulse having a different polarity is output every second. This drive pulse is input to the drive coil 422 of the step motor connected to the clock circuit 440. Thereby, the step motor (not shown) drives the rotor to rotate each time the drive pulse is energized, and the second hand, minute hand,
The hour hand is driven, and the time is displayed on the display panel in an analog manner.

Here, the clock circuit 440 of the present embodiment is
The voltage V supplied from the main power supply _ssDriven by
The power supply voltage circuit 420 and the power supply voltage
Voltage generating circuit for generating a predetermined low voltage Vreg
100 and a constant voltage operation driven by this constant voltage Vreg.
FIG. 13 including the operation circuit unit 410
A more detailed functional block diagram of the clock circuit 440 is shown.
I have.

The constant voltage operation circuit section 410 includes a crystal oscillation circuit 10 partially including an externally connected crystal oscillator 12, a waveform shaping circuit 409, and a high frequency dividing circuit 41.
1 is included.

The power supply voltage circuit section 420 includes a level shifter 412, a medium / low frequency dividing circuit 414, and other circuits 416. In the clock circuit 440 according to the present embodiment, the power supply voltage circuit 420 and the constant voltage generation circuit 100 constitute a power supply voltage operation circuit 430 driven by a voltage supplied from a main power supply.

The crystal oscillation circuit 10 includes a crystal oscillator 12
And outputs a sine wave output having a reference frequency fs = 32768 Hz to the waveform shaping gate 409.

The waveform shaping circuit 409 shapes the sine wave output into a rectangular wave, and outputs it to the high frequency frequency dividing circuit 411.

The high frequency divider 411 divides the reference frequency 32768 Hz to 2048 Hz, and outputs the divided output via the level shifter 412.
14 is output.

The medium / low frequency dividing circuit 414
The signal that has been frequency-divided to 8 Hz is further frequency-divided to 1 Hz and input to another circuit 416.

The other circuit 416 includes a driver circuit for energizing and driving the coil in synchronization with the frequency-divided signal of 1 Hz, and drives the clock driving step motor in synchronization with the frequency-divided signal of 1 Hz. I do.

In the timepiece circuit of this embodiment, in addition to the power supply voltage operation circuit section 410 in which the entire circuit is driven by the power supply voltage Vss supplied from the main power supply, a constant voltage operation circuit driven by a low constant voltage Vreg The part 430 is provided for the following reason.

That is, in such a timepiece circuit, it is necessary to reduce its power consumption in order to secure a stable operation for a long time.

Normally, the power consumption of a circuit depends on the signal frequency,
It increases in proportion to the capacity of the circuit and further in proportion to the square of the supply voltage.

Here, focusing on the clock circuit, in order to reduce the power consumption of the whole circuit, the power supply voltage supplied to each part of the circuit may be set to a low value, for example, Vreg.
The constant voltage generation circuit 100 can form the minimum constant voltage Vreg within a range that compensates for the oscillation operation of the crystal oscillation circuit 10.

Next, paying attention to the signal frequency, the clock circuit is roughly classified into a crystal oscillation circuit 10, a waveform shaping circuit 409, a high-frequency frequency dividing circuit 411 having a high signal frequency, and another circuit 410. be able to. As described above, the frequency of this signal is proportional to the power consumption of the circuit.

Therefore, the constant voltage generation circuit 100 of the present embodiment
Generates a constant voltage Vreg lower than the power supply voltage Vss supplied from the main power supply, and supplies the constant voltage Vreg to the circuit unit 410 that handles a high-frequency signal. As described above, by lowering the drive voltage supplied to the circuit 410 that handles the high-frequency signal, the power consumption of the entire timepiece circuit can be effectively reduced without increasing the load on the constant voltage generation circuit 100 significantly. be able to.

As described above, the clock circuit and the electronic circuit including the same according to the present embodiment include the crystal oscillation circuit 10 according to any one of the above embodiments and the constant voltage generation circuit 100 connected thereto. . For this reason, the minimum constant voltage can be supplied to the crystal oscillation circuit 10 while securing the operation margin of the signal inverting amplifier, regardless of the manufacturing variation, so that the power consumption of the electronic circuit and the clock circuit can be reduced. I can do it. Therefore, in the portable electronic device or watch as described above, not only can the oscillation operation be performed stably, but also the life of the battery can be extended, and the usability of the portable electronic device or watch can be improved. Can be improved.

For the above-mentioned reason, even in a watch or a portable electronic device having a built-in silver battery, an operation margin can be ensured even if MOSFETs in manufacturing vary. Further, in a rechargeable wristwatch powered by a lithium ion secondary battery, the M
Even if the OS varies, the operation margin can be secured and the charging time can be shortened.

[Brief description of the drawings]

FIGS. 1A and 1B are a schematic diagram and a timing chart of a crystal oscillation circuit according to a first embodiment.

FIGS. 2A and 2B are a schematic diagram and a timing chart of a switching circuit according to a first embodiment.

FIGS. 3A and 3B are a schematic diagram and a timing chart, respectively, of a crystal oscillation circuit according to a second embodiment.

FIG. 4 is a schematic diagram of a crystal oscillation circuit according to a third embodiment.

FIG. 5 is an explanatory diagram of a method for measuring a short-circuit current of a signal inverting amplifier according to a third embodiment.

FIG. 6 is a graph showing a relationship between an oscillation stop voltage and a short current.

FIGS. 7A and 7B are a schematic diagram and a timing chart of a switching circuit according to a fourth embodiment.

FIG. 8 is a schematic diagram of a variation of the crystal oscillation circuit according to the third embodiment.

FIG. 9 is a schematic diagram showing gate waveforms and drain waveforms of the crystal oscillation circuits of Examples 1 to 4.

FIG. 10 is a schematic diagram illustrating a circuit according to a fifth embodiment.

FIG. 11 is a diagram illustrating a comparison example of data in which the source and the back gate of the NMOSFET have the same potential and data in which the source potential and the back gate potential are different.

FIG. 12 is a functional block diagram of a timepiece to which the present invention is applied.

FIG. 13 is a functional block diagram of a portable electronic device to which the present invention has been applied.

FIG. 14 is a schematic diagram of a conventional crystal oscillation circuit and a constant voltage generation circuit.

FIG. 15 shows a constant voltage | Vreg | and an oscillation stop voltage | V
FIG. 4 is an explanatory diagram of temperature characteristics of sto |.

FIG. 16 is a diagram illustrating an NM used in a constant voltage generation circuit.
FIG. 4 is a characteristic diagram of an OSFET.

[Explanation of symbols]

 Reference Signs List 10 crystal oscillation circuit 11 output terminal 12 crystal oscillator 14 signal inversion amplifier 16 transistor 18 transistor

Claims (5)

[Claims] 1. An oscillator circuit including a signal inverting amplifier and a feedback circuit, the control circuit controlling a back gate voltage between a source and a back gate of a transistor constituting the signal inverting amplifier. 2. An electronic circuit including the oscillation circuit according to claim 1. 3. A semiconductor device comprising the oscillation circuit according to claim 1 or the electronic circuit according to claim 2. 4. An electronic device including the oscillation circuit according to claim 1, the electronic circuit according to claim 2, or the semiconductor device according to claim 3, wherein the electronic device generates an operation reference signal from an oscillation output of the oscillation circuit. 5. A timepiece including the oscillation circuit according to claim 1, the electronic circuit according to claim 2, or the semiconductor device according to claim 3, wherein the timepiece forms a clock reference signal from an oscillation output of the oscillation circuit.