JP2011010478A - Electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus which can effectively use generated power without uselessly reducing an electric power accumulation amount of an electric power accumulating means in an electronic device equipped with a power generating means and the electric power accumulating means.SOLUTION: The electronic device is provided with a first switch (Tr1) separating function circuits (21 and 24) and a capacitor (3) from a solar cell (12) and a secondary cell (2), a second switch (Tr2) separating the secondary cell (2) from the solar cell (12), the capacitor (3) and the function circuits (21 and 24) and a first comparator (CP1) comparing terminal voltage of the secondary cell (2) with that of the capacitor (3). When the terminal voltage of the secondary cell (2) is larger than that of the capacitor (3), the first switch (Tr1) is changed over to an on-state and the second switch (Tr2) to an off-state.

Description

  The present invention relates to an electronic device including a power generation unit and a power storage unit.

  Conventionally, there are electronic timepieces having various power generation functions such as solar power generation, thermal power generation, and self-winding power generation that generates kinetic energy by swinging the device itself. By generating and using the generated power in the secondary battery, the timepiece can be operated even during periods when there is no power generation.

  In addition, as a technology related to the present invention, Patent Documents 1 and 2 provide an auxiliary capacity with a small electric capacity in addition to the secondary battery, so that even if the secondary battery is discharged, power generation is performed next. An electronic timepiece having a quick start function that enables a timepiece to be started quickly by charging the auxiliary capacity and using the voltage when the battery is released.

JP-A-8-36070 JP 11-299125 A

  In an electronic timepiece having a conventional power generation function, a rectifying element is provided between the power generation element and the secondary battery, and current is supplied from the power generation element to the secondary battery during a period when the amount of power generation is large. During a short period, the rectifying element prevents the backflow of current from the secondary battery to the power generation element side.

  Therefore, when the charge level of the secondary battery is relatively high and the power generation amount of the power generation element is slightly low, the voltage of the secondary battery becomes higher than the power generation voltage, and the generation current is supplied by the rectifier element. Is cut off. Therefore, even when sufficient power is generated by this power generation to operate the LSI (large scale integrated circuit) of the watch, no drive current is supplied from the power generation element to the LSI side. There was a problem that the electric power of would be used. In other words, if the generated power is used, it is not necessary to reduce the charge amount of the secondary battery, but the decrease in the charge amount of the secondary battery proceeds because the generated power is not used, and the power of the secondary battery is reduced when the power generation is stopped. There was a problem of expediting exhaustion.

  An object of the present invention is to provide an electronic apparatus that includes a power generation means and a power storage means and that can effectively use generated power without unnecessarily reducing the amount of power stored in the power storage means.

In order to achieve the above object, the invention according to claim 1
Power generation means;
A first power storage means connected in parallel to the power generation means, a second power storage means having a smaller capacity than the first power storage means, and a functional circuit for realizing the function of the device;
A first switch means capable of disconnecting the functional circuit and the second power storage means from the power generation means and the first power storage means by switching from the closed state to the open state;
A second switch means capable of disconnecting the first power storage means from the power generation means, the second power storage means and the functional circuit by switching from the closed state to the open state;
A first comparator for comparing the terminal voltage of the first power storage means and the terminal voltage of the second power storage means;
Logic means for controlling switching between the first switch means and the second switch means based on the output of the one comparator;
With
The logic means is
When the terminal voltage of the first power storage means is larger than the terminal voltage of the second power storage means, the first switch means is switched to the closed state, and the second switch means is switched to the open state.
An electronic device characterized in that when the terminal voltage of the first power storage means is smaller than the terminal voltage of the second power storage means, the first switch means is switched to an open state and the second switch means is switched to a closed state. is there.

According to a second aspect of the present invention, in the electronic device according to the first aspect,
A second comparator for comparing a first threshold voltage, which is a power supply voltage capable of driving the functional circuit, and a terminal voltage of the second power storage unit;
The logic means is
When the terminal voltage of the second power storage means is lower than the first threshold voltage based on the output of the second comparator, the switching control of the first switch means based on the output of the first comparator is canceled, The first switch means is always closed.

According to a third aspect of the present invention, in the electronic device according to the second aspect,
Detecting means for detecting a charge level of the first power storage means;
First control means for switching between stopping and continuing the operation of the first comparator and the second comparator;
The first control means includes
When the charge level of the first power storage means is at a normal use level based on the detection of the detection means, the first comparator and the second comparator are operated, while the charge level of the first power storage means is The operation of the first comparator and the second comparator is stopped when it is at a charge level that limits the discharge of the first power storage means.

The invention according to claim 4 is the electronic device according to any one of claims 1 to 3,
A second control means capable of forcibly switching the first switch means and the second switch means to a closed state;
The second control means includes
The first switch means and the second switch means are forcibly closed when in a predetermined operation mode in which the load of the functional circuit becomes large.

Invention of Claim 5 is an electronic apparatus as described in any one of Claims 1-4,
The first power storage means is a secondary battery;
The second power storage means is a capacitor.

Invention of Claim 6 is an electronic apparatus as described in any one of Claims 1-5,
The functional circuit performs an operation related to the function of the watch.

  According to the present invention, during a period in which the power generation amount of the power generation means is large, both the first power storage means and the second power storage means are charged, while these powers are used to operate the functional circuit, During the period when the power generation amount of the means is small, the discharge of the first power storage means is suppressed, and the functional circuit operates by using the power of the power generation means. Thus, the function circuit can be operated by effectively using the power generation amount of the power generation means without wasting the power storage amount of the first power storage means.

1 is a block diagram showing the entirety of an electronic timepiece according to an embodiment of the present invention. It is a flowchart which shows the control procedure of the switch control process performed by CPU. 3 is a time chart showing state transition between each voltage related to charging and the second latch. It is explanatory drawing showing the switching state of the 1st switch and 2nd switch in a high illumination state. It is explanatory drawing showing the switching state of the 1st switch and 2nd switch in the state of low illumination intensity and zero illumination intensity. It is explanatory drawing showing the switching state of the 1st switch and 2nd switch in a high load mode state.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an entire electronic timepiece according to an embodiment of the present invention.

  The electronic timepiece 1 of this embodiment includes an analog display unit that displays time by rotating a plurality of hands (for example, hour hand, minute hand, second hand) 11, and a solar cell 12 as a power generation means disposed on a dial, for example. For example, it is a main part of a wristwatch.

  As shown in FIG. 1, the electronic timepiece 1 includes a diode D1 that prevents backflow of current to the solar cell 12 in addition to the pointer 11 and the solar cell 12, and a first power storage unit that stores generated power. Secondary battery 2 and capacitor 3 as the second power storage means, step motor 14 for rotationally driving pointer 11, wheel train mechanism 13 for transmitting the motion of step motor 14 to pointer 11, and a predetermined frequency for timekeeping An oscillation circuit 15 that generates an oscillation signal, an LSI (Large Scale Integrated Circuit) 18 that performs various control operations for realizing a clock operation, and the like are provided.

  The LSI 18 includes a drive circuit 24 that outputs a drive current to the step motor 14, a clock circuit 25 that receives an oscillation signal from the oscillation circuit 15 and clocks the time, and an integrated control of each unit such as a time display process and a power supply switching process. A CPU (Central Processing Unit) 21 as a control means for performing control processing, a RAM 22 that provides a working memory space to the CPU 21, a ROM 23 that stores control data and a control program, connection of a charging destination to the solar cell 12, The first switch Tr1 and the second switch Tr2 for switching the connection of the power supply sources of the functional circuits (including the CPU 21, RAM 22, ROM 23, drive circuit 24, timing circuit 25, oscillation circuit 15 and the like), and the first and second switches Switch switching circuit 40 that generates a switching signal for Tr1 and Tr2, and the battery voltage of the secondary battery 2 are detected. That the battery voltage detector 32 serving as a detecting means, the power supply voltage BAC BAC voltage detector 31 detects that it is now (battery all clear) voltage and the like.

  The secondary battery 2 stores electric power or discharges using an electrochemical reaction, and its storage capacity is much larger than that of the capacitor 3. The capacitor 3 is configured to store electric charge by electrostatic capacity, and a general capacitor or an electric double layer capacitor having a relatively large capacity can be applied.

  The first and second switches Tr1 and Tr2 are composed of, for example, MOS transistors or bipolar transistors. The first switch Tr1 is provided on a common wiring that connects the solar cell 12 and the capacitor 3, and the solar cell 12 and the functional circuit (21, 24), respectively, and switches from an on (closed) state to an off (open) state. Thus, the solar cell 12 and the secondary battery 2 are separated from the capacitor 3 and the functional circuit (21, 24).

  The second switch Tr2 is provided on the wiring connecting the solar cell 12 and the secondary battery 2, and the secondary battery 2 is switched from the on state to the off state, whereby the secondary battery 2 is connected to the solar cell 12, the capacitor 3, and the functional circuit (21 , 24).

  The drive circuit 24 rotates the step motor 14 step by step by outputting the power supply voltage VDD to the step motor 14 in accordance with the timing pulse supplied from the CPU 21.

  For example, the battery voltage detector 32 compares the voltage of the secondary battery 2 with two types of threshold voltages and outputs a comparison signal to the CPU 21, so that the voltage of the secondary battery 2 is set to the Mid level (for example, 2 .3V or higher) and that the voltage of the secondary battery 2 has been reduced to a charge level (for example, 2.2V to 1.9V). The Mid level (normal use level) is a charge level at which each operation of the clock function is normally executed, and the charge level is limited to discharge of the secondary battery 2 in order to avoid a voltage drop of the secondary battery 2 and normal This is a charge level at which operation with relatively large power consumption is stopped in the clock function.

  The BAC voltage detector 31 is used to bring the LSI 18 into an all-clear state before the power supply voltage VDD falls below the operation lower limit voltage of the LSI 18 and causes the LSI 18 to perform an unstable operation. The threshold voltage is slightly higher than the operation lower limit voltage. Are compared with the power supply voltage VDD, and an all clear signal is output to the CPU 21 when the power supply voltage VDD falls below the threshold voltage. The LSI 18 is reset by the all clear signal.

  The switch switching circuit 40 includes a three-input AND gate 43 that outputs a switching signal to the control terminal of the first switch Tr1, a two-input AND gate 44 that outputs a switching signal to the control terminal of the second switch Tr2, and an AND gate. The first latch 42 that supplies one input signal of 43 and 44, the comparator CP1 that generates another input signal of the AND gates 43 and 44, and only the signal input from the comparator CP1 to one AND gate 43 is inverted. Switching to selectively switch the connection of the inverter 45, the voltage reference circuit 41 that generates two types of comparison reference voltages of the comparator CP1, and the inverting input terminal of the comparator CP1 to one of the comparison reference voltage side and the secondary battery 2 side A circuit 46, and a switching limiting circuit 47 for generating another input signal of the three-input AND gate 43; And a second latch 48 like for latching a control signal for switching the action of the replacement circuit 46 and the switching limit circuit 47. Among these configurations, the AND gates 43 and 44 and the inverter 45 constitute a logic means, and the comparator CP1 constitutes a first comparator. The second latch 48 and the CPU 21 constitute a first control means, and the first latch 42 and the CPU 21 constitute a second control means.

  The switching circuit 46 includes switch transistors 51 and 52 that are turned on / off based on the output of the second latch 48, and an inverter 53 that inverts a signal output from the second latch 48 to one switch transistor 51. When the output of the second latch 48 is low level, the connection of the inverting input terminal of the comparator CP1 is switched to the secondary battery 2 side. When the output of the second latch 48 is high level, the connection of the inverting input terminal of the comparator CP1 is changed. The connection is switched to the voltage reference circuit 41 side.

  The switching restriction circuit 47 has an effect of comparing the power supply voltage VDD and the low drive voltage Vd1 (eg, 2.0 V) and turning on the second switch Tr2 when the power supply voltage VDD falls below the low drive voltage Vd1. Further, the switching limiting circuit 47 can switch between the continuation and stop of the above action according to the output of the second latch 48. Here, the low drive voltage Vd1 is a voltage set to a lower value (for example, 2.0 V) at which power consumption is reduced among power supply voltages at which the LSI 18 operates stably. An example is shown. The switching limiting circuit 47 includes the reference voltage generation circuit 55 that generates the low drive voltage Vd1, the comparator CP2 that compares the low drive voltage Vd1 and the power supply voltage VDD, and the output of the comparator CP2. OR gate 56 for passing or blocking. The OR gate 56 receives the latch signal of the second latch 48. When the output of the second latch 48 is low level, the output of the comparator CP2 is sent to the AND gate 43, while the output of the second latch 48 is high level. Sometimes, a high level signal is always sent to the AND gate 43 regardless of the output of the comparator CP2.

  The first latch 42 and the second latch 48 latch a high-level or low-level control signal sent from the CPU 21 and continue outputting this signal. The second latch 48 latches a control signal for switching the switching circuit 46 and switching the operation of the switching restriction circuit 47 as described above.

  The first latch 42 latches a control signal for forcibly turning on the first switch Tr1 and the second switch Tr2. The first latch 42 receives the low level signal from the CPU 21 and outputs the low level signal to the AND gates 43 and 44, so that the AND gates 43 and 44 are independent of the output of the comparator CP 1 and the output of the switching restriction circuit 47. To output a low level signal to turn on both the first and second switches Tr1 and Tr2.

  When the output of the second latch 48 is a high level signal, the comparator CP1 compares the reference voltage supplied from the voltage reference circuit 41 with the terminal voltage of the capacitor 3, and indicates a high level signal indicating the magnitude thereof. Alternatively, a low level signal is output. On the other hand, when the output of the second latch 48 is a low level signal, the terminal voltages of the capacitor 3 and the secondary battery 2 are compared, and if the voltage of the capacitor 3 is high, a high level signal is output. If the voltage of the battery 2 is high, a low level signal is output.

  The voltage reference circuit 41 generates two types of reference voltages and supplies them from the output terminal OUT to the inverting input terminal of the comparator CP1. The first reference voltage is a high level voltage (“Vhigh” in FIG. 3) corresponding to the full charge voltage of the capacitor 3, and the second reference voltage is a low level voltage (corresponding to the charge required voltage of the capacitor 3 ( 3 is “Vlow” in FIG.

  These first and second reference voltages are switched by a select signal SEL which is an output of the comparator CP1. Specifically, when the voltage of the capacitor 3 exceeds the higher first reference voltage, the comparison reference voltage input to the comparator CP1 is switched to the lower second reference voltage, and the lower voltage of the capacitor 3 is switched to the second reference voltage. If the reference voltage is lower than 2, the comparison reference voltage input to the comparator CP1 is switched to the higher first reference voltage.

  The clock circuit 25 and the oscillation circuit 15 are configured to perform a clock operation by being supplied with the same power as that supplied to the LSI 18. Further, the timing operation by the timing circuit 25 and the oscillation circuit 15 is linked with the operation of the LSI 18, and when the LSI 18 is stopped, the timing operation is stopped, and when the LSI 18 is operated, the timing operation is resumed. ing.

  Next, the operation of the electronic timepiece 1 having the above configuration will be described.

  FIG. 2 shows a flowchart of the switch control process executed by the CPU 21.

  This switch control process is continuously executed during the operation of the LSI 18. The switch control process is executed in parallel with the clock function process for realizing the clock function operation. The clock function processing is, for example, driving the pointer 11 in conjunction with the timing operation of the timing circuit 25, activating an alarm (not shown) at the alarm time, or inputting from an operation unit (not shown) according to the operation. Setting processing, processing mode switching, and the like.

  In the switch control process, as shown in the flowchart of FIG. 2, the CPU 21 determines the output of the battery voltage detector 32 and performs control to switch the latch signal of the second latch 48 in accordance with the determination result.

  First, after the battery voltage detector 32 detects that the voltage of the secondary battery 2 has returned to the Mid level (YES in Step S1), it indicates that the voltage of the secondary battery 2 has dropped to the charge level. In a period until immediately before detection (NO in step S4), a low level signal is output to the second latch 48 in order to change the power supply operation state to the normal operation state (steps S2 and S6). The normal operation state in which the low level signal is latched and shifted to the second latch 48 will be described later.

  Further, during this period, the CPU 21 determines whether or not the clock function processing is in the high load mode (step S7), and if it is in the high load mode, outputs a low level signal to the first latch 42 (step S9). If not in the high load mode, a high level signal is output to the first latch 42 (step S8). The high load mode is an operation mode that consumes a relatively large drive current, such as a processing mode in which the step motor 14 is driven at high speed over a long period of time, or a processing mode in which an alarm (not shown) is driven to output a large output. .

  On the other hand, after the battery voltage detector 32 detects that the voltage of the secondary battery 2 has dropped to the charge level (YES in step S4), it indicates that the voltage of the secondary battery 2 has returned to the Mid level. In a period until immediately before the detection is made (NO in step S1), a high level signal is output to the second latch 48 in order to set the operation state of the electronic timepiece 1 to the quick start state (steps S3 and S5).

  In the flowchart of FIG. 2, the same signal is repeatedly output to the first latch 42 and the second latch 48 in several loop processes including steps S3, S6, S8, and S9. If the first latch 42 and the second latch 48 have already been written and need not be changed, the process of repeatedly outputting the same signal may be omitted.

  FIG. 3 is a time chart showing state transitions of charging-related voltages and the output of the second latch 48.

[Quick start status]
First, the quick start state that is shifted when the second latch 48 is set to the high level by the processing of steps S3 and S5 will be described.

  The quick start state is an operation state that continues until the voltage of the secondary battery 2 returns from the state below the charge level to the Mid level as described above.

  As shown in the “quick start state” period of FIG. 3, when the quick start state is entered, first, the first switch Tr1 is turned on and the second switch Tr2 is turned off. When the solar cell 12 generates power, the capacitor 3 is charged until the high level voltage “Vhigh” is reached. When the capacitor 3 is charged, the power of the capacitor 3 is used to drive the hands 11 and the LSI 18, and the first switch Tr1 is turned off and the second switch Tr2 is turned on to charge the secondary battery 2. During the charging period of the secondary battery 2, the voltage of the capacitor 3 decreases from the high level voltage “Vhigh”, while the voltage of the secondary battery 2 increases due to charging. When the discharge of the capacitor 3 progresses and decreases to the low level voltage “Vlow”, the first switch Tr1 is turned on again and the second switch Tr2 is turned off to charge the capacitor 3 to the high level voltage “Vhigh”. .

  In the quick start state, the above operation is repeated, so that the secondary battery 2 is only discharged without being discharged until the voltage of the secondary battery 2 is reduced to the charge level and then restored to the Mid level. Done. On the other hand, when power is generated by the solar cell 12, the hands 11 are quickly driven by charging and discharging the capacitor 3 to notify the user that power generation is in progress and the electronic timepiece 1 is not completely stopped. Can do. Switching between the first switch Tr1 and the second switch Tr2 in this quick start state is realized by the action of the comparator CP1 and the voltage reference circuit 41.

[Normal operation status]
Next, the normal operation state that is shifted when the second latch 48 is set to the low level by the processing of steps S2 and S6 will be described.

  4 and 5 are explanatory diagrams showing switching patterns of the first and second switches Tr1 and Tr2 in the normal operation state. FIG. 4 shows a switching pattern in a high illuminance state where the power generation amount increases, and FIG. 5 shows a switching pattern in a low illuminance state and a zero illuminance state where the power generation amount is small.

  In the normal operation state, the CPU 21 controls the second latch 48 to the low level output based on the detection output of the battery voltage detector 32 as described above, so that the voltage of the secondary battery 2 is changed from the state of the Mid level or higher to the charge level. It continues until just before it falls. In the normal operation state, the control of the normal clock operation excluding the processing in the high load mode is performed in parallel with the clock function processing.

  In the normal operation state, the connection of the inverting input terminal of the comparator CP1 is switched to the secondary battery 2 side by setting the output of the second latch 48 to the low level. That is, the comparator CP 1 compares the terminal voltage of the capacitor 3 with the terminal voltage of the secondary battery 2, and a signal representing the comparison result is sent to the two AND gates 43 and 44. Further, the comparator CP2 of the switching restriction circuit 47 compares the power supply voltage VDD and the low drive voltage Vd1, and outputs an output representing the comparison result to the three-input AND gate 43.

[High illumination state]
In this normal operation state, when the incident light to the solar cell 12 is in a high illuminance state and much power is generated, the switching state in FIG. 4A and the switching state in FIG. 4B are repeated. Thus, the generated current of the solar cell 12 is alternately sent to the capacitor 3 and the secondary battery 2.

  Specifically, in the high illuminance state, first, the power supply voltage VDD does not fall below the low drive voltage Vd1 due to the charging of the capacitor 3, so that the output of the switching restriction circuit 47 remains at the high level. The output of the first latch 42 is controlled to a high level. Accordingly, the first and second switches Tr1 and Tr2 are switched only according to the output of the comparator CP1.

  Since the comparator CP1 compares the voltage of the capacitor 3 and the voltage of the secondary battery 2, if the voltage of the capacitor 3 becomes higher, as shown in FIG. The switch Tr1 is turned off, and the second switch Tr2 on the secondary battery 2 side is turned on. Thereby, the secondary battery 2 is charged and the voltage of the secondary battery 2 rises. If the voltage of the secondary battery 2 becomes higher, as shown in FIG. 4A, the first switch Tr1 on the capacitor 3 side is turned on and the second switch Tr2 on the secondary battery 2 side is turned off. . Thereby, the capacitor 3 is charged and the voltage of the capacitor 3 rises.

  4A and 4B are alternately repeated in this way, the secondary battery 2 and the capacitor 3 are alternately charged as shown in the period A and the period B in FIG. As a result, both voltages rise at almost the same voltage. In addition, the voltage of the secondary battery 2 and the capacitor 3 is stopped at a constant level in the middle of the period A in FIG. 3 because the secondary battery 2 is fully charged. This is because charging to the secondary battery 2 is stopped.

[Low illumination state]
In the normal operation state, when the incident light to the solar cell 12 is in a low illuminance state and the power generation amount of the solar cell 12 is reduced, the electric power stored in the capacitor 3 is consumed by the functional circuit (21, 24). The voltage of the capacitor 3 decreases faster than the voltage of the secondary battery 2. As a result, the output of the comparator CP1 that compares the voltage of the capacitor 3 and the voltage of the secondary battery 2 is constant at a low level, and as shown in FIG. 5A, the first switch Tr1 is on and the second switch Tr2 is Turned off.

  By such switching, as shown in the period of “low illuminance” in FIG. 3, the power generated by the solar cell 12 is supplied to the functional circuits (21, 24) without consuming the power of the secondary battery 2. become. When the power generation amount of the solar cell 12 fluctuates slightly above or below the power consumption of the functional circuit (21, 24), the capacitor 3 is discharged and charged, and the power supply voltage VDD slightly rises and falls. An appropriate drive current is sent to the circuits (21, 24) to continue normal operation.

[Zero illumination state]
In the normal operation state, when the incident height to the solar cell 12 becomes zero illuminance or the like, and the solar cell 12 hardly generates power, as shown in the period of “illuminance 0” in FIG. ), The discharge of the capacitor 3 proceeds, and the voltage of the capacitor 3 falls below the low drive voltage Vd1.

  Then, since the output of the comparator CP2 that compares the voltage of the capacitor 3 and the low drive voltage Vd1 changes to a low level, the second switch Tr2 is turned on as shown in FIG. Here, the first switch Tr <b> 1 is kept on as long as the voltage of the secondary battery 2 does not fall below the voltage of the capacitor 3.

  When the first switch Tr1 and the second switch Tr2 are turned on, a current flows from the secondary battery 2 to the capacitor 3, and the voltage of the capacitor 3 increases. When the voltage exceeds the low drive voltage Vd1, the output of the switching limiting circuit 47 changes to the high level again as shown in FIG. 5B, so that the second switch Tr2 is turned off. Then, due to the power consumption of the functional circuits (21, 24), the discharge of the capacitor 3 proceeds again and its voltage falls below the low drive voltage Vd1.

  That is, when the solar cell 12 hardly generates power in the normal operation state, the states of FIGS. 5B and 5C are repeated, and the charging power of the secondary battery 2 is gradually transferred to the capacitor 3, The voltage of the capacitor 3 changes before and after the low drive voltage Vd1. Further, the power supply voltage VDD that changes before and after the low drive voltage Vd1 is sent to the functional circuit (21, 24), and a stable operation is performed in the functional circuit (21, 24). Further, by adjusting the power supply voltage VDD near the low drive voltage Vd1, the power consumption of the functional circuits (21, 24) is reduced as compared with the case where the power supply voltage VDD is increased.

  As shown in the period of “illuminance 0” in FIG. 3, when the voltage of the capacitor 3 changes before and after the low drive voltage Vd1, the power of the secondary battery 2 is transferred to the capacitor 3 and consumed. The voltage of the secondary battery 2 gradually decreases. However, the decrease in the voltage of the secondary battery 2 results in lower power consumption of the functional circuit (21, 24) than when the voltage of the secondary battery 2 is directly supplied to the functional circuit (21, 24). It will be somewhat gentle.

  And the operation | movement according to the electric power generation amount mentioned above is performed because it will be in the state of a high illumination intensity or a low illumination intensity again in the middle of the voltage of the secondary battery 2 falling gradually. In addition, when a period in which the solar cell 12 hardly generates power continues and the voltage of the secondary battery 2 decreases to the charge level, the CPU 21 outputs a high level signal to the second latch 48, so that the above-described normal operation state is started. The quick start status of the system has been changed.

[High load mode]
Next, the operation in the high load mode that is shifted when the first latch 42 is set to the low level by the process of step S9 in FIG. 2 will be described.

  FIG. 6 is an explanatory diagram showing a switching pattern of the first and second switches Tr1 and Tr2 in the high load mode.

  In the high load mode, as a low level signal is set in the first latch 42, the first switch Tr1 and the second switch Tr2 are forcibly turned on as shown in FIG. Thereby, both the capacitor 3 and the secondary battery 2 are connected to the functional circuit (21, 24). By this connection, a direct power supply from the secondary battery 2 to the functional circuit (21, 24) and a smoothing action by the capacitor 3 can be obtained, and a large current output can be handled.

  As described above, according to the electronic timepiece 1 of this embodiment, in the normal operation state, the voltage of the capacitor 3 is compared with the voltage of the secondary battery 2 by the comparator CP1, and the voltage is output based on the output representing the comparison result. Since the first and second switches Tr1 and Tr2 are switched, the switching of FIGS. 4A and 4B is repeated to charge the capacitor 3 and the secondary battery 2 in a high illuminance state where the charge amount increases. Is called. Further, in a low illuminance state where the amount of charge is reduced, the secondary battery 2 is disconnected and the generated power from the solar cell 12 is consumed by the functional circuits (21, 24). Therefore, even if the charge level of the secondary battery 2 is high, if the power generation is sufficient to drive the functional circuit (21, 24), the generated power of the solar cell 12 is generated by the functional circuit (21, 24). ), The power of the secondary battery 2 is not consumed unnecessarily, and even if the power generation is stopped thereafter, the power consumption of the secondary battery 2 can be delayed.

  Further, the switching limit circuit 47 compares the power supply voltage VDD and the low drive voltage Vd1, and the second switch Tr2 is controlled based on the comparison result. Therefore, in the zero illuminance state where the charge amount is further reduced, FIG. ) And (c) are repeated, the voltage of the secondary battery 2 is adjusted to the low drive voltage Vd1 by the capacitor 3, and is consumed by the functional circuit (21, 24). Therefore, the power of the secondary battery 2 is used little by little only when the power generation amount that can drive the functional circuits (21, 24) cannot be obtained, and the power of the secondary battery 2 is wasted. It will not be done. At this time, since the power supply voltage VDD is adjusted to a low driving voltage Vd1 lower than the voltage of the secondary battery 2, the functional circuit (21, 21) is compared with the case where the voltage of the secondary battery 2 is directly supplied. 24) The power consumption can be reduced. Therefore, even if the power generation is stopped, the power consumption of the secondary battery 2 can be greatly delayed.

  Further, according to the electronic timepiece 1 of this embodiment, the second latch 48 is provided to switch the connection of the switching circuit 46 and the operation of the switching restriction circuit 47, and the CPU 21 sets a low level signal in the second latch 48. Thus, while the power supply operation in the normal operation state as described above is obtained, the CPU 21 sets a high level signal in the second latch 48, so that the power supply operation in the normal operation state is stopped and quick start is performed. It is possible to switch to the state power supply operation. Therefore, the power supply operation can be appropriately switched according to the state of the charge level of the secondary battery 2.

  In addition, according to the electronic timepiece 1 of this embodiment, the first latch 42 for forcibly turning on the first and second switches Tr1 and Tr2 is provided, so the first time in the high load mode. By setting a low level signal to the latch 42 and turning on both the first and second switches Tr1 and Tr2, it is possible to cope with a large current output.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the above embodiment, the connection state of the solar cell 12, the capacitor 3, the secondary battery 2, and the functional circuit (21, 24) is switched by the two switches Tr1 and Tr2. The switching may be performed in conjunction with three or four switches. Further, the configuration in which the comparators CP1 and CP2 directly compare and compare the voltages to be compared has been illustrated, but the comparison may be performed by inputting a voltage obtained by dividing the voltage to be compared through a dividing resistor. .

  Moreover, in the said embodiment, the voltage which switches the voltage comparison operation | movement of the secondary battery 2 and the capacitor | condenser 3 to the comparator CP1, and charging / discharging of the capacitor | condenser 3 in a quick start state by switching the connection of the inverting input terminal of the comparator CP1. Although the comparison operation is performed, these voltage comparison operations may be performed using separate comparators.

  Moreover, in the said embodiment, although the solar cell 12 was illustrated as an electric power generation means, the mechanism of thermoelectric power generation or a self-winding power generation can also be applied. In the above embodiment, an example in which the present invention is applied to an electronic timepiece has been described. However, the present invention can be applied to various electronic devices having a power generation unit and a power storage unit. In addition, the detailed structure and method shown in the embodiments can be appropriately changed without departing from the spirit of the invention.

DESCRIPTION OF SYMBOLS 1 Electronic timepiece 2 Secondary battery 3 Capacitor 11 Pointer 12 Solar cell 14 Step motor 15 Oscillation circuit 21 CPU
22 RAM
23 ROM
24 drive circuit 25 clock circuit 32 battery voltage detector CP1 comparator 40 switch switching circuit 41 voltage reference circuit 42 first latch 43, 44 AND gate 45 inverter 46 switching circuit 47 switching limit circuit 48 second latch CP2 comparator 55 reference voltage generation circuit 56 OR gate Tr1 first switch (first switch means)
Tr2 second switch (second switch means)
Vd1 Low drive voltage

Claims (6)

Power generation means;
A first power storage means connected in parallel to the power generation means, a second power storage means having a smaller capacity than the first power storage means, and a functional circuit for realizing the function of the device;
A first switch means capable of disconnecting the functional circuit and the second power storage means from the power generation means and the first power storage means by switching from the closed state to the open state;
A second switch means capable of disconnecting the first power storage means from the power generation means, the second power storage means and the functional circuit by switching from the closed state to the open state;
A first comparator for comparing the terminal voltage of the first power storage means and the terminal voltage of the second power storage means;
Logic means for controlling switching between the first switch means and the second switch means based on the output of the one comparator;
With
The logic means is
When the terminal voltage of the first power storage means is larger than the terminal voltage of the second power storage means, the first switch means is switched to the closed state, and the second switch means is switched to the open state.
An electronic device, wherein when the terminal voltage of the first power storage means is smaller than the terminal voltage of the second power storage means, the first switch means is switched to an open state and the second switch means is switched to a closed state. A second comparator for comparing a first threshold voltage, which is a power supply voltage capable of driving the functional circuit, and a terminal voltage of the second power storage unit;
The logic means is
When the terminal voltage of the second power storage means is lower than the first threshold voltage based on the output of the second comparator, the switching control of the first switch means based on the output of the first comparator is canceled, 2. The electronic apparatus according to claim 1, wherein the first switch means is always closed. Detecting means for detecting a charge level of the first power storage means;
First control means for switching between stopping and continuing the operation of the first comparator and the second comparator;
The first control means includes
When the charge level of the first power storage means is at a normal use level based on the detection of the detection means, the first comparator and the second comparator are operated, while the charge level of the first power storage means is 3. The electronic device according to claim 2, wherein the operation of the first comparator and the second comparator is stopped when the charge level is at a level that limits the discharge of the first power storage means. A second control means capable of forcibly switching the first switch means and the second switch means to a closed state;
The second control means includes
The first switch means and the second switch means are forcibly closed when in a predetermined operation mode in which the load of the functional circuit is increased. The electronic device according to item. The first power storage means is a secondary battery;
The electronic device according to claim 1, wherein the second power storage unit is a capacitor.   The electronic device according to claim 1, wherein the functional circuit performs an operation related to a clock function.

Images