JP2018045319A - Clock generation circuit and regulator for regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an alternator regulator capable of preventing an indeterminate state of an integrated circuit from arising when power-on reset is released.SOLUTION: A regulator 1 comprises; a clock generation circuit 11 for generating a clock CLK to be fed to a control circuit 10 controlling an AC generator 2; and a power-on reset circuit 12 configured to reset the control circuit 10 when power source voltage is initially supplied to the control circuit 10, and to release the reset of the control circuit 10 after a predetermined time period from the initial supply of the power source voltage to the control circuit 10. The clock generation circuit 11 has an N-channel MOS transistor 114 configured to control clock CLK generation timing in accordance with a power-on reset signal POR. The N-channel MOS transistor 114 allows the clock generation circuit to start generating the clock CLK when a predetermined time period elapses from a point in time when the power-on reset signal POR shifts to a level indicative of the release of the reset.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a clock generation circuit and an alternator regulator.

  Many modern electronic devices are equipped with digital devices such as flip-flops, counters, registers, and microprocessors, or integrated circuits including the digital devices and analog devices.

  The states of flip-flops, registers, counters, etc. in the integrated circuit are generally given an initial state determined in advance by, for example, a register, and in the subsequent operation process, the state transitions according to a change in register value or an input signal. .

  However, when the power supply voltage is supplied to the integrated circuit, the internal state of the integrated circuit becomes indefinite, and an expected operation may not be obtained or a problem that affects the outside may be caused.

  Therefore, at the time of power-on, a power-on reset that forcibly initializes a register or the like is generally performed in order to secure time until the internal state is determined by a register or an input signal (Patent Document 1). 4).

  In Patent Document 1, Patent Document 2, and Patent Document 4, a clock (periodic signal for timing when the integrated circuit operates) is input to the integrated circuit. A power-on reset circuit that controls the timing for canceling the power-on reset is described.

  Patent Document 3 describes a DLL (delay lock loop) circuit that uses an input power-on reset signal to synchronize an internal clock with an externally input clock.

JP 2008-17101 A JP 2004-260648 A JP-A-8-130464 JP-A-5-333963

  In an integrated circuit that operates at a timing based on an externally input clock, if the clock input and the power-on reset signal are input simultaneously, the internal state becomes indeterminate even after the power-on reset is canceled. There is a possibility that the operation cannot be started normally.

  According to the techniques described in Patent Document 1, Patent Document 2, and Patent Document 4, since the power-on reset signal is controlled using the clock, it is possible to shift the clock input and the input of the power-on reset signal. It is. However, in order to control the power-on reset signal, it is necessary to use a lot of digital circuits, and there are concerns about an increase in chip size, failure, and deterioration in yield.

  The DLL circuit described in Patent Document 3 cannot prevent a clock and a power-on reset signal from being input simultaneously.

  The present invention has been made in view of the above circumstances, and provides a clock generation circuit capable of avoiding indefinite internal state after cancellation of a power-on reset of an integrated circuit, and an alternator regulator including the clock generation circuit. With the goal.

  The clock generation circuit of the present invention is a clock generation circuit that generates the clock input to an integrated circuit that operates based on a clock, and resets the integrated circuit when a supply voltage is started to be supplied to the integrated circuit. Power on for performing the reset and the reset cancellation generated by a power-on reset circuit that cancels the reset of the integrated circuit when a predetermined time elapses after the supply voltage is started to be supplied to the integrated circuit. A control unit that controls the generation timing of the clock based on a reset signal, and the control unit has passed a predetermined time after the power-on reset signal reaches a level indicating that the reset is released; The generation of the clock is started at the timing.

  A regulator for an alternator according to the present invention includes the clock generation circuit, the integrated circuit, and the power-on reset circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the clock generation circuit which can avoid the indefiniteness of the internal state after cancellation | release of the power-on reset of an integrated circuit, and the regulator for alternators provided with this can be provided.

It is a figure which shows schematic structure of the regulator 1 for alternators which is one Embodiment of this invention. 2 is a timing chart for explaining an operation at the time of power-on of the alternator regulator 1 shown in FIG. 1. It is a figure which shows the modification of the regulator 1 for alternators shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of an alternator regulator 1 according to an embodiment of the present invention. The alternator regulator 1 is a regulator that controls an AC generator mounted on an automobile.

  The alternator regulator 1 generates a control circuit 10 for controlling the voltage output from the AC generator 2 driven by the internal combustion engine of the automobile to constant, and a clock CLK used for operating the control circuit 10. A clock generation circuit 11, a power-on reset circuit 12 that performs a power-on reset of the control circuit 10, and a power supply 13 that supplies a power supply voltage to each of these circuits are provided.

  A power supply 13 is connected to each of the control circuit 10, the clock generation circuit 11, and the power-on reset circuit 12 through a power supply line REG. The power source 13 is connected to the battery 3 mounted on the automobile via the switch 4. The power supply 13 stabilizes the voltage supplied from the battery 3 and outputs it to the power supply line REG.

  The switch 4 is specifically an automobile ignition switch. When the switch 4 is turned on, a voltage is supplied from the battery 3 to the power supply 13, and the control circuit 10 and the clock generation circuit are supplied from the power supply 13 via the power supply line REG. 11 and the power-on reset circuit 12 are each supplied with a power supply voltage.

  The control circuit 10 is an integrated circuit in which digital devices such as flip-flops, counters, registers, and microprocessors are integrated. The control circuit 10 operates based on the clock CLK generated by the clock generation circuit 11. The control circuit 10 may include an analog device such as a capacitor, a resistor, or a transistor.

  The power-on reset circuit 12 resets the control circuit 10 (initialization of internal register values, etc.) when the supply of power supply voltage to the control circuit 10 is started, and a predetermined time after the supply of power supply voltage to the control circuit 10 is started. When elapses, the reset of the control circuit 10 is released.

  The predetermined time is set in advance for the time required for the operating state of the AC generator 2 to be stable and the various circuits in the control circuit 10 to be completely stable.

  The power-on reset circuit 12 generates a power-on reset signal POR for resetting the control circuit 10 and releasing the reset, and inputs the generated power-on reset signal POR to the control circuit 10.

  In the example of FIG. 1, when the switch 4 is on and the power-on reset signal POR is at a level exceeding the reference value, the control circuit 10 is reset, and when the power-on reset signal POR is the reference value, the control circuit is reset. 10 reset is released.

  The circuit configuration of the power-on reset circuit 12 is not particularly limited, and a known configuration can be adopted.

  For example, in the power-on reset circuit 12, a series circuit of a resistor and a capacitor is connected between the power supply 13 and the ground, the voltage at the connection point of this resistor and this capacitor is input to the inverter, and the output of the inverter is the power-on reset. In this configuration, the signal POR is output.

  This inverter outputs the input voltage as it is until the input voltage reaches a predetermined value, and outputs a reference value (0 V) signal when the input voltage reaches the predetermined value.

  The clock generation circuit 11 includes a capacitor 110, a constant current source 111 that functions as a charge / discharge circuit, a rectangular wave conversion circuit 112, a waveform shaping circuit 113, and an N-channel MOS transistor 114 that functions as a switching element. .

  The constant current source 111 is connected to the power supply line REG. The constant current source 111 operates based on a power supply voltage supplied via the power supply line REG with the switch 4 being on. The output terminal of the constant current source 111 is connected to one end of the capacitor 110. The other end of the capacitor 110 is connected to the ground.

  A connection point between the constant current source 111 and the capacitor 110 is connected to an input terminal of the rectangular wave conversion circuit 112. The output terminal of the rectangular wave conversion circuit 112 is connected to the input terminal of the waveform shaping circuit 113. The output terminal of the waveform shaping circuit 113 is connected to the input terminal of the control circuit 10.

  The N-channel MOS transistor 114 is connected to both ends of the capacitor 110 (a connection point between the constant current source 111 and the capacitor 110 and a connection point between the capacitor 110 and the ground), and a gate thereof is connected to a power-on reset signal. Controlled by POR.

  The N-channel MOS transistor 114 is turned on when the power-on reset signal POR is at a level indicating that the control circuit 10 is reset (hereinafter referred to as a reset level), and the power-on reset signal POR is output from the control circuit 10. If it is a level indicating that the reset is released (hereinafter referred to as a reset release level), it is turned off.

  The constant current source 111 charges and discharges the capacitor 110 based on the power supply voltage supplied from the power supply line REG while the switch 4 is on and the N-channel MOS transistor 114 is off. As the capacitor 110 is charged and discharged, the voltage of the capacitor 110 changes periodically.

  The rectangular wave conversion circuit 112 converts the periodically changing voltage waveform of the capacitor 110 into a rectangular wave and outputs it.

  The waveform shaping circuit 113 shapes the rectangular wave output from the rectangular wave conversion circuit 112 and outputs it as the clock CLK.

  When the switch 4 is on and the N-channel MOS transistor 114 is on, the voltage of the capacitor 110 is fixed at 0V. Therefore, in this state, the clock CLK is not output from the clock generation circuit 11.

  On the other hand, when the switch 4 is on and the N-channel MOS transistor 114 is off, the voltage of the capacitor 110 is charged and discharged by the constant current source 111 and periodically changes. Therefore, in this state, the clock CLK that periodically changes is output from the clock generation circuit 11.

  Thus, the N-channel MOS transistor 114 stops charging / discharging of the capacitor 110 by the constant current source 111 when the power-on reset signal POR is at the reset level, and the power-on reset signal POR is at the reset release level. In some cases, it functions as a control unit that starts charging / discharging of the capacitor 110 by the constant current source 111.

  FIG. 2 is a timing chart for explaining the operation at power-on of the alternator regulator 1 shown in FIG.

  “REG” shown in FIG. 2 indicates a voltage supplied to the power supply line REG. “POR” shown in FIG. 2 indicates the level of the power-on reset signal POR. “CV” shown in FIG. 2 indicates the voltage of the capacitor 110. “CLK” illustrated in FIG. 2 indicates the clock CLK output from the clock generation circuit 11.

  When the switch 4 is turned on at time t1, the power supply voltage supplied to the power supply line REG starts increasing from 0V. At the same time, the level of the power-on reset signal POR output from the power-on reset circuit 12 starts to rise from the reference value (here, 0V).

  While the level of the power-on reset signal POR exceeds the reference value, the control circuit 10 is in a reset state. Since the N-channel MOS transistor 114 is on while the level of the power-on reset signal POR exceeds the reference value, charging of the capacitor 110 by the constant current source 111 is not started, and the clock CLK remains low level.

  When the power supply voltage supplied to the power supply line REG reaches the set value TH at time t2, the level of the power-on reset signal POR is switched to the reference value (0V). At the timing when the level of the power-on reset signal POR becomes the reference value, the reset of the control circuit 10 is released.

  At time t2, when the level of the power-on reset signal POR becomes the reference value, the N-channel MOS transistor 114 is turned off, and charging and discharging of the capacitor 110 is started by the constant current source 111. As a result, the voltage of the capacitor 110 increases according to the time constant, and thereafter, when it reaches a peak, the operation of discharging according to the time constant is repeated.

  The rectangular wave conversion circuit 112 becomes high level during the period when the voltage of the capacitor 110 is equal to or higher than the threshold value TH1, for example, and becomes low level when the voltage of the capacitor 110 is lower than the threshold value TH1. Convert to rectangular wave and output.

  After charging of the capacitor 110 is started at time t2, it takes time depending on the time constant until the voltage of the capacitor 110 reaches the threshold value TH1. For this reason, a time period between the time t2 when the power-on reset is released and the time t3 when the clock CLK is input to the control circuit 10 is determined in advance depending on the time constant of the series circuit of the capacitor 110 and the constant current source 111. Time difference occurs.

  As described above, according to the alternator regulator 1 of FIG. 1, after the switch 4 is turned on, the clock generation circuit 11 controls the N-channel MOS transistor 114 to set the power-on reset signal POR to the reset level (reference value). The generation of the clock CLK is started at a timing when a predetermined time (difference between the time t2 and the time t3) has elapsed from the timing when the clock CLK is reached. Therefore, the clock CLK can be input to the control circuit 10 after the reset of the control circuit 10 is released, and the internal state of the control circuit 10 can be reliably prevented from becoming indefinite after the reset is released. .

  In the example of FIG. 1, such an effect can be obtained simply by adding the N-channel MOS transistor 114 to the configuration of the existing oscillation circuit. For this reason, the manufacturing cost of the regulator 1 for alternators can be reduced.

  Further, since the N-channel MOS transistor 114 is an analog device, it is possible to reduce the chip size of the alternator regulator 1, reduce the failure rate, and improve the yield.

  In the example of FIG. 1, the N-channel MOS transistor 114 is used as a switching element connected to both ends of the capacitor 110. However, a P-channel MOS transistor may be used as the switching element.

  In this case, the power-on reset circuit 12 is changed to a circuit configuration that inverts and outputs the output of the inverter described above. Then, after the switch 4 is turned on, the control circuit 10 is reset in a period in which the power-on reset signal POR is less than the reference value (0 V), and in a period in which the power-on reset signal POR is in the reference value (0 V), The reset of the control circuit 10 is released.

  Further, in the example of FIG. 1, the charging / discharging stop and start of the capacitor 110 are switched by turning on and off the switching elements connected to both ends of the capacitor 110 and controlling the voltage of the capacitor 110. As a modification, the charge / discharge start and stop of the capacitor 110 may be switched by controlling the operation of the constant current source 111.

  FIG. 3 is a view showing a modification of the alternator regulator 1 shown in FIG. In FIG. 3, the same components as those in FIG.

  In the alternator regulator 1 shown in FIG. 3, the N-channel MOS transistor 114 is deleted, and a switch 114A controlled by a power-on reset signal POR is added between the power supply line REG and the constant current source 111. Except for this, the configuration is the same as that shown in FIG.

  The switch 114A is turned off when the power-on reset signal POR is at the reset level, and is turned on when the power-on reset signal POR is at the reset release level.

  Thereby, in the period when the control circuit 10 is reset, the constant current source 111 does not operate, and charging and discharging of the capacitor 110 is stopped. When the reset of the control circuit 10 is released, the constant current source 111 starts operating, and the capacitor 110 is charged / discharged.

  Even with this configuration, it is possible to avoid simultaneous resetting of the control circuit 10 and input of the clock CLK to the control circuit 10.

  In FIG. 3, the switch 114A may be deleted, the constant current source 111 may be connected to the power supply line REG, and the stop and start of the operation of the constant current source 111 may be switched by the power-on reset signal POR.

  In this configuration, the constant current source 111 is stopped when the power-on reset signal POR is at the reset level, and the constant current source 111 is activated when the power-on reset signal POR is at the reset release level. Even with this configuration, it is possible to avoid simultaneous resetting of the control circuit 10 and input of the clock CLK to the control circuit 10.

  A well-known configuration can be employed for the portion other than the N-channel MOS transistor 114 in the clock generation circuit 11 in FIG. 1 and the portion other than the switch 114A in the clock generation circuit 11 in FIG. For example, the clock generation circuit 11 may be configured to generate the clock CLK using a crystal oscillator.

  Whatever oscillation system is employed, the clock generation circuit 11 stops generating the clock CLK and resets the power-on reset signal POR when the power-on reset signal POR is at the reset level. If the generation of the clock CLK is started after a predetermined time has elapsed since the change to the release level, the reset of the control circuit 10 and the input of the clock CLK to the control circuit 10 are performed simultaneously. Can be avoided.

  Up to this point, the clock generation circuit 11 has been described as generating a clock to be input to the control circuit 10 included in the alternator regulator 1. However, the circuit to which the clock CLK is input includes a digital circuit, and the clock CLK Any integrated circuit that operates based on

  For example, the clock generation circuit 11 described above can also generate a clock that is input to an integrated circuit that requires a power-on reset and is mounted on an information communication device such as a personal computer or a smartphone or a digital home appliance.

  As described above, the following items are disclosed in this specification.

(1) A clock generation circuit that generates the clock input to an integrated circuit that operates based on a clock, and resets the integrated circuit when a supply voltage is started to be supplied to the integrated circuit. On the basis of a power-on reset signal for performing the reset and the reset cancellation generated by a power-on reset circuit that cancels the reset of the integrated circuit when a predetermined time elapses after the supply voltage is supplied. A control unit that controls generation timing of the clock, and the control unit receives the clock at a timing at which a predetermined time has elapsed after the power-on reset signal has reached a level indicating that the reset is released. Clock generation circuit that starts generation of.

(2) The clock generation circuit according to (1), further including a capacitor and a charge / discharge circuit that charges and discharges the capacitor based on the power supply voltage, and a signal corresponding to a voltage change of the capacitor is the When the power-on reset signal is a level indicating that the reset is performed, the controller stops charging / discharging of the capacitor by the charge / discharge circuit, and the power-on reset signal is output as a clock. A clock generation circuit for starting charging / discharging of the capacitor by the charging / discharging circuit when the level indicates that the reset is released;

(3) The clock generation circuit according to (2), wherein the charge / discharge circuit is a constant current source that operates based on the power supply voltage, and the capacitor is connected between the constant current source and a ground. The control unit turns on when the power-on reset signal is at a level indicating that the reset is performed, and turns off when the power-on reset signal is at a level indicating that the reset is released. A clock generation circuit configured by switching elements connected to both ends of the capacitor.

(4) The clock generation circuit according to any one of (1) to (3), wherein the integrated circuit is a control circuit that controls a voltage output from the AC generator to be constant. .

(5) An alternator regulator comprising the clock generation circuit according to (4), the integrated circuit, and the power-on reset circuit.

DESCRIPTION OF SYMBOLS 1 Regulator for alternators 2 Alternator 3 Battery 4 Switch 10 Control circuit 11 Clock generation circuit 111 Constant current source 112 Rectangular wave conversion circuit 113 Waveform shaping circuit 114 N channel type MOS transistor 114A Switch 12 Power on reset circuit 13 Power supply REG Power supply line POR power-on reset signal CLK clock

Claims (5)

A clock generation circuit that generates the clock input to an integrated circuit that operates based on a clock,
A power-on reset circuit that resets the integrated circuit when a supply voltage is started to be supplied to the integrated circuit and cancels the reset of the integrated circuit when a predetermined time has elapsed after the supply voltage is supplied to the integrated circuit. A control unit for controlling the generation timing of the clock based on a power-on reset signal for performing the reset and the reset cancellation generated by
The control unit is a clock generation circuit that starts generating the clock at a timing when a predetermined time has elapsed since the power-on reset signal has reached a level indicating that the reset is released. The clock generation circuit according to claim 1,
A capacitor,
A charge / discharge circuit that charges and discharges the capacitor based on the power supply voltage; and
A signal corresponding to the voltage change of the capacitor is output as the clock,
When the power-on reset signal is at a level indicating that the reset is performed, the control unit stops charging / discharging of the capacitor by the charge / discharge circuit, and the power-on reset signal cancels the reset. A clock generation circuit for starting charging / discharging of the capacitor by the charging / discharging circuit when the level is to indicate that it is to be performed; The clock generation circuit according to claim 2,
The charge / discharge circuit is a constant current source that operates based on the power supply voltage,
The capacitor is connected between the constant current source and ground,
The control unit is turned on when the power-on reset signal is a level indicating that the reset is performed, and is turned off when the power-on reset signal is a level indicating that the reset is released. A clock generation circuit composed of switching elements connected to both ends of a capacitor. The clock generation circuit according to any one of claims 1 to 3,
The integrated circuit is a clock generation circuit that is a control circuit that controls a voltage output from the AC generator to be constant. A clock generation circuit according to claim 4;
The integrated circuit;
An alternator regulator comprising the power-on reset circuit.

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