JP3539110B2 - Oscillation circuit, semiconductor device, and portable electronic device and clock provided with these - Google Patents

Oscillation circuit, semiconductor device, and portable electronic device and clock provided with these Download PDF

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JP3539110B2
JP3539110B2 JP02728097A JP2728097A JP3539110B2 JP 3539110 B2 JP3539110 B2 JP 3539110B2 JP 02728097 A JP02728097 A JP 02728097A JP 2728097 A JP2728097 A JP 2728097A JP 3539110 B2 JP3539110 B2 JP 3539110B2
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Prior art keywords
oscillation
circuit
voltage
constant voltage
inverter
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JP02728097A
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JPH10213686A (en
Inventor
信二 中宮
佳樹 牧内
忠雄 門脇
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セイコーエプソン株式会社
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Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides an oscillation circuit,HalfConductor devices and portable electronic devices and watches equipped with themSekiI do.
[0002]
[Background Art]
2. Description of the Related Art Conventionally, an oscillation circuit using a crystal oscillator has been widely used in watches, portable telephones, computer terminals, and the like. In such a portable electronic device or watch, it is necessary to save power consumption and extend the life of the battery.
[0003]
From the viewpoint of saving power consumption, the present inventor analyzed the power consumption of an electronic circuit used in a portable electronic device, particularly a wristwatch. From this analysis, it has been confirmed that, among the electronic circuits formed on the printed circuit board, in the semiconductor device, the power consumption of the oscillation circuit portion occupies a larger proportion than other circuit portions. That is, it has been found that reducing power consumption in an oscillation circuit portion of an electronic circuit used in a portable electronic device is effective in extending the life of a battery used.
[0004]
FIG. 11 shows an example of a conventional crystal oscillation circuit and a constant voltage generation circuit.
[0005]
This crystal oscillation circuit includes a crystal resonator X'tal, an oscillation inverter INV0, and a high resistance Rf forming a feedback circuit. The feedback circuit includes a capacitor C for phase compensation in addition to the resistor Rf.D, CG, And the feedback output of the drain output of the oscillation inverter INV0 to the gate of the oscillation inverter INV0 as a 180 ° phase-inverted gate input.
[0006]
Conventionally, an oscillation inverter INV0 used in such a crystal oscillation circuit includes a pair of P-type field effect transistors (hereinafter, referred to as PMOS) QP.0, N-type field effect transistor (hereinafter referred to as NMOS) QN0And each PMOS QP0, NMOS QN0, And the drain functions as an output side. And each of the transistors QP0, QN0Have their drain sides connected to each other, and their source sides connected to the ground voltage Vdd side and the negative constant voltage Vreg side, respectively.
[0007]
In the crystal oscillation circuit having the above configuration, when the constant voltage Vreg is applied to the oscillation inverter INV0, the output of the oscillation inverter INV0 is inverted by 180 degrees and fed back to the gate. Thereby, the PMOS QP constituting the oscillation inverter INV00, NMOS QN0Are alternately turned on and off, the oscillation output of the crystal oscillation circuit gradually increases, and finally the crystal resonator X'tal performs a stable oscillation operation.
[0008]
However, in the conventional crystal oscillation circuit, the PMOS QP is always used both at startup and after stable oscillation.0, NMOS QN0Since both transistors are turned on and off alternately, there is a problem described below.
[0009]
In the conventional crystal oscillation circuit, PMOSQP0, NMOS QN0Are alternately turned on and off. In this case, the PMOSQP0Is turned on, most of the energy charged in the crystal unit X'tal is discharged as it is. Therefore, in the next charging cycle, the crystal unit X'tal must be charged from the beginning, and the present inventor has found that this charging is a major problem in reducing the power consumption of the entire circuit. Was.
[0010]
In other words, in a state where the crystal oscillation circuit is oscillating stably, a stable oscillation state can be maintained without completely discharging the power charged in the crystal resonator X'tal in the charge / discharge cycle. . However, in the conventional circuit, in this charge / discharge cycle, the cycle of discharging the charge power of the crystal unit X'tal as it is and repeating the charge is repeated, which is a major factor in increasing the power consumption of the entire circuit. I was
[0011]
In such a crystal oscillation circuit, the absolute value of the oscillation stop voltage | Vsto |0Threshold voltage of Vthn0, QP of the PMOS0Assuming that the threshold voltage is Vthp0, it can be expressed as in Equation 1.
[0012]
Equation 1: | Vsto | = K · (| Vthp0 | + Vthn0)
Here, the constant K is 0.8 to 0.9, and | Vthp0 | indicates the absolute value of Vthp0. As described above, the oscillation stop voltage Vsto depends on the threshold voltage Vthn0 of the NMOS transistor and the threshold voltage Vthp0 of the PMOS.
[0013]
On the other hand, the constant voltage generation circuit includes an operational amplifier OP and a negative (hereinafter referred to as “-”) input voltage control PMOS QP.2And plus (hereinafter referred to as +) NMOS QN for input voltage control2, Output NMOS QN1It is comprised including. That is, the negative input terminal of the operational amplifier OP is connected to a PMOS QP having a gate connected to the drain and provided between the constant current source and the power supply voltage Vss.2Connected to the drain of Further, the + input terminal of the operational amplifier OP has an NMOS QN having a gate short-circuited to the drain and provided between the constant current source and the power supply voltage Vss.2Connected to the drain.
[0014]
And the NMOS QN2Output NMOS QN, in which the source and the drain thereof are connected in series, the output of the operational amplifier OP is received at the gate, and the source is connected to the power supply voltage Vss.1Is provided. Therefore, the output voltage of the operational amplifier OP, that is, the output voltage Vreg of the constant voltage generation circuit is equal to the PMOS QP2And NMOS QN2Are affected by the respective threshold voltages Vthp2 and Vthn2.
[0015]
That is, the operation of this circuit will be described below.2The constant current flows through the PMOS QP to the signal line 100.2│Vthp2│ (α: constant) depending on the threshold voltage | Vthp2 | Then, the operational amplifier OP and the NMOS QN1As a result, the signal line 101 is controlled to the same potential α | Vthp2 | In addition, NMOS QN2, A potential difference of αVthn2 depending on the threshold voltage Vthn2 occurs between the signal line 101 and the output line 102. Therefore, a constant voltage α (| Vthp2 | + Vthn2) depending on | Vthp2 | + Vthn2 is generated between the output line 102 and the ground potential Vdd.
[0016]
Therefore, the output voltage of the operational amplifier OP, that is, the output voltage Vreg of the constant voltage generation circuit is equal to the PMOS QP2Threshold voltage Vthp2 and NMOS QN2Of the threshold voltage Vthn2. That is, the constant voltage | Vreg | is proportional to | Vthp2 | + Vthn2. Therefore, the conventional crystal oscillation circuit operates using the constant voltage value Vreg depending on | Vthp2 | + Vthn2 as a power supply.
[0017]
Therefore, in the conventional constant voltage generating circuit, even when the values of threshold voltages Vthp2 and Vthn2 vary in the semiconductor manufacturing process and | Vthp2 | or Vthn2 increases, the constant voltage | Vreg | also increases. Therefore, there is an advantage that | Vreg |> | Vsto | is always maintained in the relationship between the constant voltage Vreg and the oscillation stop voltage Vsto, the oscillation operation can be secured, and the yield of the IC can be improved.
[0018]
Conventionally, in order to operate the oscillator with low power consumption, the number of constant current sources for operating the constant voltage generating circuit has been reduced as much as possible within a range where the constant voltage generating circuit can operate. However, with the need for the development of portable devices as described above, in order to reduce the power consumption of the oscillating inverter, the oscillation operation must be ensured (| Vreg |> | Vsto |) while the constant voltage | It has become necessary to lower Vreg | as much as possible. However, when the constant current from the constant current source that operates the constant voltage generating circuit is reduced, the change in the constant voltage Vreg when the constant current fluctuates due to a temperature change.
[0019]
Here, the temperature characteristics of the transistor will be described with reference to the constant voltage generation circuit illustrated in FIG. In this constant voltage generation circuit, the NMOS QN2, PMOSQP2The current values of the constant current sources TA and TB that operate the LED have temperature dependence. That is, when the constant current sources TA and TB are composed of, for example, a depletion type PMOS, the constant current ID can be expressed by the following equation (2). Here, the current amplification factor of the depletion PMOS constituting the constant current source is β, the absolute value of the threshold voltage is | Vth |, and the gate-source voltage is VGSAnd
[0020]
Equation 2: ID= 1/2 · β · (VGS− | Vth |)2
Here, since the gate of the depletion PMOS is short-circuited in order to form a constant current, the VGS becomes 0V.
[0021]
Equation 3: ID= 1/2 · β · (-Vth)2
As shown in Equation 3, the constant current IDDoes not depend on the power supply voltage. Therefore, the constant current IDIs proportional to the square of the temperature-dependent current amplification factor β and the threshold voltage Vth.DAlso varies with temperature changes.
[0022]
FIG. 12 shows the NMOS QN23 is a graph showing the temperature fluctuation of FIG. In FIG. 12, the vertical axis represents the constant current I.DWhere the horizontal axis represents the gate-source voltage VGSRepresents In the graph, three types of curves are shown.2, The curve C shows the case where the threshold voltage is high, and the curve B shows the case where the threshold voltage is between A and C. Although not shown, the PMOS QP2Have similar characteristics. That is, as can be seen from this graph, the variation of the constant voltage Vreg with respect to the temperature change is the variation of the constant current value and the NMOS QN2Threshold voltage Vthn2, PMOS QP2Of the absolute value of the threshold voltage Vthp2.
[0023]
On the other hand, as for the variation of the oscillation stop voltage Vsto with respect to the temperature, since the oscillation stop voltage Vsto depends on the above-described equation 1, the NMOS QN0, PMOSQP0Only the variation of the threshold voltage.
[0024]
Therefore, the temperature coefficient of the constant voltage Vreg is the change amount of the constant current source and the change amount of the threshold voltage (| Vthp2 | + Vthn2), whereas the temperature coefficient of the oscillation stop voltage Vsto is the threshold voltage (| Vthp0 | + Vthn0). ), The temperature coefficient, that is, the temperature characteristic is different.
[0025]
That is, when the temperature characteristics of the constant voltage Vreg and the oscillation stop voltage Vsto are different, for example, when the constant voltage | Vreg | FIG. 13 shows the relationship between the temperature and the voltage with respect to the stop voltage | Vsto |. FIG. 13 is a graph showing the constant voltage Vreg and the oscillation stop voltage Vsto, with the horizontal axis representing temperature and the vertical axis representing voltage. In order to ensure the oscillation operation, | Vreg |> | Vsto | must be ensured at a high temperature in the operation guarantee temperature range, that is, also at the point B shown in FIG. Here, the temperature at the point B is, for example, a heat-resistant temperature of a generally known wristwatch.
[0026]
Therefore, in other low temperature regions, the constant voltage | Vreg | value must be increased more than necessary. That is, in the conventional constant voltage generation circuit and the conventional crystal oscillation circuit, useless power is consumed. Therefore, it can be seen that it is effective to make the temperature characteristics of the constant voltage Vreg and the oscillation stop voltage Vsto the same in order to reduce the power consumption. That is, conventionally, the difference in temperature gradient between the constant voltage Vreg and the oscillation stop voltage Vsto becomes large, and the above-mentioned | Vreg |> | Vsto | On the low-temperature side (or high-temperature side), | Vreg | must be set higher than that required for guaranteeing the oscillation operation. As a result, wasteful power is consumed.
[0027]
However, the oscillation stop voltage Vsto is equal to the PMOS QP which constitutes the oscillation inverter INV0 in the crystal oscillation circuit.0Threshold voltage Vthp0 and NMOS QN0In the conventional oscillation inverter as described above, only the constant voltage Vreg formed in the constant voltage generating circuit can be adjusted to reduce the power consumption. .
[0028]
That is, if the threshold voltage is changed in the formation of the transistor that constitutes the oscillation inverter, the characteristics of the oscillation inverter also change, so that it is necessary to make changes at various points along with the change in the oscillation characteristics. This would make the design difficult. Therefore, it is difficult to keep the constant voltage | Vreg | as low as possible while maintaining the relationship of | Vreg |> | Vsto | in the constant voltage Vreg and the oscillation stop voltage Vsto, and further reduce the power consumption of the oscillation circuit. Could not be planned.
[0029]
[Problems to be solved by the invention]
Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide an oscillation circuit including an oscillation inverter,HalfIn a conductor device, a portable electronic device, and a timepiece, low power consumption driving and stable oscillation are performed by adjusting a threshold voltage of a transistor in an oscillation inverter included in an oscillation circuit.
[0030]
[0031]
[Means for Solving the Problems]
(1) The present inventionThe oscillation circuit of
An oscillation inverter group including a plurality of oscillation inverters configured using transistors having different threshold voltages, and any one of the oscillation inverters is selectively used;
A feedback circuit that has a crystal oscillator connected to the output side and the input side of the oscillation inverter group, inverts the phase of the output signal of the oscillation inverter group, and feeds back the oscillation inverter group to a feedback circuit;
It is characterized by including.
[0032]
Therefore,According to the invention of the above (1)According to the oscillation circuit, of the oscillation inverter group, the transistor output of the oscillation inverter can be adjusted to an optimum voltage, and the oscillation output of the crystal oscillation circuit can be set to the optimum state. Power consumption can be reduced.
[0033]
(2) The present inventionThe oscillation circuit ofThe above (1)In addition to the features described in
A selection circuit for selecting any one of the oscillation inverters from the oscillation inverter group is included.
[0034]
Therefore,According to the invention of the above (2)According to the oscillation circuit, an oscillation inverter having an optimum threshold voltage can be selected by the selection circuit.
[0035]
(3) The present inventionThe oscillation circuit ofThe above (2)In addition to the features described in
The oscillation circuit is formed on the same substrate as the test circuit,
In a state where the crystal oscillator is not mounted, the test circuit selects each of the oscillation inverters, and measures the short-circuit current of each of the oscillation inverters. One oscillation inverter is specified, and the selection circuit selects the oscillation inverter.
[0036]
Therefore,According to the invention of the above (3)According to the oscillation circuit, the short-circuit current of each oscillation inverter of the oscillation inverter group formed on the IC chip or the wafer can be measured, so that an optimal oscillation inverter can be obtained regardless of the manufacturing conditions. The yield can be improved, and oscillation characteristics with stable and low power consumption can be obtained. Further, the selection circuit may be formed on the same substrate as the test circuit.
[0037]
(4) The present inventionThe oscillation circuit ofThe above (3)In addition to the features described in
The test circuit is connected to a test pad and controls each of the oscillation inverters via the test circuit by controlling a voltage applied to the test pad.
[0038]
Therefore,According to the invention of the above (4)According to the oscillation circuit, a signal for selecting each of the oscillation inverters can be formed by the test circuit by a combination of voltages applied to the test pads, and the short-circuit current of each oscillation inverter is measured. be able to.
[0039]
(5) The present inventionThe oscillation circuit ofThe above (1) to (4)In addition to the features described in any of
The selection circuit is provided corresponding to the oscillation inverter, and is connected to a plurality of pads, includes a plurality of unit circuits,
The plurality of unit circuits each include any one of a fuse, a nonvolatile memory, and a storage element, and select the oscillation inverter by applying a voltage to the pad.
[0040]
Therefore,According to the invention of the above (5).According to the oscillation circuit, a selection circuit for easily selecting the oscillation inverter can be configured by adding a means including any one of a fuse, a nonvolatile memory, and a storage element.
[0041]
(6) The present inventionThe oscillation circuit ofThe above (1) to (5)In addition to the features described in any of
The oscillation inverter group includes a first oscillation inverter including a transistor having a first threshold voltage, and a transistor having a second threshold voltage different from the first threshold voltage. A second oscillation inverter, and a third oscillation inverter including a transistor having a third threshold voltage different from the first and second threshold voltages. I do.
[0042]
Therefore,According to the invention of the above (6).According to the oscillation circuit, the source / drain current flowing through the oscillation inverter can be adjusted to an optimum current among the three oscillation inverters including the transistor having a small difference in threshold voltage in the oscillation inverter group. In addition, the oscillation output of the crystal oscillation circuit can be set to an optimum state, and low power consumption can be achieved.
[0043]
(7) The present inventionThe oscillation circuit ofThe above (1) to (5)In addition to the features described in
A power supply line of each of the oscillation inverters is connected to a first potential side and a second potential side different in potential from the first potential,
The oscillation circuit is configured to perform amplitude by a potential difference between the first potential and the second potential.
[0044]
Therefore,According to the invention of (7) aboveAccording to the oscillation circuit, since the amplitude of the oscillation inverter can be adjusted between the first power supply and the constant voltage, it is possible to obtain stable and low power consumption oscillation characteristics based on the voltage amplitude. Can be.
[0045]
(8) The present inventionThe oscillation circuit ofThe above (7)In addition to the features described in
A potential difference between the first potential and the second potential is larger than an absolute value of an oscillation stop voltage of the oscillation inverter.
[0046]
Therefore,According to the invention of (8) aboveAccording to the oscillation circuit, a stable oscillation operation can be ensured by the oscillation inverter.
[0047]
(9) The present inventionThe oscillation circuit of(7) or (8) aboveIn addition to the features described in
While the short-circuit current flowing to the selected oscillation inverter satisfies the condition that the ON current of the transistor constituting the selected oscillation inverter is larger, the selection of the oscillation inverter is performed,
A difference between the first potential and the second potential is set to a minimum voltage.
[0048]
Therefore,According to the invention of the above (9).According to the oscillation circuit, a stable and low power consumption oscillation operation can be performed by the oscillation inverter, and it is possible to cope with a low power supply voltage.
[0049]
(10) The present inventionThe constant voltage generation circuit of
A constant voltage control circuit having one end connected to the first potential side, the other end connected to the constant voltage output side, including a plurality of transistors having different threshold voltages, and one of the transistors being selectively used;
An operational amplifier in which a reference voltage of the constant voltage control circuit is input to one terminal and a given reference voltage is input to the other terminal;
A transistor having one end connected to the other end of each of the transistors of the constant voltage control circuit, the other end connected to the second potential side, and receiving an output of the operational amplifier to control a gate input voltage;
It is characterized by including.
[0050]
Therefore,According to the invention of the above (10).According to the constant voltage generating circuit, the value of the constant voltage at the time of selecting each transistor of the transistor group formed on the IC chip can be measured at the monitor terminal. And a constant voltage with low power consumption can be obtained in almost the same chip area.
[0051]
(11) The present inventionThe constant voltage generation circuit ofThe above (10)In addition to the features described in
The constant voltage generation circuit includes a selection circuit that selects one transistor from a plurality of transistors in the constant voltage control circuit.
[0052]
Therefore,According to the invention of (11) aboveAccording to the constant voltage generation circuit, the optimum transistor can be selected by the selection circuit.
[0053]
(12) The present inventionThe constant voltage generation circuit ofThe above (11)In addition to the features described in
The constant voltage generation circuit is connected to a monitor terminal, and is provided on the same substrate as the test circuit.
In the inspection step, the test circuit selects each transistor in the constant voltage control circuit, and measures the output voltage of each transistor in the constant voltage control circuit at the monitor terminal, whereby the test circuit controls the constant voltage control circuit. One transistor is specified from a plurality of transistors, and the transistor is selected by the selection circuit.
[0054]
Therefore,According to the invention of (12) aboveAccording to the constant voltage generating circuit, the value of the constant voltage at the time of selecting each transistor of the transistor group formed on the IC chip can be measured at the monitor terminal. And a constant voltage with low power consumption can be obtained in almost the same chip area.
[0055]
(13) The present inventionThe constant voltage generation circuit ofThe above (12)In addition to the features described in
The test circuit is connected to a test pad and controls each voltage in the constant voltage control circuit via the test circuit by controlling a voltage applied to the test pad. .
[0056]
Therefore,According to the invention of the aforementioned (13).According to the constant voltage generation circuit, a signal for selecting each transistor of the constant voltage control circuit can be formed by the test circuit by a combination of voltages applied to the test pads. The measured reference voltage can be measured.
[0057]
(14) The present inventionThe constant voltage generation circuit ofThe above (10) to (13)In addition to the features described in any of the above,
The selection circuit includes a plurality of unit circuits formed corresponding to the plurality of transistors in the constant voltage control circuit and connected to a plurality of pads,
The plurality of unit circuits each include one of a fuse, a non-volatile memory, and a storage element, and select the transistor by applying a voltage to the pad.
[0058]
Therefore,According to the invention of the above (14).According to the constant voltage generating circuit, by adding a means including any one of a fuse, a nonvolatile memory, and a storage element, it is possible to easily configure a selecting circuit for selecting the oscillation inverter.
[0059]
(15) The present inventionThe constant voltage generation circuit ofThe above (10) to (14)In addition to the features described in any of
The constant voltage control circuit includes a transistor having a fourth threshold voltage, a transistor having a fifth threshold voltage different from the fourth threshold voltage, and a sixth transistor having a fourth threshold voltage different from the fourth and fifth threshold voltages. Wherein each of the transistors has one end connected to the first potential side and the other end connected to the constant voltage output side.
[0060]
Therefore,According to the invention of the above (15).According to the constant voltage generation circuit, the constant voltage value of three types of transistors having different threshold voltages in the test circuit formed on the IC chip can be measured at the monitor terminal. Thus, an optimum constant voltage can be obtained irrespective of manufacturing conditions, and a constant voltage with low power consumption can be obtained with almost the same chip area.
[0061]
(16) The present inventionThe constant voltage generation circuit ofThe above (10) to (15)In addition to the features described in any of the above,
An output voltage of the constant voltage generation circuit is supplied to an oscillation circuit.
[0062]
Therefore,According to the invention of the above (16).According to the constant voltage generation circuit, the constant voltage can be adjusted according to the oscillation characteristics of the oscillation circuit, so that an optimum constant voltage can be supplied to the oscillation circuit.
[0063]
(17) The present inventionThe semiconductor device of
An oscillation circuit, a constant voltage generation circuit, a semiconductor device including a test circuit,
The oscillation circuit includes:
An oscillation inverter group including a plurality of oscillation inverters configured using transistors having different threshold voltages, and any one of the oscillation inverters is selectively used;
A first selection circuit for selecting one oscillation inverter from a plurality of oscillation inverters in the oscillation inverter group;
A feedback circuit that inverts the phase of an output signal of the oscillation inverter group to which an external crystal oscillator and an output side and an input side are connected, and that performs feedback input to the oscillation inverter group;
Including
The constant voltage generating circuit,
A constant voltage control circuit having one end connected to the first potential side, the other end connected to the constant voltage output side, including a plurality of transistors having different threshold voltages, and one of the transistors being selectively used;
An operational amplifier in which a reference voltage of the constant voltage control circuit is input to one terminal and a given reference voltage is input to the other terminal;
A transistor having one end connected to the other end of each transistor of the constant voltage control circuit, the other end connected to the second potential side, and a gate input voltage controlled by receiving the output of the operational amplifier;
A second selection circuit that selects one transistor from a plurality of transistors in the constant voltage control circuit;
Including
The test circuit is connected to the oscillation circuit and the constant voltage generation circuit, respectively,
A monitor terminal for monitoring an output voltage of the constant voltage generating circuit, and a monitor terminal provided to be connected to the test pad;
In the inspection step, by controlling a voltage applied to the test pad while applying a voltage to the monitor terminal, each of the oscillation inverters is selected via the test circuit, and each of the oscillation inverters is selected. Measure the short-circuit current of each inverter,
After measuring the short-circuit current, by controlling the voltage applied to the test pad, each transistor in the constant voltage control circuit is selected via the test circuit, and the output voltage of each transistor is monitored by the monitor terminal. Measure each at
As long as the oscillation operation of the oscillation inverter can be ensured, the oscillation inverter in the oscillation circuit is selected by the first selection circuit, and the transistor in the constant voltage control circuit in the constant voltage generation circuit is The selection is performed by the second selection circuit.
[0064]
Therefore,According to the invention of the above (17).According to the semiconductor device, the optimum combination of the short-circuit current and the constant voltage can be selected from the combination of the measurement result of the short-circuit current of the oscillation inverter of the crystal oscillation circuit and the measurement result of the constant voltage. , A stable oscillation output of the oscillation circuit can be obtained, the yield can be improved, and the power consumption can be further reduced.
[0065]
(18) The present inventionPortable electronic devices
The above (1) to (9)Wherein the operation reference signal is formed from the oscillation output of the oscillation circuit.
[0066]
Therefore,According to the invention of the above (18).According to the portable electronic device, it is possible to reduce the power consumption of the electronic circuit while securing the operation margin of the oscillation inverter, regardless of the manufacturing variation of the portable electronic device, and to stabilize the oscillation operation in the portable electronic device. In addition to this, it is possible to extend the life of the battery used, and to improve the usability of the portable electronic device.
[0067]
(19) The present inventionPortable electronic devicesThe above (18)In addition to the features described in
Forming a supply voltage to the oscillation circuitThe above (10) to (16)Wherein the constant voltage generating circuit is provided.
[0068]
Therefore,According to the invention of the above (19),According to the portable electronic device, since the minimum constant voltage can be further supplied to the oscillation circuit, the power consumption of the electronic circuit can be reduced.
[0069]
(20) The present inventionThe clock is(19)In addition to the features described in
The above (1) to (9)And a clock reference signal is formed from an oscillation output of the oscillation circuit.
[0070]
Therefore,According to the invention of (20) aboveAccording to the timepiece, it is possible to stably perform the oscillating operation of the timepiece while securing the operation margin of the oscillation inverter irrespective of the manufacturing variation of the timepiece, and to extend the life of the battery used. It is possible to improve the usability of the watch.
[0071]
(21) The present inventionThe clock isThe above (20)In addition to the features described in
Forming a supply voltage to the oscillation circuitThe above (10) to (16)Wherein the constant voltage generating circuit is provided.
[0072]
Therefore,According to the invention of the above (21).According to the timepiece, the minimum constant voltage can be further supplied to the oscillation circuit, so that the power consumption of the timepiece circuit can be reduced.
[0073]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.
[0074]
<Embodiment 1>
FIG. 2 shows a constant voltage generation circuit and a crystal oscillation circuit according to a preferred first embodiment of the present invention. The crystal oscillation circuit of the present embodiment is a crystal oscillation circuit used in a quartz wristwatch. The members corresponding to the circuit shown in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.
[0075]
In the crystal oscillation circuit of the present embodiment, an oscillation inverter group is formed by a plurality of oscillation inverter units, and each threshold voltage of PMOS / NMOS constituting the oscillation inverter unit is set for each oscillation inverter unit. It is formed differently so that an optimum oscillation inverter unit can be selected.
[0076]
The crystal oscillation circuit shown in FIG. 2 will be described. The crystal oscillation circuit of the present embodiment includes an oscillation inverter group 10, selection control circuits 20P and 20N, a crystal oscillator X'tal, and a high resistance Rf forming a feedback circuit. Here, the MOS is formed on an IC chip formed on a semiconductor substrate, and the other elements are mounted on a printed circuit board by being connected to the IC chip. The feedback circuit includes a capacitor C for phase compensation in addition to the resistor Rf.D, CG, And the drain output of the oscillation inverter group 10 is fed back to the gate of the oscillation inverter unit INV1 at the first stage of the oscillation inverter group 10 as a gate input whose phase is inverted by 180 degrees.
[0077]
In the oscillation inverter group 10, the PMOS QP4And NMOS QN4Oscillating inverter unit INV1, PMOSQP5And NMOS QN5Oscillation inverter units INV2 and PMOSQP6And NMOS QN6Is formed in the third inverter unit INV3 for oscillation.
[0078]
Each of the oscillation inverter units INV1 to INV1 to 3 is connected to a first potential side and a second potential side with a lower voltage, respectively, and is configured to be supplied with power and driven by a potential difference between the two potentials. I have. Here, in the crystal oscillation circuit of the present embodiment, the first potential is set to the ground voltage Vdd, and the second potential is set to the negative constant voltage Vreg supplied from the constant voltage generation circuit. .
[0079]
Each transistor in the oscillation inverter units INV1 to 3 constituting the oscillation inverter group 10 is formed with a different threshold voltage for each of the oscillation inverter units. For example, NMOSQN4, QN5, QN6Are set to Vthn4> Vthn5> Vthn6, and the PMOSQP is set according to the magnitude of the threshold voltage of each NMOS.4, QP5, QP6Are formed so that | Vthp4 |> | Vthp5 |> | Vthp6 |. The threshold voltage is controlled such that the threshold voltage differs for each oscillation inverter unit by controlling the implantation concentration of impurities at the time of transistor formation. For example, as a difference between these threshold voltages, the potential difference between Vthn4 and Vthn5, Vthn5 and Vthn6, Vthp4 and Vthp5, and Vthp5 and Vthp6 can be about 0.1V.
[0080]
Each of the oscillating inverter units INV1 to INV3 is connected to one end of the capacitor C to which the ground voltage Vdd is applied.GAnd the respective input gates are electrically connected in common. Further, each of the oscillation inverter units INV1 to INV1 to 3 has a capacitor C to which each output node is connected in common and a ground voltage Vdd is applied to one end.DAnd the other end of the crystal unit X'tal. The other end of the crystal unit X'tal is connected to the capacitor CG, The gate inputs of the oscillation inverter units INV1 to 3 and one end of the feedback resistor Rf. Further, the other end of the feedback resistor Rf is connected to each output section of each oscillation inverter unit INV1-3, and the output of each oscillation inverter unit INV1-3 is fed back to each gate.
[0081]
Further, each of the oscillation inverter units INV1 to 3 is provided so as to be connected between an NMOS selection control circuit 20N and a PMOS selection control circuit 20P to which a selection signal is input. The NMOS selection control circuit 20N includes an NMOS QN receiving a selection signal at its gate.7~ QN9And the PMOS selection control circuit 20P includes a CMOS inverter circuit IP having a gate receiving a selection signal.1~ IP3And the PMOS QP receiving its output at each gate7~ QP9It consists of. That is, the PMOS QP constituting the PMOS selection control circuit 20P7~ QP9Each of the gates receives an inverted signal of each of the selection signals.
[0082]
The connection of the PMOS selection control circuit 20P, the NMOS selection control circuit 20N, and the oscillation inverter group 10 will be described below by taking the oscillation inverter unit INV1 as an example. The oscillation inverter units INV2 and INV3 have exactly the same configuration.
[0083]
PMOS QP included in the PMOS selection control circuit 20P7Means that the power supply voltage Vss is applied to the source and the drain is the PMOS QP4Connected to the source. The NMOS QN included in the NMOS selection control circuit 20N7Means that a constant voltage Vreg is applied to the source and the drain is the NMOS QN4Connected to the source. And the selection control NMOS QN7The selection signal SEL1 instructing selection / non-selection of the oscillation inverter unit INV1 in the oscillation inverter group 10 is input to the gate of7Of the selection signal SEL1 is applied to the gates of. That is, when the selection signal SEL1 is at a high level, the oscillation inverter unit INV1 can be in a selected state, and when the selection signal SEL1 is at a low level, the oscillation inverter unit INV1 can be in a non-selected state.
[0084]
Although the oscillation inverter unit INV1 has been described as an example, the configuration of the oscillation inverter units INV2 and INV3 is the same as described above, and the selection signal SEL2 is input to the gate of the oscillation inverter unit INV2. PMOS QP for selection control8And a selection control NMOS QN whose gate receives an inverted signal of the selection signal SEL2.8Is provided. Similarly, in the inverter INV3, the selection control NMOS QN whose selection signal SEL3 is input to the gate is provided.9And a selection control PMOS QP whose gate receives an inverted signal of the selection signal SEL1.9Are similarly provided.
[0085]
As described above, the oscillation inverter group 10 and the selection control circuits 20P and 20N constituted by the oscillation inverter units INV1 to 3 having different threshold voltages respectively make the oscillation output as the crystal oscillation circuit an optimum state. The oscillation inverter group 10 is provided for adjusting the transistor output of the oscillation inverter unit to an optimum voltage.
[0086]
That is, the input of the selection signals SEL1 to SEL3 to the selection control circuits 20P and 20N controls the activation of the oscillation inverter units INV1 to INV1 to 3 and provides an oscillation inverter unit having a transistor formed with an optimum threshold voltage. Is to select. The method and circuit for switching the voltage levels of the selection signals SEL1 to SEL3 will be described later in detail with reference to FIG.
[0087]
Next, a method of selecting an oscillation inverter unit in the crystal oscillation circuit of the present embodiment will be described. In the present embodiment, for example, a case where the oscillation inverter unit INV1 is selected will be described.
[0088]
The selection signal SEL1 is set to the high level, and the selection control PMOS QP7Low level, NMOS QN7Since a high level voltage is applied to the gate of the PMOS QP7And NMOS QN7Turns on. Therefore, in the oscillation inverter unit INV1, the PMOS QP4Source is ground voltage Vdd, NMOS QN4Is electrically connected to the constant voltage Vreg, thereby selecting the oscillation inverter unit INV1.
[0089]
On the other hand, since the selection signals SEL1 and SEL2 are at the low level, the selection control PMOS QP8, QP9Are applied with inverted signals of the selection signals SEL1 and SEL2, that is, a high-level signal.8, QP9Turns off. Then, the selection control NMOS QN8, QN9Are applied with the selection signals SEL1 and SEL2, that is, a low-level signal.8, QN9Turns off. Therefore, the oscillation inverter units INV3 and INV4 are electrically disconnected from the two power supplies and are not selected.
[0090]
Next, a method of forming the selection signals SEL1 to SEL3 will be described with reference to FIG.
[0091]
FIG. 3 shows an oscillation inverter unit selection circuit according to a preferred first embodiment of the present invention. The oscillation inverter unit selection circuit according to the present embodiment includes a selection signal SEL1 for selecting an optimum oscillation inverter unit from the oscillation inverter group 10 including the oscillation inverter units INV1 to 3 in the crystal oscillation circuit. 2 to 3 are circuits.
[0092]
The oscillation inverter unit selection circuit is composed of unit circuits corresponding to the number of the oscillation inverter units. For example, for a crystal oscillation circuit having three types of oscillation inverter units INV1 to 3 shown in FIG. Three unit circuits U1 to U3 are provided. That is, the oscillation inverter unit selection circuit includes three types of pads P1 to P3 and three types of fuse circuits F1 to F3. Each of the fuse circuits F1 to F3 has one end connected to the ground voltage Vdd, the other end connected to the pads P1 to P3, the fuses f1 to f3, one end connected to the power supply voltage Vss, and the other end connected to the pad and the pad. It is configured to include resistors R1 to R3 connected in series with the other ends of the fuses f1 to f3, and output inverters I1 to I3.
[0093]
For example, when the unit circuit U1 is a circuit for forming the selection signal SEL1, the output of the unit circuit U1 is the NMOS QN of the oscillation inverter unit INV1.7Via the inverter of the selection control circuit 20P in the crystal oscillation circuit.7Input to the gate.
[0094]
In the oscillation inverter unit selection circuit of the present embodiment, fuses f1 to f3 of fuse circuits F1 to F3 can be cut by applying a high voltage of, for example, about 20V. For example, when the oscillation inverter unit INV1 is selected, first, a high voltage is applied to the pad P1 and the fuse f1 is cut off so that a current flows from the pad P1 to the power supply Vss via the resistor R1. To As a result, the voltage input to the output inverter INVU1 goes low, and the output voltage of the output inverter INVU1, that is, the output signal of the unit circuit U1 in the oscillation inverter unit selection circuit goes high. Therefore, the selection signal SEL1 shown in FIG.7Turns on and the selection control PMOS QP7Turns off.
[0095]
Although the case where the oscillation inverter unit INV1 is selected has been described above, the selection of INV2 and INV3 can be performed in the same manner. For example, when selecting the oscillation inverter unit INV2, a high voltage is applied to the pad P2, the fuse f2 of the unit circuit U2 is cut off, and when the oscillation inverter unit INV3 is selected, a high voltage is applied to the pad P3. The desired oscillation inverter unit can be similarly selected by cutting the fuse f3 of the unit circuit U3 by applying the voltage. Here, in the present embodiment, a method of storing information by cutting a fuse has been described as an example. However, the present invention is not limited to this, and information can be stored using a nonvolatile memory, a storage element, or the like.
[0096]
FIG. 4 is a timing chart showing the relationship between the oscillation stop voltage Vsto and the selection signals SEL1 to SEL3. In FIG. 4, the horizontal axis represents time. Here, between the oscillation stop voltage Vsto and the ground voltage Vdd, the oscillation stop voltage | Vsto | increases as the difference voltage increases.
[0097]
First, when the selection signal SEL1 is set to the high level, the oscillation stop voltage | Vsto | becomes K (| Vthp7 | + Vthn7) (K: constant) according to the above-described equation 1. When the selection signal SEL1 is at a low level and the selection signal SEL2 is at a high level, the oscillation stop voltage | Vsto | becomes K (| Vthp8 | + Vthn8). When the selection signal SEL2 is at a low level and the selection signal SEL3 is at a high level, the oscillation stop voltage | Vsto | becomes K (| Vthp9 | + Vthn9). That is, the oscillation stop voltage | Vsto | when SEL1 is set to the high level is the lowest, and the oscillation stop voltage | Vsto | is highest when the SEL3 is set to the high level.
[0098]
By the way, the fuse in the oscillation inverter unit selection circuit is cut at the time of inspection of the IC. At this time, first, the NMOS QN of the selection control circuit 20N connected to the oscillation inverter group 10 is turned off.7~ QN9The oscillation inverter unit is obtained by measuring the value of the negative constant voltage Vreg, which is the output voltage of the constant voltage generation circuit, and the short-circuit current Is flowing through each of the oscillation inverter units INV1 to INV1-3. Is selected.
[0099]
FIG. 5A shows a method for measuring the short-circuit current Is flowing through the oscillation inverter unit, and FIG. 5B shows an oscillation in which the vertical axis represents the oscillation stop voltage | Vsto | and the horizontal axis represents the short-circuit current Is. 5 is a graph showing a relationship between stop voltage | Vsto | and short-circuit current Is.
[0100]
As shown in the figure, the short-circuit current of the oscillation inverter unit is measured by the PMOS QPSThe ground voltage Vdd is applied to the source of the NMOS QNSIs applied by applying a constant voltage Vreg to the source of the transistor QPs and the common gate and the common drain of the PMOS QPs and the NMOS QNs, and measuring a current flowing between the ground voltage Vdd and the constant voltage Vreg.
[0101]
At this time, in the graph of the relationship between the oscillation stop voltage | Vsto | and the short-circuit current Is of the oscillation inverter unit, the constant voltage Vreg and the oscillation stop voltage Vsto are | Vreg |> | Vsto | and | Vreg | must be kept as low as possible.
[0102]
That is, for the short current Is, the PMOS QPSIt is necessary to select the oscillation inverter unit and the constant voltage Vreg so as to be equal to or higher than the on-voltage, that is, equal to or higher than the threshold voltage | VthpS | and the lowest constant voltage | Vreg |. Further, with respect to the oscillation stop voltage | Vsto |SIt is necessary to select a voltage equal to or lower than the ON voltage, that is, a voltage lower than the threshold voltage VthnS. Therefore, in order to reduce power consumption, the short-circuit current Is and the oscillation stop voltage | Vsto | must be within the range of region 1 shown in the figure. On the other hand, in order to select an oscillation inverter unit that satisfies this condition and can cope with the recent reduction in the power supply voltage, the oscillation inverter with the lowest short-circuit current that stably oscillates within a range where the on / off operation of the transistor is compensated for It is necessary to select a unit. That is, by selecting the optimum oscillation inverter unit that satisfies this condition according to the result of the short-circuit current measurement described above, the power consumption of the crystal oscillation circuit can be reduced.
[0103]
For this reason, in the IC inspection process, before mounting the crystal unit X'tal on the substrate using a test circuit (not shown) and a test pad connected to the test circuit, each oscillation inverter unit is used. The short-circuit current Is is measured at INV1 to 3, and the short-circuit current having the lowest short-circuit current within the range where the on / off operation is compensated is specified. At this time, the IC test is performed in a wafer state, and a short circuit current is measured for each IC chip using a test circuit and a test pad provided in each IC chip. At this time, only the oscillation inverter group 10 and the selection control circuits 20P and 20N are activated, and the other elements are inactive to perform the test.
[0104]
Incidentally, one or more test pads are provided in accordance with the number of oscillation inverter units and the logic of the test circuit, and the test circuit is provided with a combination of voltage levels of input signals to the test pad. , And a circuit including a logic circuit for setting any one of the selection signals SEL1 to SEL3 to a high level. The measurement of the short-circuit current is performed in a state where the high-level selection signal is input to each of the oscillation inverter units in the test circuit. At this time, a ground voltage Vdd and a constant voltage Vreg are applied to the oscillation inverter group by applying a negative voltage Vreg equivalent to a constant voltage by using the monitoring pad MP connected to the output line 102. Is applied.
[0105]
Then, after measuring the short-circuit current Is, the optimum oscillation inverter unit of the oscillation inverter group 10 is specified, and the fuse in the unit circuit of the oscillation inverter unit selection circuit provided corresponding to the oscillation inverter unit is provided. And select an optimal oscillation inverter unit.
[0106]
As described above, the crystal oscillation circuit of the present embodiment can test the short-circuit current Is of the oscillation inverter unit at the time of IC inspection, so that an optimum oscillation inverter can be obtained regardless of the manufacturing conditions. The yield can be improved, and oscillation characteristics with stable and low power consumption can be obtained.
[0107]
Here, a graph of the oscillation operation of the oscillation inverter of the present embodiment obtained in this manner is shown in FIG. 6, and the oscillation operation will be described. In FIG. 6, the horizontal axis represents time, and the time axis of the drain waveform and the gate waveform are shown as common. In the crystal oscillation circuit in which the optimal oscillation inverter unit has been selected, the amplitude of the gate input waveform is amplified according to the optimal driving capability of the oscillation inverter unit. The phase of the drain output waveform is inverted by 180 degrees with respect to the gate input waveform. And the drain capacitance CDFunctions as a filter that cuts harmonic components and enables only the oscillation frequency component to prevent harmonic oscillation of the crystal oscillation circuit. The resistance Rf and the drain capacitance CD, Crystal oscillator X'tal, gate capacitance CGThe feedback circuit includes a circuit for converting the phase of the drain waveform by 180 degrees.
[0108]
As described above, the output characteristics of the oscillation inverter in the crystal oscillation circuit of the present embodiment realize an oscillation circuit with good output characteristics and low power consumption because the oscillation operation is performed by the optimal oscillation inverter unit. can do.
[0109]
Although the crystal oscillation circuit of this embodiment has been described above, in this embodiment, three types of oscillation inverter units having different threshold voltages have been described, but the number of oscillation inverter units is not particularly limited. The number of oscillation inverter unit selection circuits can be set correspondingly to the number of oscillation inverter units.
[0110]
In the present embodiment, the setting of the threshold voltage is described as the oscillation inverter INV1> INV2> INV3, that is, Vthn4> Vthn5> Vthn6, | Vthp4 |> | Vthp5 |> | Vthp6 |, but is not limited to this. Without setting, the threshold voltage can be set as INV1 <INV2 <INV3, that is, Vthn4 <Vthn5 <Vthn6, | Vthp4 | <| Vthp5 | <| Vthp6 |.
[0111]
<Embodiment 2>
Next, a constant voltage generating circuit according to the present embodiment will be described with reference to FIG.
[0112]
The constant voltage generation circuit according to the present embodiment forms a plurality of NMOSs for controlling one input voltage of the operational amplifier with different threshold voltages, and can select an optimum NMOS from the plurality of NMOSs. It was done.
[0113]
The constant voltage generation circuit according to the present embodiment includes an operational amplifier OP, a selection control circuit 30, and an output gate NMOS QN1, Constant voltage control circuit 40, and -input PMOS QP2It is comprised including.
[0114]
The operational amplifier OP has a + input terminal and a − input terminal, and the + input terminal receives a voltage formed by the constant voltage control circuit 40. The negative input terminal is constituted by a PMOS, and the selection control PMOS QP provided between a ground voltage Vdd and a constant current source.2Receive a voltage controlled by The operational amplifier OP amplifies the potential difference between the voltage applied to the + input terminal and the voltage applied to the − input terminal, and outputs the result. Further, the -input PMOS QP2Has a source to which a ground voltage Vss is applied, a gate and a drain commonly connected, and a source connected to a constant current source.
[0115]
The output gate NMOS QN1Has a gate receiving the output of the operational amplifier OP, and has a drain connected to the output line 102 of the constant voltage generating circuit. Further, the output gate NMOS QN1Are applied with the power supply voltage Vss.
[0116]
The constant voltage control circuit 40 includes an NMOS QN10~ QN12It is comprised including. The constant voltage control circuit 40 is a circuit for controlling the constant voltage Vreg formed by the constant voltage generation circuit by controlling the input voltage of the + input terminal of the operational amplifier OP, and is a circuit for controlling the first potential Vreg. And the NMOS QN provided between a second potential lower than the first potential.10~ QNThirteenAre commonly connected to the negative input terminal of the operational amplifier OP. That is, the NMOS QN10~ QN12Are connected to the + input terminal of the operational amplifier OP, and the source is electrically connected to the output line 102 of the constant voltage generation circuit via the selection control circuit 30.
[0117]
Here, the constant voltage control NMOS QN10~ QN12Are formed with different threshold voltages, respectively, and the NMOS QN10Threshold voltage Vthn10, the NMOS QN11Threshold voltage Vthn11, the NMOS QN12Are formed such that, for example, the relationship of Vthn10> Vthn11> Vthn12 is satisfied. The control of the threshold voltage can be performed by controlling the implantation concentration of impurities when forming the transistor. At this time, for example, each potential difference between Vthn10 and Vthn11 and between Vthn11 and Vthn12 can be set to about 0.1V.
[0118]
As described above, the selection control circuit 30 is provided so as to be connected to the constant voltage control circuit 40. That is, the constant voltage control NMOS QN10~ QN12Control NMOS QN which is connected in series with each drain ofThirteen~ QNFifteenAre provided correspondingly. NMOS QN for selection controlThirteen~ QNFifteenHas a common source connected to the output line 102 of the constant voltage generation circuit, and the potential of the output line 102 substantially becomes the output voltage Vreg of the constant voltage generation circuit.
[0119]
The selection signal is a signal for selecting one of the NMOSs constituting the constant voltage control circuit having different threshold voltages, as in the example of the crystal oscillation circuit of the first embodiment. When SEL10 is high level, NMOS QN10 is selected, when SEL11 is high level, NMOS QN10 is selected.11Is selected, SEL12 is high level and NMOS QN12Can be selected. When the selection signals SEL10 to SEL12 are at a low level, respectively, the NMOS QN10~ QN12Can be respectively set to the non-selection state.
[0120]
NMOS QNs constituting the constant voltage control circuit 40 having different threshold voltages.10~ QN12In order to form the constant voltage Vreg formed by the constant voltage generating circuit in an optimal state, a current is caused to flow through one NMOS of the constant voltage control circuit 40 to connect the + input terminal of the operational amplifier OP to the + input terminal. The applied voltage, that is, the difference voltage from the applied voltage to the-input terminal can be selected, and the output signal of the operational amplifier OP, that is, the constant voltage Vreg can be controlled.
[0121]
That is, the input of the selection signals SEL10 to SEL12 to the selection control circuit 30 causes the NMOS QNThirteen~ QNFifteenIs controlled, and one NMOS formed with an optimum threshold voltage is selected. The method and circuit for switching the voltage levels of the selection signals SEL10 to SEL12 are the same as those shown in FIG. 3, and the selection signals SEL10 to SEL12 can be formed by the same switching method. Is omitted.
[0122]
Next, a method of selecting a constant voltage control circuit in the constant voltage generation circuit according to the present embodiment will be described. In the present embodiment, for example, the NMOS QN10The case of selecting is described.
[0123]
The selection signal SEL10 is set to the high level, and the selection control NMOS QNThirteenSince a high-level voltage is applied to the gate of the NMOS QNThirteenTurns on. Therefore, in the constant voltage control circuit 40, the NMOS QN10Is electrically connected to the power supply voltage Vss via the on-state NMOS QN1, thereby providing the constant voltage control NMOS QN1.10Can be selected.
[0124]
On the other hand, since both of the selection signals SEL11 and SEL12 are at the low level, the selection control NMOS QN14, QNFifteenAre applied with the selection signals SEL11 and SEL12, that is, a low-level signal.14, QNFifteenTurns off. Therefore, the constant voltage control NMOS QN11, QN12Is electrically disconnected from both power supplies and is not selected.
[0125]
FIG. 8 is a timing chart showing the relationship between the constant voltage Vreg and the selection signals SEL10 to SEL12. In FIG. 8, the horizontal axis represents time. Here, between the constant voltage | Vreg | and the ground voltage Vdd, the constant voltage | Vreg | increases as the difference voltage increases.
[0126]
First, when the selection signal SEL10 is set to the high level, as described above, the constant voltage can be represented by | Vreg | = α (| Vthp2 | + Vthn) (α: constant). Is α (| Vthp2 | + Vthn10). When the selection signal SEL10 is at the low level and the selection signal SEL11 is at the high level, the constant voltage | Vreg | becomes α (| Vthp2 | + Vthn11). When the selection signal SEL11 is at a low level and the selection signal SEL12 is at a high level, the constant voltage | Vreg | becomes α (| Vthp2 | + Vthn12). That is, the constant voltage | Vreg | when SEL10 is set to the high level is the lowest, and the constant voltage | Vreg | is highest when SEL3 is set to the high level.
[0127]
By the way, as described above, the selection of the NMOS included in the constant voltage control circuit 40 is performed by cutting the fuse in the IC inspection process by using a selection signal forming circuit similar to the circuit shown in FIG. Further, similarly to the first embodiment, in the selection signal forming circuit, information can be stored by using a nonvolatile memory, a storage element, or the like, instead of using an information storage method by blowing a fuse.
[0128]
In the selection of the NMOS included in the constant voltage control circuit, as described in the first embodiment, the constant voltage Vreg and the oscillation stop voltage Vsto are both | Vreg |> | Vsto | and | Vreg | Condition must be satisfied. As described above, the oscillation stop voltage Vsto is equal to the NMOS QN of the transistor constituting the oscillation inverter.0, PMOSQP0, The selection signal SEL10, SEL11, and SEL12 are sequentially set to a high level by controlling the voltage level applied to a test pad connected to a test circuit (not shown). Here, similarly to the test circuit described in the first embodiment, the test circuit is a circuit including a logic circuit that selectively forms the selection signals SEL10 to SEL12 based on a combination of input signals to the test pads. In this case, one or more test pads can be provided.
[0129]
And the constant voltage control NMOS QN10~ QN12Are sequentially turned on to change the constant voltage Vreg, and the constant voltage Vreg is measured by the monitoring pad MP connected to the output line 102. At this time, the IC test is performed in a wafer state, and the constant voltage Vreg is measured for each IC chip using the test circuit, the test pad, and the monitor pad provided in each IC chip. . At the time of measurement, only the constant voltage control circuit 40 and the selection control circuit 30 are activated, and the other elements are inactive.
[0130]
Then, as described in the first embodiment, the short-circuit current Is is measured in the oscillation inverter in the crystal oscillation circuit, and the optimum constant voltage Vreg that satisfies the above relationship is specified. Then, in the constant voltage generating circuit formed in the effective area of the IC chip, the fuse of the selection signal forming circuit, which is included in the constant voltage control circuit 40 and is connected to the specified optimal NMOS, is cut off, and the constant voltage control circuit 40 is used. Select one NMOS.
[0131]
As described above, the constant voltage generating circuit according to the present embodiment has been described. As described above, the constant voltage generating circuit according to the present embodiment forms the lowest possible constant voltage | Vreg | while securing an operation margin. Therefore, the present invention can be realized without significantly increasing the number of transistors, so that an optimum constant voltage can be set without significantly increasing the chip area, and a constant voltage Vreg with low power consumption can be obtained. be able to.
[0132]
In this embodiment, three types of constant voltage control NMOSs having different threshold voltages have been described. However, the number can be freely set without any particular limitation. Can be provided in correspondence with the number of constant voltage control NMOSs.
[0133]
In this embodiment, the threshold voltage is set by the constant voltage control NMOS QN.10> QN11> QN12In other words, Vthn10> Vthn11> Vthn12, but the present invention is not limited to this.10<QN11<QN12That is, Vthn10 <Vthn11 <Vthn12.
[0134]
In the first and second embodiments, the oscillation inverter of the crystal oscillation circuit can select the optimum oscillation inverter, and the constant voltage generation circuit can select the optimum NMOS of the constant voltage control circuit. Although described using an example, as shown in FIG. 1, the constant voltage generation circuit of the first embodiment and the crystal oscillation circuit of the second embodiment can be applied at the same time. Needless to say, this can be achieved. In this case, a first selection signal forming circuit for forming the selection signals SEL1 to SEL3 and a second selection signal forming circuit for forming the selection signals SEL10 to SEL12 are required, but the monitor pad is shared. be able to. Further, as described above, the circuit configurations of the first selection signal forming circuit and the second selection signal forming circuit can be the same. In the case of the configuration shown in FIG. 1, the optimum combination can be selected from the combination based on the measurement result of the short-circuit current of the oscillation inverter of the crystal oscillation circuit and the measurement result of the constant voltage Vreg. The yield can be improved while maintaining the characteristics, and the power consumption can be further reduced.
[0135]
The crystal oscillation circuit, the constant voltage generation circuit, the oscillation inverter unit selection circuit, and the selection signal forming circuit of the present invention have been described above with reference to the first and second embodiments. The formation circuit can be realized in various circuit configurations without being limited to the illustrated circuit configuration. For example, a fuse formed of polysilicon by a laser without cutting a high voltage may be used. Can also be cut.
[0136]
<Embodiment 3>
Next, FIG. 9 shows an example of an electronic circuit used for a wristwatch.
[0137]
This wristwatch incorporates a power generation mechanism (not shown). When the user wears the wristwatch and moves his arm, the rotating weight of the power generating mechanism rotates, the kinetic energy at that time rotates the power generating rotor at high speed, and an AC voltage is output from the power generating coil 300 provided on the power generation status side. You.
[0138]
This AC voltage is rectified by the diode 302 and charges the secondary battery 301. The secondary battery 301 forms a main power supply together with the booster circuit 303 and the auxiliary capacitor 304.
[0139]
In the present embodiment, when the voltage of the secondary battery is low and less than the driving voltage of the timepiece, the voltage of the secondary battery is converted into a high voltage that can be driven by the clock by the booster circuit 303 and stored in the auxiliary capacitor 304. Then, the clock circuit operates using the voltage of the auxiliary capacitor 304 as a power supply.
[0140]
This clock circuit is configured as a semiconductor device including the oscillation circuit and the constant voltage generation circuit described in the first and second embodiments, and uses a crystal resonator X′tal connected to the semiconductor device via a terminal. Then, an oscillation output having a preset oscillation frequency, here 32768 Hz, is generated, and the oscillation output is frequency-divided to output drive pulses having different polarities every second. This drive pulse is input to the drive coil 306 of the step motor connected to the clock circuit. As a result, the step motor (not shown) rotates the rotor each time a drive pulse is supplied, drives the second hand, minute hand, and hour hand (not shown) of the timepiece, and displays the time on the display panel in an analog manner.
[0141]
Here, the clock circuit 330 of the present embodiment generates the power supply voltage circuit section 220 driven by the voltage supplied from the main power supply described above, and a predetermined constant voltage Vreg lower than this value from the power supply voltage. The constant voltage generation circuit 210 described in the second embodiment and a constant voltage operation circuit unit 240 driven by the constant voltage Vreg are included.
[0142]
FIG. 10 shows a more detailed functional block diagram of the clock circuit 330.
[0143]
The constant voltage operation circuit section 240 includes the crystal oscillation circuit 200 described in the first embodiment partially including the externally connected crystal oscillator X′tal, the waveform shaping gate 201, and the high-frequency frequency dividing circuit. 202.
[0144]
The power supply voltage circuit section 220 includes a level shifter 203, a middle / low frequency dividing circuit 204, and another circuit 205. In the clock circuit of the present embodiment, the power supply voltage circuit section 220 and the constant voltage generation circuit 210 constitute a power supply voltage operation circuit section 240 driven by a voltage supplied from the main power supply.
[0145]
The crystal oscillation circuit 200 outputs a sine wave output having a reference frequency fs = 32768 Hz to the waveform shaping gate 201 using the crystal oscillator X′tal.
[0146]
The waveform shaping gate 201 shapes the sine wave output into a rectangular wave, and then outputs it to the high frequency frequency dividing circuit 202.
[0147]
The high frequency divider 202 divides the reference frequency 32768 Hz to 2048 Hz, and outputs the divided output to the middle / low frequency divider 204 via the level shifter 203.
[0148]
The middle / low frequency dividing circuit 204 further divides the signal divided to 2048 Hz to 1 Hz and inputs the divided signal to another circuit 205.
[0149]
The other circuit 205 includes a driver circuit that energizes and drives the coil in synchronization with the 1 Hz frequency division signal, and drives the timepiece drive step motor in synchronization with the 1 Hz frequency division signal.
[0150]
In the timepiece circuit of the present embodiment, in addition to the power supply voltage operation circuit section 240 in which the entire circuit is driven by the power supply voltage Vss supplied from the main power supply, the constant voltage operation circuit section 220 driven by the lower constant voltage Vreg Is provided for the following reason.
[0151]
That is, in such a timepiece circuit, it is necessary to reduce its power consumption in order to secure stable operation for a long time.
[0152]
Normally, the power consumption of a circuit increases in proportion to the frequency of the signal and the capacity of the circuit, and further increases in proportion to the square of the power supply voltage.
[0153]
Here, focusing on the clock circuit, in order to reduce the power consumption of the entire circuit, the power supply voltage supplied to each part of the circuit may be set to a low value, for example, Vreg. As described in the second embodiment, the constant voltage generation circuit 210 can form the minimum constant voltage Vreg within a range in which the oscillation operation of the crystal oscillation circuit 200 is compensated.
[0154]
Next, focusing on the signal frequency, the clock circuit can be roughly classified into a crystal oscillation circuit 200 having a high signal frequency, a waveform shaping gate 201, a high-frequency frequency dividing circuit 202, and a circuit 205 other than that. . The frequency of this signal is proportional to the power consumption of the circuit as described above.
[0155]
Therefore, the constant voltage generation circuit 210 of the present embodiment generates a lower constant voltage Vreg from the power supply voltage Vss supplied from the main power supply, and converts the generated lower constant voltage Vreg into a circuit section 230 that handles high-frequency signals, that is, , A waveform shaping gate 201 and a high frequency dividing circuit 202. As described above, by lowering the driving voltage supplied to the circuit 230 that handles the high-frequency signal, the power consumption of the entire timepiece circuit can be effectively reduced without increasing the load on the constant voltage generation circuit 210 so much. be able to.
[0156]
In the present embodiment, the level shifter 203 is provided between the high frequency divider 202 and the middle / low frequency divider 204 for the following reason.
[0157]
The peak value of the output of the high-frequency divider 202 is at the level of the constant voltage Vreg, and is smaller than the peak value of the voltage Vss of the main power supply. Therefore, even if the constant voltage Vreg level output of the high frequency divider 202 is directly input to the middle / low frequency divider 204 driven by the power supply voltage Vss, this input value is applied to the middle / low frequency divider. Since the voltage does not exceed the logic level voltage of the first stage of 202, the middle / low frequency dividing circuit 204 does not operate normally. Therefore, the level shifter 203 is used to raise the peak value of the output of the high frequency divider 202 from the constant voltage level to the power supply voltage level so that the middle and low frequency divider 204 operates normally.
[0158]
As described above, the clock circuit of the present embodiment and the electronic circuit including the same include the crystal oscillation circuit of the first embodiment and the constant voltage generation circuit of the second embodiment. In addition, since the minimum constant voltage can be supplied to the crystal oscillation circuit while the operation of the oscillation inverter secures a margin, the power consumption of the electronic circuit and the clock circuit can be reduced. Therefore, in the timepiece or the portable electronic device as described above, not only can the oscillation operation be performed stably, but also the life of the battery can be extended, and the usability of the watch or the portable electronic device can be improved. Can be improved.
[0159]
[Brief description of the drawings]
FIG. 1 is a schematic diagram of an oscillation circuit including a constant voltage generation circuit according to a second embodiment of the present invention and a crystal oscillation circuit according to the first embodiment.
FIG. 2 is a schematic diagram of an oscillation circuit having the crystal oscillation circuit according to the first embodiment of the present invention.
FIG. 3 is a schematic diagram of an oscillation inverter selection circuit according to the first embodiment of the present invention.
FIG. 4 is a schematic diagram of a timing chart showing a relationship between an oscillation stop voltage and a selection signal according to the first embodiment of the present invention.
FIG. 5 is a diagram for explaining a method for measuring the short-circuit current of the oscillation inverter according to the present invention, and a graph showing the relationship between the oscillation stop voltage and the short-circuit current.
FIG. 6 is a schematic diagram showing a gate waveform and a drain waveform of the crystal oscillation circuit according to the first embodiment of the present invention.
FIG. 7 is a schematic diagram of an oscillation circuit having a constant voltage generation circuit according to a second embodiment of the present invention.
FIG. 8 is a schematic timing chart showing a relationship between a constant voltage and a selection signal according to the second embodiment of the present invention.
FIG. 9 is a functional block diagram of a timepiece according to a third embodiment of the present invention.
FIG. 10 is a functional block diagram of a portable electronic device according to a third embodiment of the present invention.
FIG. 11 is a schematic diagram of an oscillation circuit having a conventional constant voltage generation circuit and a crystal oscillation circuit according to the present invention.
FIG. 12 is a graph showing a relationship between a constant current flowing through an NMOS connected to a constant current source and a gate-source voltage in a conventional constant voltage generation circuit.
FIG. 13 is a diagram showing a relationship between temperature and voltage with respect to a constant voltage | Vreg | and an oscillation stop voltage | Vsto |.
[Explanation of symbols]
10 ... Inverter group for oscillation
20P, 20N ... selection control circuit (crystal oscillation circuit)
30 ... Selection control circuit (constant voltage generation circuit)
40 ... constant voltage control circuit
INV1-3 ... Inverter unit for oscillation
P1 to P3 ... pad
OP: Operational amplifier
Rf: feedback resistor
CG, CD... Compensation capacitors
X'tal: quartz oscillator
U1 to U4 ... Unit circuit
F1 to F3: fuse circuit
f1 to f3 ... fuse
R1 to R3 ... resistance
I1 to I3 ... output inverter
200 Crystal oscillator circuit
201 ... waveform shaping gate
202 ・ ・ ・ High frequency divider circuit
203 ・ ・ ・ Level shifter
204: middle and low frequency divider circuit
205 ・ ・ ・ Other circuits
210 ・ ・ ・ Constant voltage generation circuit
220 ・ ・ ・ Power supply voltage circuit
230 ... constant voltage drive operation circuit section
240 ・ ・ ・ Power supply voltage operation circuit
300 ・ ・ ・ Generating coil
301 ... secondary battery
302 ... diode
303 booster circuit
304 Auxiliary capacitor
306 ・ ・ ・ Motor coil for watch

Claims (14)

  1. An oscillation inverter group including a plurality of oscillation inverters configured using transistors having different threshold voltages, wherein any one of the oscillation inverters is selectively used;
    A feedback circuit that has a crystal oscillator connected to the output side and the input side of the oscillation inverter group, inverts the phase of the output signal of the oscillation inverter group, and feeds back the oscillation inverter group to a feedback circuit;
    A selection circuit for selecting any one of the oscillation inverters from the oscillation inverter group;
    An oscillation circuit including
    The oscillation circuit is formed on the same substrate as the test circuit,
    In a state in which the quartz oscillator is not mounted, the test circuit selects each of the oscillation inverters, and measures the short-circuit current of each of the oscillation inverters, thereby selecting from the oscillation inverter group. An oscillation circuit, wherein one oscillation inverter is specified, and the selection circuit selects the oscillation inverter.
  2. In claim 1,
    An oscillator circuit, wherein the test circuit is connected to a test pad, and controls the voltage applied to the test pad to select each of the oscillation inverters via the test circuit.
  3. An oscillation inverter group including a plurality of oscillation inverters configured using transistors having different threshold voltages, wherein any one of the oscillation inverters is selectively used;
    A feedback circuit that has a crystal oscillator connected to the output side and the input side of the oscillation inverter group, inverts the phase of the output signal of the oscillation inverter group, and feeds back the oscillation inverter group to a feedback circuit;
    A selection circuit for selecting any one of the oscillation inverters from the oscillation inverter group;
    Including
    The selection circuit is provided corresponding to the oscillation inverter, and is connected to a plurality of pads, includes a plurality of unit circuits,
    The oscillation circuit, wherein each of the plurality of unit circuits includes any one of a fuse, a nonvolatile memory, and a storage element, and selects the oscillation inverter by applying a voltage to the pad. .
  4. In any one of claims 1 and 2,
    The selection circuit is provided corresponding to the oscillation inverter, and is connected to a plurality of pads, includes a plurality of unit circuits,
    The oscillation circuit, wherein each of the plurality of unit circuits includes any one of a fuse, a nonvolatile memory, and a storage element, and selects the oscillation inverter by applying a voltage to the pad. .
  5. In any one of claims 1 to 4 ,
    The oscillation inverter group includes a first oscillation inverter including a transistor having a first threshold voltage and a transistor having a second threshold voltage different from the first threshold voltage. A second oscillation inverter, and a third oscillation inverter including a transistor having a third threshold voltage different from the first and second threshold voltages. Oscillation circuit.
  6. In any one of claims 1 to 5 ,
    A power supply line of each of the oscillation inverters is connected to a first potential side and a second potential side different in potential from the first potential,
    The oscillation circuit according to claim 1, wherein the oscillation circuit performs amplitude by a potential difference between the first potential and the second potential.
  7. In claim 6 ,
    An oscillation circuit, wherein a potential difference between the first potential and the second potential is larger than an absolute value of an oscillation stop voltage of the oscillation inverter.
  8. In claim 6 or 7 ,
    While the short-circuit current flowing to the selected oscillation inverter satisfies the condition that the ON current of the transistor constituting the selected oscillation inverter is larger, the selection of the oscillation inverter is performed,
    An oscillator circuit, wherein a potential difference between the first potential and the second potential is a minimum voltage.
  9. An oscillation inverter group including a plurality of oscillation inverters configured using transistors having different threshold voltages, wherein any one of the oscillation inverters is selectively used;
    A feedback circuit that has a crystal oscillator connected to the output side and the input side of the oscillation inverter group, inverts the phase of the output signal of the oscillation inverter group, and feeds back the oscillation inverter group to a feedback circuit;
    A selection circuit for selecting any one of the oscillation inverters from the oscillation inverter group;
    Including
    While the short-circuit current flowing to the selected oscillation inverter satisfies the condition that the ON current of the transistor constituting the selected oscillation inverter is larger, the selection of the oscillation inverter is performed,
    An oscillator circuit, wherein a potential difference between the first potential and the second potential is a minimum voltage.
  10. An oscillation circuit, a constant voltage generation circuit, a semiconductor device including a test circuit,
    The oscillation circuit includes:
    An oscillation inverter group including a plurality of oscillation inverters configured using transistors having different threshold voltages, wherein any one of the oscillation inverters is selectively used;
    A first selection circuit for selecting one oscillation inverter from a plurality of oscillation inverters in the oscillation inverter group;
    A feedback circuit that inverts the phase of an output signal of the oscillation inverter group to which an external crystal oscillator and an output side and an input side are connected, and that performs feedback input to the oscillation inverter group;
    Including
    The constant voltage generating circuit,
    A constant voltage control circuit having one end connected to the first potential side, the other end connected to the constant voltage output side, including a plurality of transistors having different threshold voltages, and one of the transistors being selectively used;
    An operational amplifier in which a reference voltage of the constant voltage control circuit is input to one terminal and a given reference voltage is input to the other terminal;
    A transistor having one end connected to the other end of each transistor of the constant voltage control circuit, the other end connected to the second potential side, and a gate input voltage controlled by receiving the output of the operational amplifier;
    A second selection circuit that selects one transistor from a plurality of transistors in the constant voltage control circuit;
    Including
    The test circuit is connected to the oscillation circuit and the constant voltage generation circuit, respectively,
    A monitor terminal for monitoring an output voltage of the constant voltage generating circuit, and a monitor terminal provided to be connected to the test pad;
    In the inspection step, by controlling a voltage applied to the test pad while applying a voltage to the monitor terminal, each of the oscillation inverters is selected via the test circuit, and each of the oscillation inverters is selected. Measure the short-circuit current of each inverter,
    After measuring the short-circuit current, by controlling the voltage applied to the test pad, each transistor in the constant voltage control circuit is selected via the test circuit, and the output voltage of each transistor is monitored by the monitor terminal. Measure each at
    As long as the oscillation operation of the oscillation inverter can be ensured, the oscillation inverter in the oscillation circuit is selected by the first selection circuit, and the transistor in the constant voltage control circuit in the constant voltage generation circuit is A semiconductor device selected by a second selection circuit.
  11. A portable electronic device comprising the oscillation circuit according to any one of claims 1 to 9 , wherein an operation reference signal is formed from an oscillation output of the oscillation circuit.
  12. A timepiece comprising the oscillation circuit according to any one of claims 1 to 9 , wherein a timepiece reference signal is formed from an oscillation output of the oscillation circuit.
  13. 11. A portable electronic device including the semiconductor device according to claim 10 , wherein an operation reference signal is formed from an oscillation output of the oscillation circuit.
  14. A timepiece including the semiconductor device according to claim 10 , wherein the timepiece reference signal is formed from an oscillation output of the oscillation circuit.
JP02728097A 1997-01-27 1997-01-27 Oscillation circuit, semiconductor device, and portable electronic device and clock provided with these Expired - Fee Related JP3539110B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02728097A JP3539110B2 (en) 1997-01-27 1997-01-27 Oscillation circuit, semiconductor device, and portable electronic device and clock provided with these

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
JP02728097A JP3539110B2 (en) 1997-01-27 1997-01-27 Oscillation circuit, semiconductor device, and portable electronic device and clock provided with these
EP05008139A EP1569061A1 (en) 1997-01-22 1998-01-22 Constant-voltage generation circuit, semiconductor device, electronic equipment and timepiece
EP03022299A EP1378995B1 (en) 1997-01-22 1998-01-22 Oscillation circuit, constant voltage generation circuit, semiconductor device, electronic equipment and timepiece
PCT/JP1998/000240 WO1998032218A1 (en) 1997-01-22 1998-01-22 Oscillation circuit, electronic circuit, semiconductor device, electronic equipment and clock
US09/155,073 US6097257A (en) 1997-01-22 1998-01-22 Crystal oscillator circuit having transistor with back gate voltage control
DE1998620825 DE69820825T2 (en) 1997-01-22 1998-01-22 Oscillator circuit, electronic circuit, semiconductor component, electronic arrangement and clock
DE1998636392 DE69836392T2 (en) 1997-01-22 1998-01-22 Oscillator circuit, constant voltage generator circuit, semiconductor device, electronic device and timepiece
EP19980900699 EP0905877B1 (en) 1997-01-22 1998-01-22 Oscillation circuit, electronic circuit, semiconductor device, electronic equipment and clock
CN 98800298 CN1183658C (en) 1997-01-22 1998-01-22 Oscillation circuit, electronic circuit, semiconductor device, electronic equipment and clock
HK99105502A HK1020399A1 (en) 1997-01-22 1999-11-26 Oscillation circuit, electronic circuit, semiconductor device, electronic equipment and clock.

Publications (2)

Publication Number Publication Date
JPH10213686A JPH10213686A (en) 1998-08-11
JP3539110B2 true JP3539110B2 (en) 2004-07-07

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JP2001344039A (en) 2000-03-31 2001-12-14 Seiko Epson Corp Information processor and method for controlling the same and control program of the same
JP2012049925A (en) * 2010-08-27 2012-03-08 Ememory Technology Inc Voltage supply circuit for crystal oscillation circuit

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