JP2006084382A - Electronic clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic clock providing stable operation against fluctuation of a supply voltage VSS by realizing a constant voltage power circuit wherein a constant voltage output Vreg does not fluctuate even when an electric potential of the supply voltage VSS fluctuates, without substantially increasing current consumption. <P>SOLUTION: The electronic clock is provided with: the constant voltage power circuit comprising a reference voltage source; a differential amplification circuit; and an output MOS transistor. The constant voltage power circuit increases an operating current for only a predetermined period including and slightly longer than a period of driving a load with a comparatively large driving current such as a motor, and responsiveness of the constant voltage power circuit is improved with respect to the fluctuation of the supply voltage VSS. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic timepiece including a constant voltage power supply circuit that outputs a voltage lower than a power supply voltage.

  Increasing the duration of electronic timepieces has long been desired, and recently there are solar power generation clocks and self-winding power generation clocks that use energy generated by light irradiation and arm movement, depending on the energy generated. The problem is how to extend the life of a charged secondary battery after full charge. The power consumption of a timepiece is large for driving a time display means such as a motor or a liquid crystal. However, it is also important to reduce the power consumption of the circuit, and various proposals have been made.

The power consumption of an electronic circuit greatly depends on the operating voltage. In a CMOS logic circuit often used in a clock circuit, the charge / discharge current of the gate capacitance is mainly used. Therefore, the power consumption is proportional to the square of the operating voltage. Therefore, how to operate the circuit at a low voltage is a big point in reducing the power consumption.

  As a battery that is an energy source, a silver battery, a large-capacity lithium battery, or the like is used. The battery voltage is about 1.5 V for a silver battery and about 3 V for a lithium battery. If the watch circuit is directly operated at such a high voltage, the power consumption becomes large. Therefore, a constant voltage power supply circuit is used as a means for reducing the power consumption, and a part of the watch circuit is made more than the power supply voltage. Systems that operate at low voltages are being considered.

  FIG. 6 shows a block diagram of an example of a low power consumption timepiece system using a conventional constant voltage power supply circuit. The power supply 201 is used as an energy source, and a negative power supply voltage VSS is generated with VDD as a reference (GND). The power source 201 is a silver battery, a lithium battery, or a lithium ion battery that is a secondary battery. A constant voltage power supply circuit 701 having a conventional structure outputs a constant voltage Vreg that is lower than the power supply voltage VSS. Here, the voltage of Vreg is lower that the absolute value of the potential difference with respect to VDD as the reference (GND) is smaller, and the potential of the constant voltage Vreg is higher than the power supply voltage VSS. Unless otherwise noted, the magnitude and magnitude of the voltage are the same in the following description. A detailed description of the constant voltage power supply circuit 701 of the prior art will be given later.

  The constant voltage output Vreg (115) of the constant voltage power supply circuit 701 is connected to the oscillation circuit 204, the frequency divider circuit, and the control circuit 205. An oscillation clock is output based on the resonance frequency of the crystal unit 203 by the oscillation circuit 204 configured by a CMOS inverter. A frequency dividing circuit and control circuit 205 lowers the frequency of the oscillation clock to 1 Hz and generates a motor drive pulse.

  Then, the drive circuit 206 drives the motor 702. The drive circuit 206 is composed of a transistor with a large driving force in order to flow a large current to the motor 702. By driving the motor 702, the pointer of the time display means rotates to display the time.

The constant voltage power supply circuit 701 outputs a constant voltage output Vreg (115) lower than the power supply voltage VSS. Since the oscillation circuit 204, the frequency dividing circuit and the control circuit 205 operate at a constant voltage output Vreg (115) lower than the power supply voltage VSS, the oscillation circuit 204 and the frequency division are compared with the case where the operation is performed directly at the power supply voltage VSS. There is a great effect in reducing the power consumption of the circuit and the control circuit 205.

  Next, an example of a conventional constant voltage power supply circuit 701 is shown in the circuit diagram of FIG. This is a case where a CMOS circuit is configured on an n-type substrate. The pMOS transistors 101 and 102, the nMOS transistors 103 and 104, and the reference resistor 113 constitute a reference voltage source 116. The pMOS transistor 105 is a constant current circuit, the pMOS transistors 106 and 107 are differential input circuits, and the nMOS transistors are current mirror circuits. The differential amplifier circuit 117 is configured by 108 and 109, the output circuit 118 is configured by the pMOS transistor 110 which is a constant current circuit, and the output nMOS transistor 112, and the constant voltage output Vreg (115) is output. As shown in FIG. 6, an oscillation circuit 204, a frequency dividing circuit, and a control circuit 205 are connected to the constant voltage output Vreg (115) of the constant voltage power supply circuit 701 in FIG.

  As shown in FIG. 7, a constant voltage output Vreg (115) is output from the connection point between the pMOS transistor 110, which is a constant current circuit, and the output nMOS transistor 112. The pMOS transistor 110, which is a constant current circuit, operates as a load resistor and is output by the differential amplifier circuit 117 so that the reference voltage output Vref (114) of the reference voltage source 116 and the constant voltage output Vreg (115) have the same voltage. The gate voltage of the nMOS transistor 112 is controlled to output a constant voltage output Vreg (115) lower than the power supply voltage VSS. The capacitor Cc is a phase compensation capacitor and prevents the constant voltage power supply circuit 701 from oscillating.

With the constant voltage power supply circuit 701 described above, the oscillation circuit 204 and the frequency dividing circuit and the control circuit 205 can be operated with a constant voltage output Vreg (115) lower than the output voltage of the power supply 201. Such conventional techniques can be found in, for example, Patent Documents 1 and 2 below.
JP-A-8-43562 (5th page, FIG. 6, FIG. 7) JP 2002-149251 A

  The operating current (current consumption) of the conventional constant voltage power supply circuit 701 used in the electronic timepiece is set to about several nA to several tens of nA in order to keep the battery life as long as possible. Therefore, the response frequency that can cope with the fluctuation of the load and the power supply voltage VSS is low. Therefore, it is designed on the assumption that the fluctuation of the power supply voltage VSS is small even when the load is light and a relatively large current flows, such as when the motor is driven.

  However, in the case of a wrist watch for women (hereinafter referred to as “women's watch”), the size is often smaller than that of a wrist watch for men, and it may be difficult to use a capacitor having a capacity sufficient to suppress fluctuations in the power supply voltage VSS. is there. In addition, it is often necessary to use a battery having a small internal impedance and a large internal impedance. Therefore, when a relatively large current flows when the motor is driven, a voltage drop due to internal impedance may occur, and the battery voltage (power supply voltage VSS) may become unstable.

As a change in the battery voltage (power supply voltage VSS), a change in the current flowing through the drive coil when the motor is driven is directly affected. The drive coil of the motor 702 has an inductance of about 2H and has a resistance of about 2 kΩ. Accordingly, the rise and fall time constants of the current flowing through the drive coil are about 1 ms as shown by the following formula, and are current changes having a frequency component of about 1 Khz.

Time constant τ = L (coil inductance) / R (coil resistance)
= 2 (H) / 2k (Ω) = 1 ms

Therefore, if the constant voltage power supply circuit 701 has a response frequency of about 1 kHz, the constant voltage output Vreg (115) does not fluctuate. However, as described above, since the operating current of the conventional constant voltage power supply circuit is only a few tens of nA, the response frequency due to the fluctuation of the power supply voltage is about several tens Hz, and the constant voltage output cannot respond to the fluctuation of the power supply voltage. Vreg (115) also shakes.

  FIG. 8 shows how the constant voltage output Vreg (115) of the conventional constant voltage power supply circuit 701 fluctuates with the fluctuation of the potential of the power supply voltage VSS when a current is passed through the motor 702 in the conventional electronic timepiece of FIG. Show. Since the frequency of the potential fluctuation of the power supply voltage VSS is about 1 kHz, the constant voltage output Vreg fluctuates without the conventional constant voltage power supply circuit 701 responding.

  If this fluctuation is too large, it may cause oscillation stop and malfunction of the frequency divider and control circuit 205. As a countermeasure, in order to improve the responsiveness of the constant voltage power supply circuit 701, the current value of the pMOS transistor 105 which is the constant current circuit of the differential amplifier circuit 117 and the pMOS transistor 110 which is the constant current circuit of the output circuit 118 in FIG. By increasing the operating current of the differential amplifier circuit 117 and the output circuit 118, it is possible to make the constant voltage output Vreg (115) difficult to shake.

  However, with the conventional electronic timepiece, if the above measures are taken to improve the response, the current consumption of the constant voltage power supply circuit increases, and the effect of providing the constant voltage power supply circuit to reduce power consumption is halved. Resulting in. An object of the present invention is to provide an electronic timepiece having a constant voltage power supply circuit that prevents a constant voltage output Vreg from being fluctuated even if the potential of a power supply voltage VSS fluctuates without increasing current consumption.

  The electronic timepiece of the present invention includes a constant voltage power supply circuit, the constant voltage power supply circuit generates a reference voltage, an output circuit that generates a constant voltage output based on the reference voltage, and a constant voltage output And a reference voltage to generate a control voltage for controlling a constant voltage output to a desired voltage. In order to achieve the above object, a constant voltage power supply circuit is provided in a predetermined period. The operation current of the differential amplifier circuit and the output circuit is increased.

  In this way, a specific structure for temporarily increasing the operating current of the differential amplifier circuit and the output circuit is a constant current circuit that is operated only for a predetermined period in addition to the constant current circuit that is always operating. It is to provide.

  According to the electronic timepiece of the invention, a constant current circuit that operates only for a predetermined period and a current flowing through a constant current circuit that is always operating for a period slightly longer than a period for operating a load having a relatively large operating current such as a motor. Is added to increase the operating current of the differential amplifier circuit and the output circuit of the constant voltage power supply circuit, so that the power supply can be increased while driving the motor without increasing the average current consumption. An electronic timepiece having a constant voltage power supply circuit in which the constant voltage output Vreg does not fluctuate even when the potential of the voltage VSS fluctuates can be realized.

  Hereinafter, preferred embodiments of an electronic timepiece according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an electronic timepiece according to the present invention, and FIG. 2 is a circuit diagram showing details of a constant voltage power supply circuit 202 in the block diagram of FIG. First, a low power consumption timepiece system using the constant voltage power supply circuit of the present invention will be described with reference to the block diagram of FIG.

The electronic timepiece of FIG. 1 drives a power supply 201, an oscillation circuit 204, a frequency divider and control circuit 205, a constant voltage power supply circuit 202 that supplies a voltage lower than the power supply voltage to these circuits, and a time display means 207. And a driving circuit 206. This electronic timepiece uses a power supply 201 as an energy source and generates a power supply voltage VSS. The power source 201 is composed of a silver battery, a lithium battery, or a lithium ion battery that is a secondary battery. An oscillation clock is output based on the resonance frequency of the crystal unit 203 by the oscillation circuit 204 configured by a CMOS inverter.

  The frequency of the oscillation clock is lowered to 1 Hz by the frequency divider and control circuit 205, and a control signal for the time display means 207 is generated. The oscillation circuit 204, the frequency divider circuit, and the control circuit 205 operate at a constant voltage determined in advance by the constant voltage power supply circuit 202. Then, the time display device 207 is driven by the drive circuit 206. The drive circuit 206 includes a transistor having a large channel width in order to flow a large current to the time display device 207. The time display means 207 is a hand in an analog timepiece, and it is a motor that moves the hand. In a digital watch, it is a liquid crystal display element.

  Then, once a second, a drive pulse is generated from the frequency divider and control circuit 205 to drive the time display device 207. When the drive pulse is generated or just before that, the frequency divider and control circuit 205 determines the time. The voltage power circuit control signal CNT (123) is supplied to the constant voltage power circuit 202 to increase the operating current of the constant voltage power circuit 202.

  Next, an embodiment of the constant voltage power supply circuit 202 according to the present invention will be described with reference to FIG. The constant voltage power supply circuit 202 is composed of a reference voltage source 116 constituting a reference voltage generating circuit, a differential amplifier circuit 117, and an output circuit 118. First, the reference voltage source 116 will be described. The reference voltage source 116 constitutes a reference voltage source using a band gap reference voltage by the four MOS transistors of the pMOS transistors 101 and 102 and the nMOS transistors 103 and 104 and the reference resistor 113.

In this reference voltage source 116, the voltage VR generated across the reference resistor 113 is expressed by the following equation (1).

VR = (kT / q) × ln ((S2 / S1) × (S4 / S3)) (1)
k: Boltzmann constant q: Amount of charge of one electron (Coulomb)
T: Absolute temperature

S1 to S4 are dimension ratios of the channel width “W” and the channel length “L” of the MOS transistors 101 to 104 shown in FIG.

Therefore, the current IR flowing through the pMOS transistor 102 is expressed by the following formula (2), where R is the resistance value of the reference resistor 113.

IR = VR / R = (kT / qR) × ln ((S2 / S1) × (S4 / S3)) (2)

Further, since the gates of the two n-channel MOS transistors 103 and 104 are connected, a current mirror operation is performed. The current I1 flowing through the p-channel MOS transistor 101 having the dimension ratio S1 and the n-channel MOS transistor 104 having the dimension ratio S4 shown in FIG. 2 is determined by the ratio of S3 and S4. Therefore, the current IR flows through the nMOS transistor 103 having the dimension ratio S3 according to the following formula (3).

I1 = IR × (S4 / S3) (3)

I1 is constant regardless of the power supply voltage VSS. Therefore, the reference voltage output Vref (114
), The source-drain voltage Vds when the current I1 flows through the pMOS transistor 101 is output and is constant regardless of the power supply voltage VSS.

  Next, the differential amplifier circuit 117 will be described. The differential amplifier circuit 117 includes pMOS transistors 105 and 120 which are constant current circuits, a pMOS transistor 119 which operates as a switch for connecting or disconnecting the pMOS transistor 120 to GND, pMOS transistors 106 and 107 serving as a differential input circuit, a current mirror It consists of nMOS transistors 108 and 109 of the circuit.

  The pMOS transistor 105, which is a constant current circuit, has a gate connected to the pMOS transistor 101 of the reference voltage source 116, and performs a current mirror operation. Further, the pMOS transistor 120 which is a constant current circuit is also connected to the pMOS transistor 101 of the reference voltage source 116 and the gate thereof, so that the potential of the source of the pMOS transistor 120 is maintained while the pMOS transistor 119 operating as a switch is on. Becomes almost GND, the pMOS transistor 120 also performs a current mirror operation. Therefore, the current Idef1 flowing through the pMOS transistor 105, which is a constant current circuit, and the current Idef2 flowing through the pMOS transistor 120 are currents determined by the ratios of S1 and S5 and S1 and S20, which are the W / L ratios of the pMOS transistors 101, 105, and 120. It becomes.

  Therefore, the operating current of the differential amplifier circuit 117 while the pMOS transistor 119 operating as a switch is on is a current Idef1 + Idef2 which is the sum of the current Idef1 flowing through the pMOS transistor 105 and the current Idef2 flowing through the pMOS transistor 120. The operating current is increased by Idef2 as compared to the period in which the operating pMOS transistor 119 is off, and the response of the differential amplifier circuit is improved.

  Here, if the W / L ratio S20 of the pMOS transistor 120 which is a constant current circuit is set to about 100 times the W / L ratio S5 of the pMOS transistor 105, the period during which the pMOS transistor 119 operating as a switch is on is differential. The operating current of the amplifier circuit 117 is 100 times as long as the pMOS transistor 119 operating as a switch is off, and the responsiveness is improved 100 times.

  The pMOS transistor 119 operating as a switch is turned on when the gate is at “L” level and turned off when it is at “H” level, and is controlled by a constant voltage power supply circuit control signal CNT (123) generated by the frequency divider and control circuit 205.

  The gate of the normal input pMOS transistor 106 is connected to the gate and drain of the pMOS transistor 101 of the reference voltage source 116, that is, the reference voltage output Vref (114), and the inverting input which is the gate of the pMOS transistor 107 is output. The differential amplifier circuit 117 is connected to the constant voltage output Vreg (115) of the circuit 118 and operates so that the inverting input constant voltage output Vreg (115) is the same as the non-inverting input reference voltage Vref (114). Therefore, both have the same potential. The nMOS transistors 108 and 109 of the current mirror circuit operate at a constant current and have an effect of increasing the voltage gain of the differential amplifier circuit 117.

  Finally, the output circuit 118 will be described. The output circuit 118 includes pMOS transistors 110 and 122 which are constant current circuits, a pMOS transistor 121 which operates as a switch for connecting or disconnecting the pMOS transistor 122 which is a constant current circuit to the GND potential, and an output nMOS transistor 112. The gate of the pMOS transistor 110 which is a constant current circuit is connected to the gate of the pMOS transistor 101 of the reference voltage source 116 and performs a current mirror operation.

  Further, since the gate of the pMOS transistor 122 which is a constant current circuit is also connected to the gate of the pMOS transistor 101 of the reference voltage source 116, if the pMOS transistor 121 which operates as a switch is on, the pMOS which is a constant current circuit is turned on. Since the potential of the source of the transistor 122 is almost GND, a current mirror operation is performed.

  Therefore, the current Iout1 flowing through the pMOS transistor 110 which is a constant current circuit and the current Iout2 flowing through the pMOS transistor 122 which is a constant current circuit are S1 and S10 which are W / L ratios of the pMOS transistors 101, 110 and 122, and S1 and S22. It is determined by the ratio.

  If the pMOS transistor 121 operating as a switch is on, the current flowing through the output circuit becomes Iout1 + Iout2 which is the sum of the current Iout1 flowing through the pMOS transistor 110 which is a constant current circuit and the current Iout2 flowing through the pMOS transistor. The frequency characteristics of 118 are improved.

  As described in the description of the differential amplifier circuit 117, the gate of the pMOS transistor 121 operating as a switch is turned on at “L” level and turned off at “H” level, and a constant voltage generated from the frequency divider and the control circuit 205. It is controlled by the power supply circuit control signal CNT (123).

  An output nMOS transistor 112 having a large W / L ratio through which a large current can flow is connected to the drains of the pMOS transistors 110 and 122 which are constant current circuits. The gate of the output nMOS transistor 112 is controlled by a control voltage which is the potential at the point where the drains of the pMOS transistor 106 and the nMOS transistor 108 of the differential amplifier circuit 117 are connected. As described above, the constant voltage output Vreg (115) is The differential amplifier circuit 117 outputs the same voltage as the reference voltage Vref (114).

  Since the constant voltage output Vreg (115) outputs the same potential as the reference voltage Vref (114), the constant voltage output Vreg (115) is constant voltage even if the operating currents of the differential amplifier circuit 117 and the output circuit 118 of the constant voltage power supply circuit are increased 100 times. There is no effect on the output Vreg (115). Therefore, the operating current of the constant voltage power supply circuit 202 can be increased without affecting the operations of the oscillation circuit 204, the frequency dividing circuit, and the control circuit 205.

  Further, when it is desired to increase the constant voltage output Vreg (115) from the relationship of the operating voltage of the oscillation circuit 204, the frequency dividing circuit, and the control circuit 205, the source of the pMOS transistor 101 of the reference voltage source 116, as shown in FIG. By inserting the nMOS transistor 111 between the gate and the drain of the nMOS transistor 104, the reference voltage output Vref (114) is increased by the source-drain voltage Vds when the current I1 flows through the nMOS transistor 111.

  Since the gate voltages of the differential input pMOS transistors 106 and 107 of the differential amplifier circuit 117 operate to be the same voltage, the constant voltage output Vreg (115) also increases. If it is desired to further increase the constant voltage output Vreg (115), it can be realized by connecting nMOS transistors 111 in multiple stages.

FIG. 3 shows that the power supply voltage VSS has an amplitude V1 in the frequency range of DC to 100 kHz when the operating current is increased to about 100 times that in the steady state and in the case of the steady state operating current. The result of having measured the fluctuation | variation (responsiveness) of the constant voltage output Vreg at the time of shaking by is shown. In the case of constant operating current (= 10 nA), the fluctuation of the power supply voltage VSS does not affect the constant voltage output Vreg until about DC to 10 Hz, and at a frequency higher than this, the constant voltage output Vreg is V1. Shake with voltage. On the other hand, when the operating current is set to 1 μA, which is 100 times the steady state, it can be seen that the constant voltage output Vreg is not affected by the fluctuation of the power supply voltage VSS up to about DC to 1 kHz, and the responsiveness is improved. Represents.

  As described above, the change in the operating current of the motor driving coil is about 1 kHz. Therefore, if the operating current of the constant voltage power supply circuit is increased 100 times during the period in which the current is supplied to the driving motor, the current flows to the driving motor. Even if the power supply voltage VSS fluctuates, the constant voltage output Vreg of the constant voltage power supply circuit does not fluctuate.

Here, the time during which a current is supplied to the drive motor is about 4 ms. For 7 ms with a slight margin, the operating current of the constant voltage power supply circuit is set to 1 μA, which is 100 times that of the steady state. As the average current because it is driven once per second

1 μA × 7 ms / 1000 ms (1 second) = 0.7 nA

Thus, it is negligible with respect to the operating current of about 10 nA of the constant voltage power supply circuit in a steady state. That is, if the operating current of the constant voltage power supply circuit is increased by a factor of 100 during a slightly longer period including the period in which current is flowing through the drive motor, the increase in current consumption is negligible.

In addition, the influence of the internal impedance of the battery voltage when the operating current of the constant voltage power supply circuit is increased by 100 times is that the internal impedance of the battery for women is high and is about 100Ω. The influence of the voltage drop on the operating current of the circuit is
100Ω (internal impedance) × 1 μA (operating current) = 0.1 mV
Thus, the operations of the oscillation circuit 204, the frequency divider circuit, and the control circuit 205 that are normally operated at about 0.7 V or more are not affected.

  Next, when a large current flows from the battery 201 by driving the motor which is the time display means 207, to the constant voltage output Vreg of the constant voltage power supply circuit of the present invention when the power supply voltage VSS fluctuates due to the internal impedance of the battery. The state of the influence will be described with reference to FIG.

  Once a second, a motor drive pulse is generated in the drive circuit from the frequency divider and control circuit 205 and a current is passed through the drive coil to drive the motor, but at the same time or a little earlier than this, constant voltage power supply circuit control The signal CNT is set to “L”. In FIG. 2, the pMOS transistors 119 and 121 operating as switches are turned on, and the operating current of the constant voltage power supply circuit 202 is increased by 100 times to improve the response. When the motor drive pulse is stopped after 4 ms, no current flows through the drive coil. However, since the motor then stops while continuing to vibrate, a counter electromotive voltage is generated at this time, and a current flows through the drive coil. This continues for 2-3 ms after the motor drive pulse stops.

  The current flowing through the coil due to the reverse voltage also changes at a frequency of about 1 kHz. As shown in FIG. 4, the constant voltage power supply circuit responds if the change in the current flowing through the drive coil is about 1 kHz by continuing the constant voltage power supply circuit control signal CNT for 3 ms after the motor drive pulse is stopped, for example. Therefore, even if the power supply voltage VSS fluctuates, the constant voltage output Vreg does not fluctuate. If the constant-voltage power supply circuit control signal CNT is set to “H” after the drive coil current has subsided, the operating current will decrease, and it will operate at the steady operating current (10 nA) until the next drive pulse is generated (after about 1 second). Keep doing.

Therefore, as described above, the constant-current power supply circuit operating current is increased by 100 times only during a slightly longer period including the period during which current is passed through the drive coil, so that the current is constant regardless of current flow through the drive coil. The voltage output Vreg can be stabilized. Therefore, the constant voltage power supply circuit 202 in which the constant voltage output Vreg does not fluctuate even when the potential of the power supply voltage VSS fluctuates can be realized without increasing the current consumption. The frequency divider and control circuit 205 can operate stably.

It is a block diagram which shows the electronic timepiece using the constant voltage power supply circuit in this invention. It is a circuit diagram which shows the constant voltage power supply circuit of the electronic timepiece in this invention. It is the result of measuring the fluctuation of the constant voltage output Vreg when the power supply voltage VSS of the constant voltage power supply circuit in the present invention is fluctuated with the amplitude V1 in the range of DC to 100 kHz. It is a wave form diagram which shows the output waveform of the constant voltage output Vreg when the power supply voltage VSS fluctuates at the time of the motor drive of the constant voltage power supply circuit of the electronic timepiece in this invention. FIG. 4 is a circuit diagram in which the constant voltage output Vreg is further increased in the constant voltage power supply circuit of the electronic timepiece according to the invention. It is a block diagram which shows the electronic timepiece using the constant voltage power supply circuit in a prior art. It is a circuit diagram which shows the constant voltage power supply circuit of the electronic timepiece in a prior art. It is a wave form diagram which shows the output waveform of the constant voltage output Vreg when the power supply voltage VSS fluctuates at the time of the motor drive of the constant voltage power supply circuit of the electronic timepiece in a prior art.

Explanation of symbols

101 pMOS transistor of size ratio S102 pMOS transistor of size ratio S103 nMOS transistor of size ratio S104 nMOS transistor of size ratio S4 105 pMOS transistor of size ratio S5 106 normal input transistor of differential amplifier circuit 107 difference Inverting input transistor of dynamic amplifier circuit 108 Current mirror nMOS transistor 109 Current mirror nMOS transistor 110 pMOS transistor with dimension ratio S10 111 nMOS transistor 112 output nMOS transistor 113 reference resistor 114 reference voltage output Vref
115 Constant voltage output Vreg
116 Reference voltage source 117 Differential amplifier circuit 118 Output circuit 119 pMOS transistor 120 operating as a switch 120 pMOS transistor having a size ratio S20 121 pMOS transistor operating as a switch 122 pMOS transistor having a size ratio S22 123 Constant voltage power supply circuit control signal CNT
DESCRIPTION OF SYMBOLS 201 Power supply 202 Constant voltage power supply circuit by this invention 203 Crystal oscillator 204 Oscillation circuit 205 Frequency dividing circuit and control circuit 206 Drive circuit 207 Time display means 701 Constant voltage power supply circuit 702 according to prior art

Claims (3)

A reference voltage generating source for generating a reference voltage, an output circuit for generating a constant voltage output based on the reference voltage from the reference voltage generating source, and comparing the constant voltage output of the output circuit with the reference voltage In an electronic timepiece including a constant voltage power supply circuit including a differential amplifier circuit that generates a control voltage for controlling the constant voltage output to a desired voltage,
The electronic timepiece characterized in that the constant voltage power supply circuit increases the operating currents of the differential amplifier circuit and the output circuit during a predetermined period as compared to a steady operation. The electronic timepiece according to claim 1,
Each of the differential amplifier circuit and the output circuit includes a constant current circuit that performs steady operation, and a constant current circuit that is additionally provided via a switch, and the additional constant current circuit is determined in advance. An electronic timepiece configured to operate only when a switch is turned on for a period of time, and a flowing current is added to a current of a constant current circuit that performs the steady operation, thereby increasing an operating current of the differential amplifier circuit and the output circuit. The electronic timepiece according to claim 1,
The predetermined period of time for increasing the operating currents of the differential amplifier circuit and the output circuit from that during steady operation is from the start of driving the time display means of the electronic timepiece or immediately before the predetermined time elapses after the end of driving. An electronic timepiece characterized by being.

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