JPH10213686A - Oscillation circuit, constant voltage generating circuit semiconductor device, and portable electronic device and timepiece equipped with them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow low power consumption driving and stable oscillation, by adjusting the threshold voltage of a transistor in an oscillation inverter which constitutes an oscillation circuit. SOLUTION: A quartz oscillation circuit constitutes oscillation inverter group 10 with oscillation inverter units INV1-INV3. Transistors NMOSQN4 -QN6 and PMOSQP4 -QP6 , of the oscillation inverter units INV1-INV3 are formed with different threshold voltages. Selection control circuits 20P and 20N comprising selection control transistors PMOSQP7 -QP9 and NMOSQN7 -QN9 adjust the transistor outputs of the oscillation inverter units INV1-INV3 among the oscillation inverter group 10 to an optimum voltage. Thus, oscillation operation is stabilized for a longer life of a battery.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit, a constant voltage generation circuit, a semiconductor device, a portable electronic device and a timepiece equipped with the same, and more particularly, to an oscillation inverter and a constant current included in the oscillation circuit. The present invention relates to a voltage generation circuit.

[0002]

2. Description of the Related Art Conventionally, an oscillation circuit using a crystal oscillator has been widely used in watches, portable telephones, computer terminals, and the like. In such a portable electronic device or watch, it is necessary to save power consumption and extend the life of the battery.

[0003] From the viewpoint of saving power consumption, the present inventor analyzed the power consumption of an electronic circuit used in a portable electronic device, particularly a wristwatch. From this analysis, it has been confirmed that, of the electronic circuits formed on the printed circuit board, in the semiconductor device, the power consumption of the oscillation circuit portion occupies a larger proportion than other circuit portions. That is, it has been found that reducing power consumption in an oscillation circuit portion of an electronic circuit used in a portable electronic device is effective in extending the life of a battery used.

FIG. 11 shows an example of a conventional crystal oscillation circuit and a constant voltage generation circuit.

[0005] This crystal oscillation circuit comprises a crystal oscillator X'ta
1, an oscillation inverter INV0, and a high resistance Rf forming a feedback circuit. The feedback circuit includes, in addition to the resistor Rf, capacitors C _D and C _G for phase compensation, and uses the drain output of the oscillation inverter INV0 as a gate input whose phase has been inverted by 180 degrees to set the gate of the oscillation inverter INV0. This is to input feedback to.

Conventional oscillating inverter INV0 used in such a crystal oscillation circuit, (hereinafter referred to as PMOS) pair of P-type field effect transistor QP _0, (hereinafter referred to as NMOS) N-type field effect transistor comprises a QN ₀ , Each PM
The gates of OSQP ₀ and NMOS QN ₀ are configured to function as an input side, and the drain is configured to function as an output side. The transistors QP ₀ and QN ₀ have their drains connected to each other, and their sources connected to the ground voltage Vdd side and the negative constant voltage Vreg side, respectively.

In the crystal oscillation circuit having the above configuration, when a constant voltage Vreg is applied to the oscillation inverter INV0, the output of the oscillation inverter INV0 is inverted by 180 degrees and fed back to the gate. Thus, the PMOS QP ₀ , NM constituting the oscillation inverter INV ₀
OSQN ₀ is alternately turned on and off, the oscillation output of the crystal oscillator circuit gradually increases, and finally the crystal oscillator X′tal
Performs a stable oscillation operation.

[0008] However, in the conventional crystal oscillator circuit, also at the time of start-up, even after stable oscillation, always PMOSQP _0, NMOSQN ₀
Since both transistors are turned on and off alternately, there is a problem described below.

In the conventional crystal oscillation circuit, the PMOS QP ₀ and the NMOS QN ₀ are alternately turned on and off even after stable oscillation. In this case, when it is turned on driving the PMOSQP ₀ is directly discharged most of the charging energy to the crystal oscillator X'tal. Therefore, in the next charging cycle, the crystal unit X′tal must be charged from the beginning, and the present inventor has stated that this charging is
It has been found that this is a major problem in reducing the power consumption of the entire circuit.

That is, in a state where the crystal oscillation circuit is oscillating stably, a stable oscillation state is maintained even if the power charged in the crystal oscillator X'tal is not completely discharged in a charge / discharge cycle. be able to. However, in the conventional circuit, in this charge / discharge cycle, the cycle of discharging the charge power of the crystal unit X'tal as it is and repeating the charge is repeated, which is a major factor in increasing the power consumption of the entire circuit. I was

Further, in such a crystal oscillation circuit, the absolute value of the oscillation-stopped voltage | Vsto |, the NMOSQN ₀
The threshold voltage Vthn0, the QP ₀ threshold voltage of the PMOS V
If thp0, it can be expressed as in Equation 1.

Equation 1: | Vsto | = K · (| Vthp0 | + Vthn0) Here, the constant K is 0.8 to 0.9, and | Vthp0 | indicates the absolute value of Vthp0. Thus, the oscillation stop voltage Vs
to is the threshold voltage Vthn0,
It depends on the threshold voltage Vthp0 of the PMOS.

On the other hand, the constant voltage generating circuit includes an operational amplifier OP
And a negative (hereinafter referred to as-) input voltage control PMOS
QP ₂ and plus (less than + and referred to) input voltage control for NMOSQ
N ₂ and an output NMOS QN ₁ . That is, the operational amplifier of the OP - input terminal, a gate connected to the drain, and is connected to a constant current source and the power source voltage Vss drain of PMOSQP ₂ provided between. Further, the positive input terminal of the operational amplifier OP is, the gate is shorted to the drain, and is connected to the drain of NMOSQN ₂ provided between the constant current source and the power source voltage Vss.

[0014] Then, source and a drain of the NMOSQN ₂ are connected in series, and receives the output of the operational amplifier OP to the gate, the source is connected to power supply voltage Vss, NMOSQN ₁ is provided for output . Therefore,
The output voltage of the the operational amplifier OP, namely, the output voltage Vreg of the constant voltage generating circuit, said PMOSQP ₂ and NMO
Receiving respective threshold voltages of the SQN ₂ Vthp2, Vthn2 effects, respectively.

[0015] That is, to describe the operation of this circuit in the following, the PMOSQP by the constant current flows to _2, the PMOSQP ₂ threshold voltage to the signal line 100 | Vth
A voltage α | Vthp2 | (α: constant) depending on p2 | is generated. The signal line 101 is connected to the same potential α as the signal line 100 by the operational amplifier OP and the NMOS QN _1.
| Vthp2 |. Moreover, by flowing current from the constant current source NMOSQN _2, the signal line 101
And an output line 102, a potential difference of αVthn2 depending on the threshold voltage Vthn2 occurs. Therefore, between the output line 102 and the ground potential Vdd, | Vthp2 | + Vthn2
A constant voltage α (| Vthp2 | + Vthn2) depending on the voltage is generated.

Therefore, the output voltage of the operational amplifier OP, that is, the output voltage Vreg of the constant voltage generation circuit is
Receiving SQP ₂ threshold voltage Vthp2 and NMOSQN ₂ of the influence of the threshold voltages Vthn2, respectively. That is, constant voltage | V
reg | is proportional to | Vthp2 | + Vthn2. Therefore, the crystal oscillation circuit having the conventional configuration operates using the constant voltage value Vreg depending on | Vthp2 | + Vthn2 as a power supply.

Therefore, in the conventional constant voltage generating circuit, the threshold voltages Vthp2 and Vt
Even when the value of hn2 varies and the value of | Vthp2 | or Vthn2 increases, the constant voltage | Vreg | also increases at the same time, so that | Vreg |> | Vsto in the relationship between the constant voltage Vreg and the oscillation stop voltage Vsto. Is maintained, the oscillation operation can be ensured, and the yield of IC can be improved.

In order to reduce the power consumption of the oscillation circuit, the number of constant current sources for operating the constant voltage generating circuit has been reduced as much as possible within a range where the constant voltage generating circuit can operate. However, with the need for the development of portable devices as described above, in order to reduce the power consumption of the oscillation inverter, the oscillation operation must be ensured (| Vreg |> | Vst
o |), it is necessary to lower the constant voltage | Vreg | as much as possible. However, when the constant current from the constant current source that operates the constant voltage generating circuit is reduced, the constant voltage Vre when the constant current fluctuates due to a temperature change.
The change in g increases.

Here, the temperature characteristics of the transistor will be described using a constant voltage generating circuit shown in FIG. In this constant voltage generation circuit, the NMOS QN ₂ , PM
The current values of the constant current sources TA and TB for operating the OSQP ₂ have temperature dependence. That is, the constant current sources TA, TB
, For example, when a depletion-type PMOS is used, the constant current ID can be expressed by Equation 2. Here, the current amplification factor of the depletion PMOS constituting the constant current source is β, the absolute value of the threshold voltage is | Vth |, and the gate-source voltage is _VGS .

Equation 2: I _D = 1/2 · β · (V _GS − | Vth |) ² Here, the depletion PMOS is short-circuited between the gate and the source to form a constant current. Since VGS is 0 V, substituting this results in Equation 3.

Equation 3: I _D = 1/2 · β · (−Vth) ^{2 As} shown in Equation 3, the constant current I _D does not depend on the power supply voltage. Therefore, since the constant current _ID is proportional to the square of the temperature-dependent current amplification factor β and the threshold voltage Vth,
The value of the constant current _ID also varies with a change in temperature.

Further, it is shown on the graph representing the temperature variation of NMOSQN ₂ in FIG. In FIG. 12, the vertical axis represents the constant current _ID , and the horizontal axis represents the gate-source voltage V _GS.
Represents The graph shows three types of curves,
If the curve A threshold voltage of the NMOSQN ₂ is low, when the curve C the threshold voltage is high, the curve B shows the case wherein the threshold voltage is an intermediate between A and C. Although not shown, the PMOS QP ₂ also has similar characteristics. That is, as can be seen from this graph, the amount of variation with respect to the temperature change of the constant voltage Vreg is a variation of the constant current value, the threshold voltage of NMOSQN ₂ Vthn2, PMOSQP
₂ is the sum of the respective changes in the absolute value of the threshold voltage Vthp2.

On the other hand, as for the variation of the oscillation stop voltage Vsto with respect to the temperature, since the oscillation stop voltage Vsto depends on the equation 1, only the variation of the threshold voltage of the NMOS QN ₀ and the PMOS QP ₀ is obtained.

Therefore, the temperature coefficient of the constant voltage Vreg is:
Change amount of constant current source and threshold voltage (| Vthp2 | + Vthn2)
However, the temperature coefficient of the oscillation stop voltage Vsto is the change amount of the threshold voltage (| Vthp0 | + Vthn0), so that the temperature coefficient, that is, the temperature characteristic is different.

That is, the constant voltage Vreg and the oscillation stop voltage Vs
When the temperature characteristics of “to” are different, for example, when the constant voltage | Vreg | has a larger negative slope with respect to the temperature in absolute value, the temperature and voltage related to the constant voltage | Vreg | and the oscillation stop voltage | Vsto | Is shown in FIG. FIG. 13 shows a graph of the constant voltage Vreg and the oscillation stop voltage Vsto, with the horizontal axis representing temperature and the vertical axis representing voltage. To ensure the oscillation operation, at a high temperature in the operation guarantee temperature range,
That is, at the point B shown in FIG.
sto | must be secured. Here, the temperature at the point B is, for example, a heat resistance temperature of a generally known wristwatch.

Therefore, in other low temperature regions, the constant voltage |
The Vreg | value must be increased more than necessary. That is, in the conventional constant voltage generation circuit and the conventional crystal oscillation circuit, useless power is consumed. Therefore, it can be seen that it is effective to make the temperature characteristics of the constant voltage Vreg and the oscillation stop voltage Vsto the same in order to reduce the power consumption. That is, conventionally, the difference in the temperature gradient between the constant voltage Vreg and the oscillation stop voltage Vsto becomes large, and in order to guarantee the oscillation operation on the high temperature side (or the low temperature side), the | Vreg
|> Vsto | must always be satisfied, and | Vreg | must be higher on the low-temperature side (or high-temperature side) than is required to guarantee the oscillation operation. As a result, wasteful power is consumed. Was.

However, the oscillation stop voltage Vsto is equal to the PM constituting the oscillation inverter INV0 in the crystal oscillation circuit.
It depends on the threshold voltage Vthp0 and NMOSQN threshold voltage Vthn0 ₀ of OSQP _0, in the conventional oscillating inverter as described above, the low consumption by adjusting only the constant voltage Vreg that is formed in the constant voltage generating circuit The only thing that could be done was to use electricity.

That is, if the threshold voltage is changed in the formation of the transistor constituting the oscillation inverter, the characteristics of the oscillation inverter also change. It became necessary and made the design difficult. Therefore, | Vr between the constant voltage Vreg and the oscillation stop voltage Vsto
It is difficult to keep the constant voltage | Vreg | as low as possible while maintaining the relationship of eg |> | Vsto |, and it was not possible to further reduce the power consumption of the oscillation circuit.

[0029]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide an oscillation circuit including an oscillation inverter, a constant voltage generation circuit, a semiconductor device, and a portable device. It is an object of the present invention to perform low-power-consumption driving and stable oscillation by adjusting the threshold voltage of a transistor in an oscillating inverter that constitutes an oscillating circuit in electronic devices and watches.

Another object of the present invention is to perform low power consumption driving by controlling a threshold voltage of a transistor connected to an input section of an operational amplifier in a constant voltage generating circuit.

[0031]

An oscillation circuit according to a first aspect of the present invention includes a plurality of oscillation inverters configured using transistors having different threshold voltages, and any one of the oscillation inverters is selectively used. An oscillating inverter group, and a crystal oscillator connected to the output side and the input side of the oscillating inverter group, inverting the phase of the output signal of the oscillating inverter group, and providing a feedback input to the oscillating inverter group. And a feedback circuit that performs the operation.

Therefore, according to the oscillation circuit of the first aspect, the transistor output of the oscillation inverter in the oscillation inverter group can be adjusted to an optimum voltage, and the oscillation output as the crystal oscillation circuit can be adjusted. An optimum state can be achieved, and power consumption can be reduced.

The oscillation circuit according to a second aspect of the present invention is characterized in that, in addition to the features of the first aspect, a selection circuit for selecting any one of the oscillation inverters from the oscillation inverter group is provided.

Therefore, according to the oscillation circuit of the second aspect, the oscillation inverter having the optimum threshold voltage can be selected by the selection circuit.

According to a third aspect of the present invention, in addition to the characteristic feature of the second aspect, the oscillation circuit is formed on the same substrate as the test circuit, and is not mounted with the crystal resonator. Selecting one of the oscillation inverters from the oscillation inverter group by selecting each of the oscillation inverters in the test circuit and measuring a short-circuit current of each of the oscillation inverters; The oscillation inverter is selected by a circuit.

Therefore, according to the oscillation circuit of the third aspect, since the short-circuit current of each oscillation inverter of the oscillation inverter group formed on the IC chip or the wafer can be measured, regardless of the manufacturing conditions. In addition, an optimum oscillation inverter can be obtained, the yield can be improved, and oscillation characteristics with stable and low power consumption can be obtained. Further, the selection circuit may be formed on the same substrate as the test circuit.

According to a fourth aspect of the present invention, in the oscillation circuit according to the third aspect, the test circuit is connected to a test pad and a voltage applied to the test pad is controlled. Each of the oscillation inverters is selected via the test circuit.

According to the oscillation circuit of the fourth aspect, a signal for selecting each of the oscillation inverters can be formed by the test circuit by a combination of voltages applied to the test pads. Of the oscillation inverter can be measured.

According to a fifth aspect of the present invention, in addition to the features of the first to fourth aspects, the selection circuit further comprises:
A plurality of unit circuits are provided corresponding to the oscillation inverter and connected to a plurality of pads, each of the plurality of unit circuits being one of a fuse, a nonvolatile memory, and a storage element. And selecting the oscillation inverter by applying a voltage to the pad.

Therefore, according to the oscillation circuit of the fifth aspect, by adding a means including any one of a fuse, a nonvolatile memory, and a storage element, selection of the oscillation inverter can be easily performed. A circuit can be configured.

According to a sixth aspect of the present invention, in the oscillation circuit according to the first aspect, the oscillation inverter group includes a transistor having a first threshold voltage. A first oscillation inverter, a second oscillation inverter including a transistor having a second threshold voltage different from the first threshold voltage, and different from the first and second threshold voltages. And a third oscillation inverter including a transistor having a third threshold voltage.

Therefore, according to the oscillation circuit of the sixth aspect, the source-drain current flowing through the oscillation inverter among the three oscillation inverters including the transistor having a small difference in threshold voltage in the oscillation inverter group. Can be adjusted to an optimum current, an oscillation output as a crystal oscillation circuit can be set to an optimum state, and low power consumption can be achieved.

According to a seventh aspect of the present invention, in addition to the characteristic feature of the first or sixth aspect, the power supply line of each of the oscillation inverters is connected to a first potential side and the first potential. And the oscillation circuit is connected to a second potential side
The amplitude is obtained by a potential difference between the first potential and the second potential.

Therefore, according to the oscillation circuit of the present invention, since the amplitude of the oscillation inverter can be set between the first power supply and the constant voltage, the oscillation based on the voltage amplitude can be stabilized. In addition, oscillation characteristics with low power consumption can be obtained.

According to an eighth aspect of the present invention, in addition to the characteristic feature of the seventh aspect, the potential difference between the first potential and the second potential is larger than an absolute value of an oscillation stop voltage of the oscillation inverter. Is also large.

Therefore, according to the oscillation circuit of the eighth aspect, a stable oscillation operation can be ensured by the oscillation inverter.

According to the ninth aspect of the present invention, in addition to the features of the seventh or eighth aspect, the short-circuit current flowing through the selected oscillation inverter is higher than the on-state current of the transistor constituting the selected oscillation inverter. The oscillation inverter is selected within a range that satisfies the condition of being large, and a potential difference between the first potential and the second potential is set to a minimum voltage.

According to the oscillating circuit of the ninth aspect, the oscillating inverter can perform a stable and low power consumption oscillating operation, and can cope with a low power supply voltage.

According to a tenth aspect of the present invention, in the constant voltage generating circuit, one end is connected to the first potential side and the other end is connected to the constant voltage output side,
A constant voltage control circuit including a plurality of transistors each having a different threshold voltage, wherein one of the transistors is selectively used; and a reference voltage of the constant voltage control circuit is input to one terminal and given to the other terminal. And one end connected to the other end of each of the transistors of the constant voltage control circuit, the other end connected to the second potential side, and receiving an output of the operational amplifier to receive a gate input. And a transistor whose voltage is controlled.

Therefore, according to the constant voltage generating circuit of the tenth aspect, the value of the constant voltage at the time of selecting each transistor of the transistor group formed on the IC chip can be measured at the monitor terminal. An optimum constant voltage can be obtained irrespective of manufacturing conditions, and a constant voltage with low power consumption can be obtained with almost the same chip area.

According to the eleventh aspect of the present invention, in addition to the characteristic feature of the tenth aspect, the constant voltage generating circuit comprises:
One of a plurality of transistors in the constant voltage control circuit
A selection circuit for selecting one of the transistors.

Therefore, according to the constant voltage generating circuit of the present invention, the optimum transistor can be selected by the selecting circuit.

According to a twelfth aspect of the present invention, in addition to the characteristic feature of the eleventh aspect, the constant voltage generating circuit is connected to a monitor terminal and provided on the same substrate as the test circuit. In the inspection step, the test circuit selects each transistor in the constant voltage control circuit, and measures the output voltage of each transistor in the constant voltage control circuit at the monitor terminal, whereby the test circuit controls the constant voltage control circuit. One transistor is specified from a plurality of transistors, and the transistor is selected by the selection circuit.

Therefore, according to the constant voltage generating circuit of the twelfth aspect, the value of the constant voltage at the time of selecting each of the transistors in the transistor group formed on the IC chip can be measured at the monitor terminal. An optimum constant voltage can be obtained irrespective of manufacturing conditions, and a constant voltage with low power consumption can be obtained with almost the same chip area.

According to a thirteenth aspect of the present invention, in addition to the characteristic feature of the twelfth aspect, the test circuit is connected to a test pad, and a voltage applied to the test pad is controlled. Select each transistor in the constant voltage control circuit via the test circuit.

Therefore, according to the constant voltage generating circuit of the present invention, a signal for selecting each transistor of the constant voltage control circuit is formed by the test circuit by a combination of voltages applied to the test pads. And the reference voltage formed by each of the transistors can be measured.

According to a fourteenth aspect of the present invention, in addition to the characteristic feature of the tenth aspect, the selection circuit corresponds to the plurality of transistors in the constant voltage control circuit. A plurality of unit circuits formed and connected to a plurality of pads, each of the plurality of unit circuits including any one of a fuse, a nonvolatile memory, and a storage element, and applying a voltage to the pad. Is applied to select the transistor.

Therefore, according to the constant voltage generating circuit of the present invention, the oscillation inverter can be easily selected by adding means including any one of a fuse, a nonvolatile memory, and a storage element. A selection circuit can be configured.

According to a fifteenth aspect of the present invention, in addition to the feature of any of the tenth to fourteenth aspects, the constant voltage control circuit includes a transistor having a fourth threshold voltage; And a transistor having a sixth threshold voltage different from the fourth and fifth threshold voltages, and one end of each of the transistors has a first threshold voltage different from the fourth and fifth threshold voltages. It is characterized in that it is connected to the potential side and the other end is connected to the constant voltage output side.

Therefore, according to the constant voltage generating circuit of the present invention, the constant voltage values of three types of transistors having different threshold voltages in the test circuit formed on the IC chip can be measured at the monitor terminal. Therefore, an optimal transistor can be selected, an optimal constant voltage can be obtained regardless of manufacturing conditions, and a constant voltage with low power consumption can be obtained with almost the same chip area.

According to a sixteenth aspect of the present invention, in addition to the features of any of the tenth to fifteenth aspects, the constant voltage generation circuit supplies an output voltage of the constant voltage generation circuit to an oscillation circuit. And

According to the constant voltage generating circuit of the present invention, the constant voltage can be adjusted in accordance with the oscillation characteristics of the oscillation circuit, so that the optimum constant voltage can be supplied to the oscillation circuit. Can be.

A semiconductor device according to a seventeenth aspect is a semiconductor device including an oscillation circuit, a constant voltage generation circuit, and a test circuit, wherein the oscillation circuit is configured using transistors having different threshold voltages. An oscillation inverter group including a plurality of oscillation inverters and any one of the oscillation inverters is selectively used, and a first selection for selecting one oscillation inverter from the plurality of oscillation inverters in the oscillation inverter group A circuit, a feedback circuit for inverting the phase of the output signal of the oscillation inverter group, the output side and the input side of which are connected to an externally mounted crystal unit, and for feedback input to the oscillation inverter group;
The constant voltage generation circuit includes a plurality of transistors having one end connected to the first potential side and the other end connected to the constant voltage output side, and a plurality of transistors having different threshold voltages, respectively, and one of the transistors is selectively used. A constant voltage control circuit, an operational amplifier in which a reference voltage of the constant voltage control circuit is input to one terminal and a given reference voltage is input to the other terminal, and one end of each of the transistors of the constant voltage control circuit One transistor is connected to the other end, the other end is connected to the second potential side, and one transistor is selected from a plurality of transistors in the constant voltage control circuit and a transistor whose gate input voltage is controlled by receiving the output of the operational amplifier. A second selection circuit, the test circuit being connected to the oscillation circuit and the constant voltage generation circuit, respectively, and being connected to the output voltage of the constant voltage generation circuit. A monitor terminal for monitoring, provided to be connected to the test pad, in the inspection process,
By controlling the voltage applied to the test pad while applying a voltage to the monitor terminal, selecting each of the oscillation inverters via the test circuit,
Measure the short-circuit current of each of the oscillation inverters,
After measuring the short-circuit current, by controlling the voltage applied to the test pad, each transistor in the constant voltage control circuit is selected via the test circuit, and the output voltage of each transistor is monitored by the monitor terminal. , The oscillation inverter in the oscillation circuit is selected by the first selection circuit within a range in which the oscillation operation of the oscillation inverter can be ensured, and the constant voltage in the constant voltage generation circuit is selected. A transistor in the control circuit is selected by the second selection circuit.

Therefore, according to the semiconductor device of the present invention, the optimum short-circuit current and constant voltage can be selected from the combination of the measurement result of the short-circuit current of the oscillation inverter of the crystal oscillation circuit and the measurement result of the constant voltage. A combination can be selected, a stable oscillation output of the oscillation circuit in the semiconductor device can be obtained, the yield can be improved, and power consumption can be further reduced.

A portable electronic device according to claim 18 includes the oscillation circuit according to any one of claims 1 to 9, wherein an operation reference signal is formed from an oscillation output of the oscillation circuit.

Therefore, according to the portable electronic device of the eighteenth aspect, it is possible to reduce the power consumption of the electronic circuit while securing the operation margin of the oscillating inverter regardless of the manufacturing variation of the portable electronic device. In a portable electronic device, not only can the oscillation operation be stably performed, but also the service life of the battery can be extended, and the usability of the portable electronic device can be improved.

A portable electronic device according to a nineteenth aspect of the present invention includes, in addition to the features of the eighteenth aspect, a constant voltage generation circuit according to any one of the tenth to sixteenth aspects for forming a supply voltage to the oscillation circuit. It is characterized by the following.

Therefore, according to the portable electronic device of the nineteenth aspect, since the minimum constant voltage can be further supplied to the oscillation circuit, the power consumption of the electronic circuit can be reduced.

According to a twentieth aspect of the present invention, in addition to the features of the nineteenth aspect, the timepiece includes the oscillation circuit of any one of the first to ninth aspects, wherein a clock reference signal is formed from an oscillation output of the oscillation circuit. It is characterized by.

Therefore, according to the timepiece of the twentieth aspect, the timepiece can not only stably perform the oscillating operation while securing the operation margin of the oscillating inverter irrespective of manufacturing variations of the timepiece, The service life of the battery can be extended, and the usability of the watch can be improved.

A timepiece according to a twenty-first aspect is characterized in that, in addition to the features described in the twentieth aspect, the timepiece further includes a constant voltage generation circuit according to any of the tenth to sixteenth aspects, which forms a supply voltage to the oscillation circuit. And

Therefore, according to the timepiece according to the twenty-first aspect, a minimum constant voltage can be further supplied to the oscillation circuit, so that the power consumption of the timepiece circuit can be reduced.

[0073]

Next, preferred embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 2 shows a constant voltage generation circuit and a crystal oscillation circuit according to a preferred first embodiment of the present invention. The crystal oscillation circuit of the present embodiment
This is a crystal oscillation circuit used for a quartz wristwatch. The members corresponding to the circuits shown in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted.

In the crystal oscillation circuit of this embodiment, an oscillation inverter group is formed by a plurality of oscillation inverter units, and P
The threshold voltages of the MOS / NMOS are formed differently for each oscillation inverter unit, so that an optimum oscillation inverter unit can be selected.

The crystal oscillation circuit shown in FIG. 2 will be described. The crystal oscillation circuit of the present embodiment includes an oscillation inverter group 10, selection control circuits 20P and 20N, a crystal oscillator X'tal, and a high resistance Rf forming a feedback circuit. Here, the MOS is formed on an IC chip formed on a semiconductor substrate, and the other elements are mounted on a printed circuit board by being connected to the IC chip. The feedback circuit includes, in addition to the resistor Rf, capacitors C _D and C _G for phase compensation, and uses the drain output of the group of oscillation inverters 10 as a gate input whose phase is inverted by 180 degrees to form the group of oscillation inverters 10. Of the first-stage oscillation inverter unit INV1.

In the oscillation inverter group 10,
Second oscillating inverter unit INV2 comprising first oscillation inverter unit INV1, PMOSQP ₅ and NMOSQN ₅ comprising PMOSQP ₄ and NMOSQN _4, PMOSQP
Third oscillation inverter unit INV3 is formed comprising ₆ and NMOSQN _6.

Then, each oscillation inverter unit INV
1 to 3 are connected to a first potential side and a second potential side of a voltage lower than the first potential side, respectively, and are configured to be supplied with power and driven by a potential difference between both potentials. here,
In the crystal oscillation circuit of the present embodiment, the first potential is set to the ground voltage Vdd, and the second potential is set to the negative constant voltage Vreg supplied from the constant voltage generation circuit.

Each of the transistors in the oscillation inverter units INV1 to 3 constituting the oscillation inverter group 10 is formed with a different threshold voltage for each of the oscillation inverter units. For example, the threshold voltages of the NMOSs QN ₄ , QN ₅ , and QN ₆ are set to Vthn4>Vthn5> Vthn6.
According to the magnitude of the threshold voltage of the OS, the PMOS QP ₄ , Q
The threshold voltages of P ₅ and QP ₆ are | Vthp4 |> | Vthp5 |> | Vthp
6 |. As for the control of the threshold voltage, the implanted impurity concentration at the time of forming the transistor is controlled so that the threshold voltage differs for each oscillation inverter unit. For example, as a difference between these threshold voltages, the potential difference between Vthn4 and Vthn5, Vthn5 and Vthn6, Vthp4 and Vthp5, and Vthp5 and Vthp6 is about 0.1V.
Degree.

[0080] Then, each of the oscillation inverter unit INV1~3 is, the other end of the capacitor C _G of the ground voltage Vdd is applied to one end, the input gate of each are commonly electrically connected. Moreover, each oscillation inverter unit INV1~3, together with the respective output nodes are commonly connected, one end of the other end of the capacitor C _D to the ground voltage Vdd is applied to one end, and crystal oscillator X'tal Connected. The other end of the crystal unit X′tal is
The other end of the capacitor C _G, the gate input of each oscillating inverter unit INV1～3, feedback resistor Rf
Is connected to one end. Further, the other end of the feedback resistor Rf is connected to each of the oscillation inverter units INV1 to INV1.
3 and the outputs of the oscillation inverter units INV1 to 3 are fed back to the respective gates.

Further, each of the oscillation inverter units I
The NV1 to NV3 are provided to be connected between the NMOS selection control circuit 20N and the PMOS selection control circuit 20P to which the selection signal is input. The NMOS selection control circuit 20N
Together are constituted by NMOSQN ₇ ~QN ₉ for receiving a selection signal to the gate, the PMOS selection control circuit 20P
Are CMOS inverter circuits IP ₁ -IP ₃ receiving selection signals at their gates, and PMO receiving the output at each gate.
It is constituted by SQP ₇ ~QP _9. That is, the PM
The gates of PMOSQP ₇ ~QP ₉ constituting the OS selection control circuit 20P in which the inverted signal of the respective selection signal is input.

Then, the PMOS selection control circuit 20
The connection between P, the NMOS selection control circuit 20N, and the oscillation inverter group 10 will be described below, for example, using the oscillation inverter unit INV1 as an example. The oscillation inverter units INV2 and INV3 have exactly the same configuration.

The source of the PMOS QP ₇ included in the PMOS selection control circuit 20 P is applied with the power supply voltage Vss, and the drain is connected to the source of the PMOS QP ₄ . Then, NMOSQN ₇ contained in the NMOS selection control circuit 20N, along with constant voltage Vreg is applied to the source, the drain is connected to the source of NMOSQN _4. Then, the gate of the selection control NMOSQN _7, the selection signal SEL1 for commanding the selection / non-selection of the oscillation inverter unit INV1 at the oscillation inverter group 10 is input to the gate of the selection control PMOSQP ₇ is An inverted signal of the selection signal SEL1 is applied. That is, when the selection signal SEL1 is at a high level, the oscillation inverter unit INV1 can be in a selected state, and when the selection signal SEL1 is at a low level, the oscillation inverter unit INV1 can be in a non-selected state.

As described above, the oscillation inverter unit INV1
However, as described above, the configurations of the oscillation inverter units INV2 and INV3 are the same, and
In the oscillating inverter unit INV2, the selection control PMOS QP having the selection signal SEL2 input to the gate.
₈ and a selection control NMOS QN ₈ whose gate receives an inverted signal of the selection signal SEL2. Similarly, the inverter INV3 includes a selection control NMOSQN ₉ selection signal SEL3 is input to the gate, the selection control PMOSQP ₉ which inverted signal is input to the selection signal SEL1 to the gate is provided in the same manner .

As described above, the oscillation inverter group 10 constituted by the oscillation inverter units INV1 to 3 having different threshold voltages and the selection control circuits 20P, 20P, 2
0N is provided in the oscillation inverter group 10 for adjusting the transistor output of the oscillation inverter unit to an optimal voltage in order to optimize the oscillation output as the crystal oscillation circuit. is there.

That is, the input of the selection signals SEL1 to SEL3 to the selection control circuits 20P and 20N controls the activation of the oscillation inverter units INV1 to INV1 to 3 and provides an oscillation having a transistor formed with an optimum threshold voltage. To select the inverter unit. The method and circuit for switching the voltage levels of the selection signals SEL1 to SEL3 will be described later in detail with reference to FIG.

Next, a method of selecting an oscillation inverter unit in the crystal oscillation circuit of the present embodiment will be described. In the present embodiment, for example, a case where the oscillation inverter unit INV1 is selected will be described.

[0088] selection signal SEL1 is set to the high level, the low level to the gate of the selection control PMOSQP _7, NMOSQ
Since the voltage at the gate to the high level N ₇ is applied, the PMOSQP ₇ and NMOSQN ₇ is turned on. Therefore, in the oscillation inverter unit INV1, the PMOS QP
₄ is electrically connected to the ground voltage Vdd, and the source of the NMOS QN ₄ is electrically connected to the constant voltage Vreg.
The oscillation inverter unit INV1 can be selected.

[0089] On the other hand, since the selection signal SEL1, SEL2 are low, since the inverted signal of the respective selection signal SEL1, SEL2 to the gate of the selection control PMOSQP _8, QP _9, i.e. the high-level signal is applied, PM
OSQP ₈ and QP ₉ are turned off. And NMOS for selection control
The selection signal SEL1 to the gate of QN _8, QN _9, SEL2
That is, since a low level signal is applied, the NMOS
QN ₈ and QN ₉ are turned off. Therefore, the oscillation inverter units INV3 and INV4 are electrically disconnected from the two power supplies and are not selected.

Next, a method of forming the selection signals SEL1 to SEL3 will be described with reference to FIG.

FIG. 3 shows an oscillation inverter unit selection circuit according to the first preferred embodiment of the present invention.
The oscillation inverter unit selection circuit of the present embodiment
In the crystal oscillation circuit, an oscillation inverter group 10 constituted by the oscillation inverter units INV1 to 3
Among these are circuits for forming selection signals SEL1 to SEL3 for selecting an optimum oscillation inverter unit.

The oscillation inverter unit selection circuit is composed of unit circuits corresponding to the number of the oscillation inverter units. For example, a circuit for a crystal oscillation circuit having three types of oscillation inverter units INV1 to 3 shown in FIG. Is provided with three unit circuits U1 to U3. That is, the oscillation inverter unit selection circuit has three
Types of pads P1 to P3 and three types of fuse circuits F1
To F3. Each of the fuse circuits F1 to F3 has one end connected to the ground voltage Vdd and the other end connected to a pad P1 to Pd.
The fuses f1 to f3 connected to P3, one end is connected to the power supply voltage Vss, and the other end is connected to the pad and the fuse f1.
, F3, and resistors R1 to R3 connected in series with the other ends of the output inverters and output inverters I1 to I3.

When the unit circuit U1 is a circuit for forming the selection signal SEL1, for example, the output of the unit circuit U1 is the N of the oscillation inverter unit INV1.
The gate of MOSQN ₇ or via the inverter in the selection control circuit 20P of the crystal oscillator in the circuit, is input to the gate of PMOSQP _7.

In the oscillation inverter unit selection circuit of the present embodiment, fuses f1 to f3 of fuse circuits F1 to F3 can be cut by applying a high voltage of about 20 V, for example. For example, when selecting the oscillation inverter unit INV1, first, a high voltage is applied to the pad P1 and the fuse f1 is cut, so that a current flows from the pad P1 to the power supply Vss via the resistor R1. To As a result, the voltage input to the output inverter INVU1 goes low, and the output voltage of the output inverter INVU1, that is, the output signal of the unit circuit U1 in the oscillation inverter unit selection circuit goes high. Therefore, the selection signal SEL1 is selected for control NMOSQN ₇ is turned on to the high level as shown in FIG. 3, the selection control P
MOSQP ₇ turns off.

As described above, the oscillation inverter unit INV1
Has been described, but INV2, INV
Selection of 3 can be performed in a similar manner. For example, when selecting the oscillation inverter unit INV2, a high voltage is applied to the pad P2 and the fuse f of the unit circuit U2 is applied.
2 to select the oscillation inverter unit INV3, apply a high voltage to the pad P3 and cut the fuse f3 of the unit circuit U3 to select a desired oscillation inverter unit in the same manner. Can be. Here, in the present embodiment, a method of storing information by cutting a fuse has been described as an example. However, the present invention is not limited to this, and information can be stored using a nonvolatile memory, a storage element, or the like.

FIG. 4 is a timing chart showing the relationship between the oscillation stop voltage Vsto and the selection signals SEL1 to SEL3. In FIG. 4, the horizontal axis represents time. Here, between the oscillation stop voltage Vsto and the ground voltage Vdd, as the difference voltage increases, the oscillation stop voltage | Vsto | increases.

First, by setting the selection signal SEL1 to a high level, the oscillation stop voltage | Vs
to | is K (| Vthp7 | + Vthn7) (K: constant). When the selection signal SEL1 is at a low level and the selection signal SEL2 is at a high level, the oscillation stop voltage | Vsto | becomes K (| Vthp8 | + Vthn8). When the selection signal SEL2 is at a low level and the selection signal SEL3 is at a high level, the oscillation stop voltage | Vsto | becomes K (| Vthp9 | + Vthn9).
That is, the oscillation stop voltage | Vsto | when SEL1 is set to the high level is the lowest, and the oscillation stop voltage | Vsto | is highest when the SEL3 is set to the high level.

[0098] Incidentally, the cutting of the fuse in the oscillating inverter unit selection circuit is performed during IC testing, in this case, first, the selection control circuit 20N connected to the oscillation inverter group 10 NMOSQN ₇ ~QN ₉ By measuring the value of the negative constant voltage Vreg, which is the output voltage of the constant voltage generating circuit, to which the respective sources are commonly connected, and the short current Is flowing through each of the oscillation inverter units INV1 to INV1-3, A selection is made.

FIG. 5A shows a method of measuring the short-circuit current Is flowing through the oscillation inverter unit.
(B) is a graph showing the relationship between the oscillation stop voltage | Vsto | and the short current Is, with the vertical axis representing the oscillation stop voltage | Vsto | and the horizontal axis representing the short current Is.

[0100] Measurement of short-circuit current of the oscillation inverter unit, as shown, by applying a ground voltage Vdd to the source of PMOSQP _S constituting the oscillation inverter unit applies the constant voltage Vreg to the source of NMOSQN _S , The common gate and the common drain of the PMOS QPs and the NMOS QNs are short-circuited, and the current flowing between the ground voltage Vdd and the constant voltage Vreg is measured.

At this time, in the graph of the relationship between the oscillation stop voltage | Vsto | and the short-circuit current Is of the oscillation inverter unit, in order to reduce the power consumption of the crystal oscillation circuit, the aforementioned constant voltage Vreg and oscillation stop voltage Vsto Is | Vreg |> |
Vsto | and | Vreg | must be kept as low as possible.

[0102] That is, for the short current Is, the PMOSQP _S ON voltage or more, i.e. the threshold voltage |
It is necessary to select the oscillation inverter unit and the constant voltage Vreg so as to be equal to or higher than VthpS | and the lowest constant voltage | Vreg |. Further, the oscillation-stopped voltage | Vsto | in the oscillation voltage required is less ON voltage of NMOSQN _S, i.e. it is necessary to select the following voltage threshold voltage VthnS. Therefore, in order to reduce the power consumption, the short-circuit current Is and the oscillation stop voltage | Vsto | must be within the range of the region 1 shown in the figure. On the other hand, in order to select an oscillation inverter unit that satisfies this condition and can cope with the recent low voltage of the power supply, the oscillation inverter with the lowest short-circuit current that oscillates stably within a range where the on / off operation of the transistor is compensated It is necessary to select a unit. That is, by selecting the optimum oscillation inverter unit that satisfies this condition according to the result of the short-circuit current measurement described above, the power consumption of the crystal oscillation circuit can be reduced.

For this purpose, in the IC inspection process, a quartz oscillator X′tal is used by using a test circuit (not shown) and a test pad connected to the test circuit.
Before mounting on the board, each oscillation inverter unit IN
The short-circuit current Is is measured at V1 to V3, and the short-circuit current having the lowest short-circuit current within the range where the on-off operation is compensated is specified. At this time, the IC test is performed in a wafer state, and a short circuit current is measured for each IC chip using a test circuit and a test pad provided in each IC chip. At this time, the oscillation inverter group 10 and the selection control circuit 20
The test is performed with only P and 20N active and the other elements inactive.

Incidentally, one or more test pads are provided according to the number of oscillation inverter units and the logic of the test circuit, and the test circuit has a voltage level of an input signal to the test pad. Is formed by a combination including a logic circuit for setting any one of the selection signals SEL1 to SEL3 to a high level. The measurement of the short-circuit current is performed in the test circuit in a state where the high-level selection signal is input to each of the oscillation inverter units in a simulated manner. At this time, a ground voltage Vdd and a constant voltage Vreg are applied to the oscillation inverter group by applying a negative voltage Vreg equivalent to a constant voltage using the monitoring pad MP connected to the output line 102.
Is applied.

After measuring the short-circuit current Is, the optimum oscillating inverter unit of the oscillating inverter group 10 is specified, and the unit of the oscillating inverter unit selecting circuit provided corresponding to the oscillating inverter unit is provided. The fuse in the circuit is cut, and one optimal oscillation inverter unit is selected.

As described above, the crystal oscillation circuit according to the present embodiment uses the short-circuit current I of the oscillation inverter unit.
Since s can be tested at the time of IC inspection, an optimum oscillation inverter can be obtained irrespective of manufacturing conditions, yield can be improved, and stable and low power consumption oscillation characteristics can be obtained.

Here, FIG. 6 shows a graph of the oscillating operation of the oscillating inverter of the present embodiment thus obtained, and the oscillating operation will be described. In FIG. 6, the horizontal axis represents time, and the drain waveform and the gate waveform have a common time axis. In the crystal oscillation circuit in which the optimal oscillation inverter unit has been selected, the amplitude of the gate input waveform is amplified according to the optimal driving capability of the oscillation inverter unit. Then, the phase of the drain output waveform is inverted by 180 degrees with respect to the gate input waveform. The drain capacitance C _D cuts the harmonic components, and enable only the oscillation frequency component, which acts as a filter to prevent harmonic oscillation of the crystal oscillation circuit. The feedback circuit including the resistor Rf, the drain capacitance C _D , the crystal unit X′tal, and the gate capacitance C _G converts the phase of the drain waveform by 180 degrees.

As described above, the output characteristics of the oscillation inverter in the crystal oscillation circuit of the present embodiment are excellent in output characteristics and oscillation with low power consumption because the oscillation operation is performed by the optimum oscillation inverter unit. A circuit can be realized.

Although the crystal oscillation circuit of the present embodiment has been described above, in the present embodiment, three types of oscillation inverter units having different threshold voltages have been described. Can be freely set without any particular limitation. Similarly, the number of oscillation inverter unit selection circuits can be provided corresponding to the number of oscillation inverter units.

In the present embodiment, the threshold voltage is set by the oscillation inverters INV1>INV2> INV3, that is, Vthn4>Vthn5> Vthn6, | Vthp4 |> | Vt
hp5 |> | Vthp6 |, but without being limited to this, the setting of the threshold voltage is set to INV1 <INV2 <IN
V3, that is, Vthn4 <Vthn5 <Vthn6, | Vthp
4 | <| Vthp5 | <| Vthp6 |.

<Second Embodiment> Next, a constant voltage generating circuit according to the present embodiment will be described with reference to FIG.

In the constant voltage generating circuit of the present embodiment, a plurality of NMOSs for controlling one input voltage of the operational amplifier are formed with different threshold voltages, respectively, and an optimum NMOS is selected from the plurality of NMOSs. It is made possible.

The constant voltage generation circuit according to the present embodiment includes an operational amplifier OP, a selection control circuit 30, and an output gate NMOS.
And QN _1, a constant voltage control circuit 40, - is configured to include an input PMOSQP _2.

The operational amplifier OP has a + input terminal and a − input terminal, and the + input terminal receives a voltage formed by the constant voltage control circuit 40. The-input terminal is P
Is constituted by a MOS, it receives a voltage which is controlled by the selection control PMOSQP ₂ provided between the ground voltage Vdd and the constant current source. The operational amplifier OP amplifies and outputs a potential difference between the voltage applied to the + input terminal and the voltage applied to the − input terminal. Furthermore, the - input PMOSQP ₂ is the source ground voltage Vss is applied, a gate and a drain are connected in common, and are connected to a constant current source.

[0115] The output gate NMOSQN ₁ is a one that receives the output of the operational amplifier OP to the gate, and the drain is connected to the output line 102 of the constant voltage generating circuit. Further, the power supply voltage Vss is applied to the source of the output gate NMOSQN _1.

The constant voltage control circuit 40 includes an NMOS QN ₁₀
It is configured to include a Qn _12. This constant voltage control circuit 4
0 is a constant voltage Vreg formed by the constant voltage generation circuit,
A circuit for controlling by controlling an input voltage of a + input terminal of the operational amplifier OP, wherein the NMOS QN is provided between a first potential and a second potential lower than the first potential. ₁₀ Qn ₁₃ of the respective gate and drain of the common operational amplifier OP - is connected to the input terminal. That is, each drain and gate of the NMOSQN ₁₀ ~QN ₁₂ together with is connected to the + input terminal of the operational amplifier OP, a source is electrically connected via the selection control circuit 30 to the output line 102 of the constant voltage generating circuit ing.

Here, the constant voltage control NMOS QN _10-
QN ₁₂ is formed with a respective different threshold voltages, the threshold voltage Vthn10 the NMOSQN _10, wherein NMOSQN ₁₁
Threshold voltage Vthn11, the threshold voltage Vt of the NMOSQN ₁₂
hn12 is, for example, Vthn10>Vthn11> Vthn1
2 are formed. The control of the threshold voltage can be performed by controlling the implantation concentration of impurities at the time of forming the transistor. At this time, for example, Vthn10 and Vthn11, V
Each potential difference between thn11 and Vthn12 can be set to about 0.1V.

Then, as described above, the selection control circuit 3
0 is connected to the constant voltage control circuit 40 and provided. That is, the constant voltage control NMOSs QN _{10 to} QN ₁₂
Each of which is connected to the drain in series, selection control NMOSQN ₁₃ ~QN ₁₅ for receiving a selection signal in each gate is provided to respectively correspond. The selection control for NMOSQN ₁₃ ~
The sources of the QNs ₁₅ are commonly connected to the output line 102 of the constant voltage generating circuit, and the potential of the output line 102 substantially becomes the output voltage Vreg of the constant voltage generating circuit.

The selection signal is a signal for selecting one of NMOSs constituting a constant voltage control circuit having a different threshold voltage, as in the example of the crystal oscillation circuit of the first embodiment. , select NMOSQN10 the selection signal SEL10 at the high level, selects the NMOSQN ₁₁ SEL11 is high level, it is possible to SEL12 to the selected state NMOSQN ₁₂ at a high level. When the selection signals SEL10 to SEL12 are at a low level, respectively,
MOS QN _{10 to} QN ₁₂ can be set to a non-selected state.

[0120] The different NMOSQN ₁₀ ~QN ₁₂ is a respective threshold voltage of the constant voltage control circuit 40, in order to form the constant voltage Vreg which is formed by the constant voltage generating circuit in an optimum state, the constant voltage control circuit NMO in one of 40
By applying a current to S, a voltage applied to the + input terminal of the operational amplifier OP, that is, a difference voltage from a voltage applied to the-input terminal can be selected, and the output signal of the operational amplifier OP, that is, the constant voltage Vreg is controlled. It is possible to do that.

That is, the selection signals SEL10 to SEL12 are selected.
The inputs to the selection control circuit 30, in which the control on and off of NMOSQN ₁₃ ~QN ₁₅ constituting the constant voltage control circuit 40, selects one NMOS formed in the optimum threshold voltage. The selection signals SEL10 to SEL12
FIG. 3 shows the voltage level switching method and circuit of FIG.
Since the selection signals SEL10 to SEL12 can be formed by the same switching method using the same circuit as shown in FIG.

Next, a method of selecting a constant voltage control circuit in the constant voltage generation circuit according to the present embodiment will be described. In the present embodiment, for example, a case where NMOS QN ₁₀ is selected will be described.

The selection signal SEL10 is set to the high level,
Since a high-level voltage is applied to the gate of the selection control NMOS QN ₁₃ , the NMOS QN ₁₃ turns on. Therefore, the constant voltage control circuit 40, by the source of NMOSQN ₁₀ are connected the power source voltage Vss and electrically via NMOSQN1 the ON state, NMOS constant-voltage control
QN ₁₀ can be selected.

On the other hand, since both of the selection signals SEL11 and SEL12 are at the low level, the selection control NMOS Q
The selection signal to the gate of the N _14, QN ₁₅ SEL11, SE
L12, that is, a low-level signal is applied.
MOS QN ₁₄ and QN ₁₅ are turned off. Therefore, the constant voltage control N
MOS QN ₁₁ and QN ₁₂ are electrically disconnected from both power supplies and are not selected.

FIG. 8 shows the constant voltage Vreg and the selection signal S.
The timing chart about the relationship of EL10-12 is shown. In FIG. 8, the horizontal axis represents time. Here, between the constant voltage | Vreg | and the ground voltage Vdd, as the difference voltage increases, the constant voltage | Vreg | increases.

First, by setting the selection signal SEL10 to the high level, as described above, the constant voltage becomes | Vreg
| = Α (| Vthp2 | + Vthn) (α: constant), so that the constant voltage | Vreg | is α (| Vthp2 | + Vthn).
10). When the selection signal SEL10 is at a low level and the selection signal SEL11 is at a high level, the constant voltage | Vreg | becomes α (| Vthp2 | + Vthn1
1). When the selection signal SEL11 is at a low level and the selection signal SEL12 is at a high level, the constant voltage | Vreg | becomes α (| Vthp2 | + Vthn12). That is, the constant voltage | Vreg | when SEL10 is set to the high level is the lowest, and the constant voltage | Vreg | is highest when SEL3 is set to the high level.

By the way, as described above, the selection of the NMOS included in the constant voltage control circuit 40 is performed by cutting the fuse in the IC inspection step by the same selection signal forming circuit as the circuit shown in FIG. . Further, similarly to the first embodiment, in the selection signal forming circuit,
Instead of the information storage method by blowing the fuse, information can be stored using a nonvolatile memory, a storage element, or the like.

In selecting the NMOS included in the constant voltage control circuit, as described in the first embodiment, the constant voltage Vreg and the oscillation stop voltage Vsto are | Vreg |> | Vsto |
Both conditions of lowering | Vreg | must be met. As described above, the oscillation stop voltage Vsto
Is the NMO of the transistor that constitutes the oscillation inverter.
Since it depends on the threshold voltages Vthn0 and | Vthp0 | of SQN ₀ and PMOS QP ₀ , the voltage level applied to a test pad connected to a test circuit (not shown) is controlled, and the selection signals SEL10, SEL11, and SEL12 are sequentially turned high. Level. Here, similarly to the test circuit described in the first embodiment, the test circuit selects the selection signals SEL10 to SEL1 to SEL1 to SEL1 by selecting a combination of the input signals to the test pads.
2 is a circuit including a logic circuit for selectively forming the test pad 2, and one or more test pads can be provided.

The constant voltage control NMOSs QN _{10 to} QN ₁₂
Are sequentially turned on to change the constant voltage Vreg, and the constant voltage Vreg is applied to the monitor pad MP connected to the output line 102.
Measure reg. At this time, the IC test is performed in a wafer state, and the constant voltage Vreg is measured for each IC chip using the test circuit, the test pad, and the monitor pad provided in each IC chip. . At the time of measurement, only the constant voltage control circuit 40 and the selection control circuit 30 are activated, and the other elements are in an inactive state.

Then, as described in the first embodiment,
The short-circuit current Is is measured in the oscillation inverter in the crystal oscillation circuit, and the optimum constant voltage Vreg satisfying the above relationship is specified. Then, the constant voltage control circuit 40 in the constant voltage generation circuit formed in the effective area of the IC chip.
, The fuse of the selection signal forming circuit connected to the specified optimum NMOS is cut, and one constant voltage control NMOS is selected.

Although the constant voltage generating circuit of the present embodiment has been described above, as described above, the constant voltage generating circuit of the present embodiment generates a constant voltage | Vreg | Since it can be realized without significantly increasing the number of transistors, the optimum constant voltage can be set without significantly increasing the chip area, and the constant voltage with low power consumption can be set. Vreg can be obtained.

In this embodiment, three types of constant voltage control NMOSs having different threshold voltages have been described. However, the number can be freely set without any particular limitation. The number of unit circuits of the voltage selection circuit can also be provided corresponding to the number of constant voltage control NMOSs.

In the present embodiment, the threshold voltage is set by the constant voltage control NMOS QN ₁₀ > QN ₁₁ > QN ₁₂ , that is,
Although described as Vthn10>Vthn11> Vthn12,
Without being limited to this, the threshold voltage can be set to QN ₁₀ <QN
₁₁ <QN ₁₂ , that is, Vthn10 <Vthn11 <Vthn1
It can also be set as 2.

In the first and second embodiments, the oscillation inverter of the crystal oscillation circuit can select the optimum oscillation inverter, and the constant voltage generation circuit can select the optimum NMOS of the constant voltage control circuit. However, as shown in FIG. 1, the constant voltage generation circuit of the first embodiment and the crystal oscillation circuit of the second embodiment can be simultaneously applied, as shown in FIG. It goes without saying that power consumption can be reduced. In this case, a first selection signal forming circuit for forming the selection signals SEL1 to SEL3 and a second selection signal forming circuit for forming the selection signals SEL10 to SEL12 are required, but the monitor pad is shared. be able to. Further, as described above, the circuit configurations of the first selection signal forming circuit and the second selection signal forming circuit can be the same. In the case of the configuration shown in FIG. 1, the optimum combination can be selected from the combination based on the measurement result of the short-circuit current of the oscillation inverter of the crystal oscillation circuit and the measurement result of the constant voltage Vreg. The yield can be improved while maintaining the characteristics, and the power consumption can be further reduced.

The crystal oscillation circuit, the constant voltage generation circuit, the oscillation inverter unit selection circuit, and the selection signal forming circuit of the present invention have been described with reference to the first and second embodiments. The selection signal forming circuit can be realized in various circuit configurations without being limited to the circuit configuration shown in the figure. For example, the fuse can be formed by polysilicon using a laser without applying a high voltage. The blown fuse can also be cut.

Third Embodiment FIG. 9 shows an example of an electronic circuit used for a wristwatch.

This wristwatch incorporates a power generation mechanism (not shown). When the user wears the wristwatch and moves his arm, the rotating weight of the power generating mechanism rotates, the kinetic energy at that time rotates the power generating rotor at high speed, and an AC voltage is output from the power generating coil 300 provided on the power generation status side. You.

This AC voltage is rectified by the diode 302 and charges the secondary battery 301. This secondary battery 301
Constitutes a main power supply together with the boosting circuit 303 and the auxiliary capacitor 304.

In the present embodiment, when the voltage of the secondary battery is low and less than the driving voltage of the timepiece, the booster circuit 303
, The voltage of the secondary battery is converted into a high voltage that can be driven by a clock, and stored in the auxiliary capacitor 304. Then, the clock circuit operates using the voltage of the auxiliary capacitor 304 as a power supply.

This timepiece circuit is configured as a semiconductor device including the oscillation circuit and the constant voltage generation circuit described in the first and second embodiments, and a crystal resonator X ′ connected to this semiconductor device via a terminal. It is configured to generate an oscillation output having a preset oscillation frequency, here 32768 Hz, using tal and divide this oscillation output to output drive pulses having different polarities every second. I have. This drive pulse is input to the drive coil 306 of the step motor connected to the clock circuit. This allows
The step motor (not shown) rotates the rotor every time a drive pulse is supplied, drives the second hand, minute hand, and hour hand of a timepiece (not shown), and displays the time on the display panel in an analog manner.

Here, the clock circuit 330 according to the present embodiment is described.
Is a power supply voltage circuit section 220 driven by a voltage supplied from the main power supply described above, and a second embodiment that generates a predetermined constant voltage Vreg lower than this value from the power supply voltage.
And a constant voltage Vreg.
And a constant voltage operation circuit section 240 driven by the

FIG. 10 is a more detailed functional block diagram of the clock circuit 330. As shown in FIG.

The constant voltage operation circuit section 240 includes the crystal oscillation circuit 200 described in the first embodiment partially including the externally connected crystal oscillator X′tal, the waveform shaping gate 201, And a frequency dividing circuit 202.

The power supply voltage circuit section 220 includes a level shifter 203, a middle / low frequency dividing circuit 204, and other circuits 205. In the timepiece circuit of the present embodiment, the power supply voltage circuit section 220 and the constant voltage generation circuit 210 constitute a power supply voltage operation circuit section 240 driven by a voltage supplied from a main power supply.

The crystal oscillation circuit 200 outputs a sine wave output having a reference frequency fs = 32768 Hz to the waveform shaping gate 201 by using the crystal oscillator X′tal.

The waveform shaping gate 201 shapes the sine wave output into a rectangular wave, and outputs the rectangular wave to the high frequency dividing circuit 202.

The high frequency divider 202 divides the reference frequency 32768 Hz to 2048 Hz, and outputs the divided output via the level shifter 203 to the middle / low frequency divider 2.
04.

The medium / low frequency dividing circuit 204
The signal that has been frequency-divided to 8 Hz is further frequency-divided to 1 Hz and input to the other circuit 205.

The other circuit 205 includes a driver circuit for energizing and driving the coil in synchronization with the 1-Hz divided signal, and drives the timepiece drive step motor in synchronization with the 1-Hz divided signal. I do.

In the timepiece circuit of the present embodiment, in addition to the power supply voltage operation circuit section 240 in which the whole circuit is driven by the power supply voltage Vss supplied from the main power supply, a constant voltage operation driven by a lower constant voltage Vreg The circuit section 220 is provided for the following reason.

That is, in such a clock circuit, it is necessary to reduce the power consumption in order to secure a stable operation for a long time.

Normally, the power consumption of the circuit depends on the frequency of the signal,
It increases in proportion to the capacity of the circuit and further in proportion to the square of the supply voltage.

Here, paying attention to the clock circuit, in order to reduce the power consumption of the whole circuit, the power supply voltage supplied to each part of the circuit may be set to a low value, for example, Vreg. As described in the second embodiment, the constant voltage generation circuit 210 can form the minimum constant voltage Vreg within a range in which the oscillation operation of the crystal oscillation circuit 200 is compensated.

Next, focusing on the signal frequency, the clock circuit is roughly divided into a crystal oscillation circuit 200 having a high signal frequency, a waveform shaping gate 201, a high frequency frequency dividing circuit 202, and a circuit 205 other than the above. be able to. As described above, the frequency of this signal is proportional to the power consumption of the circuit.

Therefore, the constant voltage generating circuit 2 of the present embodiment
10 generates a constant voltage Vreg lower than the power supply voltage Vss supplied from the main power supply, and converts the generated constant voltage Vreg into a circuit unit 230 that handles a high-frequency signal, that is, a crystal oscillation circuit 200, a waveform shaping gate 201, and a high-frequency frequency dividing circuit 202 To supply. As described above, by lowering the drive voltage supplied to the circuit 230 that handles the high-frequency signal, the power consumption of the entire timepiece circuit can be effectively reduced without increasing the load on the constant voltage generation circuit 210 so much. be able to.

In this embodiment, the level shifter 203 is provided between the high frequency divider 202 and the middle / low frequency divider 204 for the following reason.

The output peak value of the high frequency frequency dividing circuit 202 is at the level of the constant voltage Vreg, and is smaller than the peak value of the voltage Vss of the main power supply. For this reason, even if the constant voltage Vreg level output of the high frequency divider 202 is directly input to the middle / low frequency divider 204 driven by the power supply voltage Vss, this input value is applied to the middle / low frequency divider. Since the voltage does not exceed the logic level voltage at the first stage of 202, the middle / low frequency dividing circuit 204 does not operate normally. Therefore, the middle and low frequency divider 204
In order to operate normally, the output peak value of the high frequency frequency dividing circuit 202 is raised from the constant voltage level to the power supply voltage level by using the level shifter 203.

As described above, the clock circuit of this embodiment and the electronic circuit including the same include the crystal oscillation circuit of the first embodiment and the constant voltage generation circuit of the second embodiment. Irrespective of the variation, the operation of the oscillation inverter can supply the minimum constant voltage to the crystal oscillation circuit while securing a margin, so that the power consumption of the electronic circuit and the clock circuit can be reduced. Therefore, in the watch or the portable electronic device as described above, not only can the oscillation operation be performed stably, but also the life of the battery can be extended, and the usability of the watch or the portable electronic device can be improved. Can be improved.

[0159]

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an oscillation circuit including a constant voltage generation circuit according to a second embodiment of the present invention and a crystal oscillation circuit according to the first embodiment.

FIG. 2 is a schematic diagram of an oscillation circuit having the crystal oscillation circuit according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram of an oscillation inverter selection circuit according to the first embodiment of the present invention.

FIG. 4 is a schematic timing chart showing a relationship between an oscillation stop voltage and a selection signal according to the first embodiment of the present invention.

FIG. 5 is a diagram for explaining a method for measuring a short-circuit current of an oscillation inverter according to the present invention, and a graph showing a relationship between an oscillation stop voltage and a short-circuit current.

FIG. 6 is a schematic diagram showing a gate waveform and a drain waveform of the crystal oscillation circuit according to the first embodiment of the present invention.

FIG. 7 is a schematic diagram of an oscillation circuit having a constant voltage generation circuit according to a second embodiment of the present invention.

FIG. 8 is a schematic diagram of a timing chart showing a relationship between a constant voltage and a selection signal according to the second embodiment of the present invention.

FIG. 9 is a functional block diagram of a timepiece according to a third embodiment of the present invention.

FIG. 10 is a functional block diagram of a portable electronic device according to a third embodiment of the present invention.

FIG. 11 is a schematic diagram of an oscillation circuit having a conventional constant voltage generation circuit and a crystal oscillation circuit according to the present invention.

FIG. 12 is a graph showing a relationship between a constant current flowing through an NMOS connected to a constant current source and a gate-source voltage in a conventional constant voltage generating circuit.

FIG. 13 is a diagram showing a relationship between temperature and voltage with respect to a constant voltage | Vreg | and an oscillation stop voltage | Vsto |.

[Explanation of symbols]

Reference Signs List 10 oscillation inverter group 20P, 20N selection control circuit (crystal oscillation circuit) 30 selection control circuit (constant voltage generation circuit) 40 constant voltage control circuit INV1-3 oscillation use inverter unit P1 to P3 · · · pad OP · · · op Rf · · · feedback resistor C _G, C _D ··· compensation capacitor X'tal · · · crystal oscillator U1 to U4 · · · unit circuits F1 F3: fuse circuit f1 to f3: fuse R1 to R3: resistor I1 to I3: output inverter 200: crystal oscillation circuit 201: gate for waveform shaping 202: high frequency component Circumferential circuit 203 ・ ・ ・ Level shifter 204 ・ ・ ・ Medium / low frequency dividing circuit 205 ・ ・ ・ Other circuits 210 ・ ・ ・ Constant voltage generation circuit 220 ・ ・ ・ Power supply voltage circuit section 230 ・ ・ ・ Constant voltage drive Work circuit portion 240 ... voltage operating circuit 300 ... generating coil 301 ... secondary battery 302 ... diode 303 BOOST circuit 304 ... auxiliary capacitor 306 ... watch motor coil

Claims (21)

[Claims] 1. An oscillation inverter group including a plurality of oscillation inverters configured by using transistors having different threshold voltages, wherein one of the oscillation inverters is selectively used, and an output of the oscillation inverter group. And a feedback circuit that inverts the phase of the output signal of the oscillation inverter group and feeds back the input signal to the oscillation inverter group. circuit. 2. The oscillation circuit according to claim 1, further comprising a selection circuit for selecting any one of the oscillation inverters from the oscillation inverter group. 3. The oscillating circuit according to claim 2, wherein the oscillating circuit is formed on the same substrate as the test circuit, and the test circuit controls the oscillating inverters in a state where the crystal oscillator is not mounted. By selecting and measuring the short-circuit current of each of the oscillation inverters,
An oscillation circuit characterized in that one oscillation inverter is specified from the oscillation inverter group, and the selection circuit selects the oscillation inverter. 4. The test circuit according to claim 3, wherein the test circuit is connected to a test pad, and a voltage applied to the test pad is controlled.
An oscillation circuit, wherein each of the oscillation inverters is selected via the test circuit. 5. The method according to claim 1, wherein the selection circuit includes a plurality of unit circuits provided corresponding to the oscillation inverter and connected to a plurality of pads. An oscillation circuit, wherein each of the unit circuits includes one of a fuse, a nonvolatile memory, and a storage element, and selects the oscillation inverter by applying a voltage to the pad. 6. The oscillation inverter group according to claim 1, wherein the oscillation inverter group includes a first oscillation inverter including a transistor having a first threshold voltage, and the first threshold voltage. A second oscillation inverter including a transistor having a second threshold voltage different from the first and second threshold voltages different from the first and second threshold voltages.
An oscillation circuit comprising at least a third oscillation inverter including a transistor having a threshold voltage. 7. The oscillation line according to claim 1, wherein a power supply line of each of the oscillation inverters is connected to a first potential side and a second potential side different from the first potential side. An oscillation circuit, wherein the circuit performs amplitude with a potential difference between the first potential and the second potential. 8. The oscillation circuit according to claim 7, wherein a potential difference between the first potential and the second potential is larger than an absolute value of an oscillation stop voltage of the oscillation inverter. 9. The oscillation inverter according to claim 7, wherein a short-circuit current flowing through the selected oscillation inverter is larger than an ON current of a transistor constituting the selected oscillation inverter. An oscillation circuit that performs selection and sets a potential difference between the first potential and the second potential to a minimum voltage. 10. A constant voltage control circuit having one end connected to a first potential side and the other end connected to a constant voltage output side, including a plurality of transistors each having a different threshold voltage, wherein one of the transistors is selectively used. An operational amplifier in which a reference voltage of the constant voltage control circuit is input to one terminal and a given reference voltage is input to the other terminal, and one end is connected to the other end of each of the transistors of the constant voltage control circuit. A transistor whose other end is connected to the second potential side and whose gate input voltage is controlled by receiving the output of the operational amplifier. 11. The constant voltage generation circuit according to claim 10, wherein the constant voltage generation circuit includes a selection circuit that selects one transistor from a plurality of transistors in the constant voltage control circuit. 12. The constant voltage control circuit according to claim 11, wherein the constant voltage generation circuit is connected to a monitor terminal and provided on the same substrate as a test circuit. By selecting each transistor and measuring the output voltage of each transistor in the constant voltage control circuit at the monitor terminal, one transistor is identified from the plurality of transistors in the constant voltage control circuit, and the selection is performed. A constant voltage generating circuit, wherein the transistor is selected by a circuit. 13. The test circuit according to claim 12, wherein the test circuit is connected to a test pad, and a voltage applied to the test pad is controlled.
A constant voltage generation circuit, wherein each transistor in the constant voltage control circuit is selected via the test circuit. 14. The plurality of unit circuits according to claim 10, wherein the selection circuit is formed corresponding to the plurality of transistors in the constant voltage control circuit and connected to a plurality of pads. Wherein each of the plurality of unit circuits includes any one of a fuse, a nonvolatile memory, and a storage element, and selects the transistor by applying a voltage to the pad. Voltage generation circuit. 15. The transistor according to claim 10, wherein the constant voltage control circuit includes a transistor having a fourth threshold voltage, and a transistor having a fifth threshold voltage different from the fourth threshold voltage. And a transistor having a sixth threshold voltage different from the fourth and fifth threshold voltages, wherein each of the transistors has one end connected to the first potential side and the other end connected to the constant voltage output side. A constant voltage generation circuit characterized in that: 16. The constant voltage generation circuit according to claim 10, wherein an output voltage of the constant voltage generation circuit is supplied to an oscillation circuit. 17. A semiconductor device including an oscillation circuit, a constant voltage generation circuit, and a test circuit, wherein the oscillation circuit includes a plurality of oscillation inverters configured using transistors having different threshold voltages. An oscillation inverter group in which any one of the oscillation inverters is selectively used; a first selection circuit for selecting one oscillation inverter from a plurality of oscillation inverters in the oscillation inverter group; Invert the phase of the output signal of the oscillation inverter group connected to the crystal oscillator and the output side and the input side,
A feedback circuit for feedback-inputting the oscillation inverter group; wherein the constant voltage generating circuit has a plurality of transistors each having one end connected to the first potential side and the other end connected to the constant voltage output side, and having different threshold voltages. Including
A constant voltage control circuit in which any one of the transistors is selectively used; an operational amplifier in which a reference voltage of the constant voltage control circuit is input to one terminal and a given reference voltage is input to the other terminal; A transistor connected to the other end of each of the transistors of the constant voltage control circuit, the other end connected to the second potential side, and a gate input voltage controlled by receiving the output of the operational amplifier; and the constant voltage control circuit. From multiple transistors in 1
A second selection circuit for selecting one of the transistors, wherein the test circuit is connected to the oscillation circuit and the constant voltage generation circuit, respectively, and a monitor terminal for monitoring an output voltage of the constant voltage generation circuit; In the inspection step, a voltage applied to the monitor terminal is controlled in an inspection step, so that the voltage applied to the test pad is controlled, so that each of the oscillations can be controlled through the test circuit. By selecting an inverter and measuring the short-circuit current of each of the oscillation inverters, and controlling the voltage applied to the test pad after the short-circuit current is measured, the constant voltage control is performed via the test circuit. Selecting each transistor in the circuit, measuring the output voltage of each transistor at the monitor terminal, To the extent that the oscillation operation can be secured in use inverter,
The oscillation inverter in the oscillation circuit is selected by the first selection circuit, and a transistor in a constant voltage control circuit in the constant voltage generation circuit is selected by the second selection circuit. Semiconductor device. 18. A portable electronic device including the oscillation circuit according to claim 1, wherein an operation reference signal is formed from an oscillation output of the oscillation circuit. 19. The method according to claim 18, wherein a supply voltage to the oscillation circuit is formed.
6. A portable electronic device comprising the constant voltage generating circuit according to any one of 6. 20. A timepiece including the oscillation circuit according to claim 1, wherein a timepiece reference signal is formed from an oscillation output of the oscillation circuit. 21. The method according to claim 20, wherein a supply voltage to the oscillation circuit is formed.
6. A timepiece comprising the constant voltage generating circuit according to any one of 6.