JPH11274508A - Method for manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing thin film transistors which enhances a breakdown voltage by using polycrystal silicon. SOLUTION: A polycrystal silicon film is formed on a transparent insulation substrate 21 and is exposed to oxygen plasma to form an insulation film, and thereafter the insulation film is peeled off. A gate insulation film 36 is deposited on the polycrystal silicon film, and a conductive film is formed and patterned to form a gate layer 27. The gate layer 27 is self-aligned and doped, and a gate insulation film, a channel region 23, a source region 24 and a drain region 25 are simultaneously etched and formed. An interlayer insulation film 28 is deposited and a contact hole 29 is formed in the interlayer insulation film 28, and a gate electrode 31, a source electrode 32 and a drain electrode 33 are formed to complete thin film transistors 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor having an improved withstand voltage.

[0002]

2. Description of the Related Art In recent years, a thin film transistor having a polycrystalline semiconductor as an active layer has been used as a pixel switching element or a driving circuit forming element of a liquid crystal display element.

A process of manufacturing a thin film transistor using polycrystalline silicon as a polycrystalline semiconductor will be described with reference to FIGS.

[0004] First, as shown in FIG. 26, a semiconductor layer is deposited and patterned on a transparent insulating substrate 1 to form an active layer 2, and a gate insulating film 3 is formed on the transparent insulating substrate including the active layer 2. cover.

[0007] Next, as shown in FIG. 27, a conductor layer film is formed on the active layer 2 via the gate insulating film 3 and is patterned to form a gate electrode 4.

Then, self-alignment is performed using gate electrode 4 as a mask, an impurity is implanted into active layer 2 to activate and match channel region 5 with gate electrode 4 and low-resistance source and drain regions adjacent to channel region 5. To form

The gate insulating film 3 including the gate electrode 4
An interlayer insulating layer 8 is formed thereon, a contact hole 9 is formed in the interlayer insulating layer 8 and the gate insulating film 3, a metal layer is formed in the contact hole 9, and a source electrode 10 connected to the source region 6 is formed. And a drain electrode 11 connected to the drain region 7 to form a top-gate thin film transistor 12.

As described above, as a thin film transistor using a polycrystalline semiconductor such as polycrystalline silicon, a thin film transistor using a high temperature process with a maximum process temperature of about 1000 ° C. has been put to practical use.

On the other hand, in recent years, the cost has been reduced by using a non-alkali glass having a heat resistant temperature of 600 ° C. or less for a transparent insulating substrate. When the heat-resistant temperature is low, a low-temperature process is used. In the low-temperature process, the active layer is irradiated with excimer laser on amorphous silicon deposited by a low-pressure CVD (Chemical Vapor Deposition) method or a plasma CVD method. After melt crystallization, a silicon oxide film is deposited as a gate insulating film by a plasma CVD method, or a silicon oxide film is deposited by an atmospheric pressure CVD method.
It is formed by annealing at about 0 ° C.

[0010]

However, the thin film transistor 12 formed by such a low-temperature process has a problem in withstand voltage.

For example, a comparison between the case where the active layer is formed of amorphous silicon and the case where the active layer is formed of polycrystalline silicon using the top gate type thin film transistor having the same shape as described above, Has a low withstand voltage as compared with the case where it is formed of amorphous silicon.

The present invention has been made in consideration of the above problems, and has as its object to provide a method of manufacturing a thin film transistor using polycrystalline silicon and having improved withstand voltage.

[0013]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a polycrystalline semiconductor thin film on an insulating substrate, a step of exposing the semiconductor thin film to gas plasma, and a step of exposing the semiconductor thin film to gas plasma. Peeling off the insulating film, and covering the gate insulating film on the semiconductor thin film from which the insulating film has been peeled off, by forming the insulating film on the semiconductor thin film in a gas plasma process, The unevenness on the surface of the polycrystalline semiconductor thin film is reduced, the electric field concentration is reduced, and the withstand voltage is improved by preventing dielectric breakdown.

The gas plasma contains at least one of oxygen and nitrogen.
An insulating film is formed on the surface of the semiconductor thin film by oxidation or nitridation.

Further, the step of exposing to the gaseous plasma includes:
The temperature is 50 ° C. or less, and can be applied to a low-temperature process.

Further, the present invention provides a step of forming a semiconductor thin film on an insulating substrate, a step of forming a gate insulating film on the semiconductor thin film, a step of forming a conductor film on the gate insulating film, The step of simultaneously etching the gate insulating film and the conductive film, and simultaneously etching the gate insulating film and the conductive film, thereby preventing the conductive film from overlapping the side surface of the semiconductor thin film. Also, withstand voltage is improved by preventing dielectric breakdown.

Further, the steps of forming a semiconductor thin film on an insulating substrate, forming a gate insulating film on the semiconductor thin film, and forming a conductor film on the gate insulating film are performed in a vacuum. Since it is formed consistently, unnecessary oxidation or nitridation does not occur, and the interface state is lowered.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a thin film transistor according to the present invention will be described below with reference to the drawings.

As shown in FIGS. 1 and 2, an n-type or p-type thin film transistor (Thin F) is formed on a transparent insulating substrate 21.
ilm Transistor) 22 is formed.

First, a 50 nm-thickness channel region 23 which becomes an active layer of polycrystalline silicon and is doped with phosphorus (P) for n-type and boron (B) for p-type is formed. A source region 24 and a drain region 25 are formed adjacent to 23, respectively.

Further, a gate insulating film 26 of silicon oxide (SiO ₂ ) having a thickness of 100 nm is formed on the upper surface of the channel region 23 and the like, and an alloy is formed above the channel region 23 via the gate insulating film 26. Gate layer 27 is formed. On the entire surface including the gate layer 27, an interlayer insulating film 28 of silicon oxide (SiO ₂ ) having a thickness of 500 nm is formed.
Is formed, and a contact hole 29 is formed in the interlayer insulating film 28.
Is formed in the contact hole 29. A 600 nm-thick aluminum (Al) gate electrode 31 connected to the gate layer 27 and a 600 nm-thickness connected to the source region 24 are formed in the contact hole 29.
A drain electrode 33 made of aluminum having a thickness of 600 nm connected to the source electrode 32 made of aluminum and the drain region 25 is formed by deposition.

Next, the manufacturing method of the above embodiment will be described.

First, as shown in FIG.
On top of Plasma Enhanced CVD
An amorphous silicon layer having a thickness of 50 nm is formed by a Chemical Vapor Deposition method. Then, by annealing at 450 ° C., the hydrogen concentration in the amorphous silicon layer is reduced, the amorphous silicon is polycrystallized by excimer laser light irradiation, and the polycrystalline silicon film 35 as a semiconductor thin film is formed. To form The pressure is 160 Pa and the RF power is 0.5 W
/ Cm ² , at a substrate temperature of 420 ° C., the substrate is exposed to oxygen plasma containing an oxygen element to form an insulating film of silicon oxide (SiO ₂ ) on the surface of the polycrystalline silicon film 35, and is etched with a buffered fluorine solution for 30 seconds. Is peeled off.

Next, as shown in FIG. 4, a plasma enhanced CVD method using TEOS and oxygen as source gases at a substrate temperature of 350 ° C. is performed on the polycrystalline silicon film 35.
A gate insulating film 36 serving as a gate oxide film of a silicon oxide film having a thickness of 100 nm is deposited.

Then, a conductive film of an alloy of molybdenum and tungsten is formed on the gate insulating film 36 by a sputtering method, and is patterned.
A gate layer 27 is formed as shown in FIG. Also, the gate layer
27 is self-aligned and doped by an ion doping method with an impurity, phosphorus for n-type, and boron for p-type with a doping amount of 1e ¹⁶ atms / cm ² ,
A channel region 23 self-aligned with the gate layer 27 and low-resistance regions 38 and 38 adjacent to the channel region 23 are formed, and are activated by excimer laser light irradiation.

As shown in FIGS. 7 and 8, the gate insulating film 36 and the low-resistance region 38 are simultaneously etched and islanded to form the gate insulating film 26, the source region 24, and the drain region 25.

Further, as shown in FIG. 1 and FIG. 2, a film thickness of 5
An interlayer insulating film 28 of a 00 nm silicon oxide film is deposited.
Then, a contact hole 29 is formed in the interlayer insulating film 28,
Sputtering aluminum, each thickness 6
The gate electrode 31 connected to the 00 nm gate layer 27, the source electrode 32 connected to the source region 24, and the drain region
The drain electrode 33 connected to 25 is formed, and the thin film transistor 22 is completed.

The breakdown voltage of the thin film transistor 22 of the above-described embodiment, the thin film transistor using conventional polycrystalline silicon, and the thin film transistor using amorphous silicon are compared with each other. In the case of the thin film transistor 22 of this embodiment, the withstand voltage can be increased as compared with the conventional thin film transistor using polycrystalline silicon shown in FIG. 10, and the thin film transistor using amorphous silicon shown in FIG. The dielectric strength can be approached.

Here, considering the reason why the breakdown voltage of the thin film transistor is reduced when polycrystalline silicon is used for the active layer, irregularities are formed on the surface of the polycrystalline silicon during formation and irregularities are formed on the side surfaces during etching. Arises
This is because the electric field is concentrated due to these irregularities and the insulation withstand voltage is reduced.

Further, TEOS is deposited on the polycrystalline silicon thin film.
Thickness 100 formed by plasma CVD using oxygen and oxygen
The dielectric breakdown voltage of the silicon thin film of nm will be described with reference to FIGS.

The silicon thin film formed on the polycrystalline silicon thin film as it is shown in FIG. 12 has a much lower dielectric strength than the silicon thin film formed on the crystalline silicon thin film shown in FIG. On the other hand, in the case where the silicon thin film is formed on the polycrystalline silicon thin film whose surface has been made uneven by polishing as shown in FIG. 14, the withstand voltage is increased, and in the case where the silicon thin film is formed on the crystalline silicon thin film shown in FIG. The dielectric strength is almost equal.

As described above, the dielectric breakdown voltage is greatly increased by polishing and flattening the irregularities on the surface of the polycrystalline silicon. However, for example, the polycrystalline silicon of a large transparent insulating substrate used for a liquid crystal display element is used. It is very difficult to polish the silicon film surface.

The surface shown in FIG. 15 is exposed to oxygen plasma to form an insulating film, and a silicon thin film is formed on the polycrystalline silicon thin film from which the insulating film has been peeled off.
Although not as polished as shown in FIG. 4, the dielectric strength is improved.

This is considered to be due to the effect of removing the insulating film formed by the oxidation, thereby rounding off the projections and depressions on the surface and reducing the concentrated electric field.

On the other hand, the reason why the insulating film formed by oxidizing the surface is peeled off is that the oxide film formed by plasma is rich in silicon and contains many electric charges in the film. If the insulating film is not removed, the threshold voltage of the thin film transistor shifts by about 2 V when the insulating film is not removed.

The decrease in dielectric strength of the polycrystalline silicon thin film transistor shown in FIG. 10 is larger than that of the polycrystalline silicon thin film shown in FIG. This is because not only the irregularities on the surface of the polycrystalline silicon thin film but also the irregularities are formed on the side surfaces of the polycrystalline silicon thin film after the island is cut off. The effect of the unevenness appears remarkably.

Further, the thin film transistor of amorphous silicon has a dielectric breakdown voltage close to that of polycrystalline silicon having a step formed of metal as shown in FIG.

Further, according to the above embodiment, the gate layer 27 does not overlap the side walls of the source region 24 and the drain region 25, and the step is covered with the thick interlayer insulating film 28. The withstand voltage of the thin film transistor 22 is determined by the flat withstand voltage.

Next, another embodiment will be described with reference to FIGS.
This will be described with reference to elements for forming a drive circuit integrated type liquid crystal display element shown in FIG.

As shown in FIGS. 24 and 25, an n-type thin film transistor (Thin Film Tran) is formed on a transparent insulating substrate 41.
sistor) 42, p-type thin film transistor 43 and storage capacitor 44
Are formed.

First, a channel region 45 of an n-type thin film transistor 42 is formed on a transparent insulating substrate 41, and an LDD (Light Doped Drain) region 4 is formed adjacent to the channel region 45.
6 and 46 are formed, and the channel region 4 of these LDD regions 46 is formed.
On the opposite side of 5, a source region 47 and a drain region 48 of an n ⁺ region are formed, respectively. Similarly, a channel region 51 of a p-type thin film transistor 43 is formed on a transparent insulating substrate 41, and a source region 52 and a drain region 53 of an n ⁺ region are formed adjacent to the channel region 51. Further, a silicon film 54 of the auxiliary capacitance 44 is formed on the transparent insulating substrate 41.

Further, a gate insulating film 5 made of silicon oxide (SiO ₂ ) is formed on the upper surfaces of these channel regions 45 and 51 and the like.
5 and 56 are formed, gate layers 57 and 58 are formed above the channel regions 45 and 51 via the gate insulating films 55 and 56, and a silicon oxide film 61 and a metal film are formed on the silicon film 54.
62 are laminated.

On the gate layers 57 and 58 and the metal film 62, an interlayer insulating film 63 is formed.

Further, a contact hole 64 of the n-type thin film transistor 42 is formed in the interlayer insulating film 63, and a gate electrode 65 connected to the gate layer 57 is formed in the contact hole 64.
Source electrode 66 connected to source region 47, drain region
A drain electrode 67 connected to 25 is formed by deposition. Further, similarly, a contact hole 71 of the p-type thin film transistor 43 is formed in the interlayer insulating film 63, and a gate electrode 72 connected to the gate layer 58 is formed in the contact hole 71.
Source electrode 73 connected to source region 52, drain region
A drain electrode 74 connected to 53 is formed by deposition. An auxiliary capacitance electrode 75 is formed on the auxiliary capacitance 44 so as to face the metal film 62.

Next, the manufacturing method of the above embodiment will be described.

First, as shown in FIG.
41 forming a polycrystalline silicon film 81 as a semiconductor thin film on, at a temperature of about 450 ° C., exposed to an oxygen plasma containing elemental oxygen, the surface silicon oxide of the polycrystalline silicon film 81 which is a semiconductor thin film (SiO ₂ ) Is formed, and the surface insulating film is removed by etching with a buffered hydrofluoric acid solution.

Next, as shown in FIGS. 18 and 19,
On the polycrystalline silicon film 81, a silicon oxide film 82 serving as a gate oxide film and a metal film 83 are deposited, and the metal film 83 is patterned. Then, the low resistance region 84 is formed by implanting impurities.

Further, as shown in FIG. 20, the metal film 83 is patterned again to form a gate layer 57, the gate layer 57 is self-aligned, an impurity is implanted again, and n is formed adjacent to the channel region 45. ^{In addition} to forming the LDD regions 46 and 46 of the-region, an n ⁺ region 85 is formed.

As shown in FIG. 21, a resist 86 is deposited and patterned to mask the entire region of the n-type thin film transistor 42 and the gate layer 58 of the p-type thin film transistor 43, and to form a channel region 51 and an adjacent p ⁺ region. Form 87.

Then, as shown in FIGS. 22 and 23, the silicon oxide film 61 and the n ⁺ region 85, the p ⁺ region 87, the silicon oxide film 61 and the metal film 62 are simultaneously etched to form islands. The gate insulating film 55 of the thin film transistor 42,
A source region 47 and a drain region 48 are formed, a gate insulating film 56 of the p-type thin film transistor 43, a source region 52 and a drain region 53 are formed, and a silicon oxide film of the auxiliary capacitance 44 is formed.
61 and a metal film 62 are formed.

Further, as shown in FIGS. 24 and 25, an interlayer insulating film 63 of a silicon oxide film is deposited on the entire surface. Then, contact holes 64 and 71 are formed in the interlayer insulating film 63 and connected to the gate electrode 65 connected to the gate layer 57 of the n-type thin film transistor 42, the source electrode 66 connected to the source region 47, and the drain region 48. Drain electrode 67
A gate electrode 72 connected to the gate layer 58 of the p-type thin film transistor 43, a source electrode 73 connected to the source region 52, and a drain electrode connected to the drain region 53.
74 is formed, and the auxiliary capacitance electrode 75 of the auxiliary capacitance 44 is formed to complete the process.

Also in the above embodiment, n is reduced by the two effects that the unevenness of the surface of polycrystalline silicon, which is a polycrystalline semiconductor, is reduced, and that the gate layers 57, 58 do not overlap the side portions of the polycrystalline silicon. The breakdown voltage of the p-type thin film transistor 42 and the p-type thin film transistor 43 can be increased.

In each of the embodiments, oxygen plasma is used to alleviate the irregularities on the surface of polycrystalline silicon. However, the same effect can be obtained by forming silicon nitride by nitriding. it can. Furthermore, when the nitriding treatment may be used NH ₃ or N ₂ plasma, N ₂ O
Oxidation and nitridation may be performed simultaneously using a gas or a mixed plasma of N ₂ and O ₂ to form silicon oxynitride.

Further, in each of the embodiments, the two effects of reducing the unevenness of the surface of polycrystalline silicon, which is a polycrystalline semiconductor, and preventing the gate layer from overlapping on the side are simultaneously used. Even when used alone, each has a certain effect. In particular, the process of forming a semiconductor thin film on a transparent insulating substrate, the process of forming a gate insulating film, and the process of forming a conductor layer are performed in a vacuum consistent manner, and the gate layer does not overlap with the side portions of the polycrystalline silicon. When the effect is used, the interface state between the gate insulating film and the semiconductor thin film can be reduced, and the characteristics of the thin film transistor are improved.

[0055]

According to the present invention, by forming an insulating film on a semiconductor thin film in a gas plasma process, unevenness on the surface of a polycrystalline semiconductor thin film is reduced, electric field concentration is reduced, and dielectric breakdown is reduced. By preventing this, the withstand voltage can be improved.

Further, by simultaneously etching the gate insulating film and the conductor film, the conductor film does not overlap the side surface of the semiconductor thin film, and the withstand voltage can be improved by preventing dielectric breakdown.

Further, the steps of forming a semiconductor thin film on an insulating substrate, forming a gate insulating film on the semiconductor thin film, and forming a conductor film on the gate insulating film are performed in a vacuum. Since it is formed consistently, unnecessary oxidation or nitridation does not occur, and the interface state is lowered to improve the characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a thin film transistor according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view cut along another surface of the same.

FIG. 3 is a sectional view showing one manufacturing process of the thin film transistor.

FIG. 4 is a cross-sectional view showing a manufacturing step following that of FIG. 3 for the thin film transistor;

FIG. 5 is a cross-sectional view showing the next manufacturing step of the thin film transistor shown in FIG. 4;

FIG. 6 is a cross-sectional view taken along another surface of the same.

FIG. 7 is a cross-sectional view showing a manufacturing step subsequent to FIG. 5 for the thin film transistor.

FIG. 8 is a cross-sectional view taken along another surface of the same.

FIG. 9 is a graph showing the withstand voltage of the thin film transistor.

FIG. 10 is a graph showing the withstand voltage of a conventional thin film transistor using polycrystalline silicon.

FIG. 11 is a graph showing a withstand voltage of a thin film transistor using amorphous silicon.

FIG. 12 is a graph showing the withstand voltage of a silicon thin film formed on a polycrystalline silicon thin film as it is.

FIG. 13 is a graph showing the withstand voltage of a silicon thin film formed on a crystalline silicon thin film.

FIG. 14 is a graph showing the withstand voltage of a silicon thin film formed on a polycrystalline silicon thin film whose surface has been made uneven by polishing.

FIG. 15 is a graph showing the dielectric strength of a silicon thin film formed on polycrystalline silicon whose surface has been exposed to oxygen plasma to remove the insulating film.

FIG. 16 is a graph showing the withstand voltage of polycrystalline silicon formed with a metal step.

FIG. 17 is a cross-sectional view showing one manufacturing step of the thin-film transistor according to another embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a manufacturing step following that of FIG. 17 for manufacturing the thin film transistor;

FIG. 19 is a cross-sectional view taken along another surface of the same.

FIG. 20 is a cross-sectional view showing the next manufacturing step of the thin film transistor shown in FIG. 18;

FIG. 21 is a cross-sectional view showing the next manufacturing step of the thin film transistor shown in FIG. 20;

FIG. 22 is a cross-sectional view showing a manufacturing step following that of FIG. 21 for manufacturing the thin film transistor;

FIG. 23 is a cross-sectional view cut along another surface of the same.

FIG. 24 is a cross-sectional view showing the next manufacturing step of the thin film transistor shown in FIG. 22;

FIG. 25 is a cross-sectional view taken along another surface of the same.

FIG. 26 is a cross-sectional view showing one manufacturing step of a conventional thin film transistor.

FIG. 27 is a cross-sectional view showing the next manufacturing step of the thin film transistor shown in FIG. 26;

FIG. 28 is a cross-sectional view showing a manufacturing step following that of FIG. 27 for manufacturing the thin film transistor;

FIG. 29 is a cross-sectional view showing the next manufacturing step of FIG. 28 for manufacturing the thin film transistor.

FIG. 30 is a cross-sectional view taken along another surface of the same.

[Explanation of symbols]

 21, 41 Transparent insulating substrate 22, 42, 43 Thin film transistor 35, 81 Polycrystalline silicon film as semiconductor thin film 55, 56 Gate insulating film

Claims (5)

[Claims] A step of forming a polycrystalline semiconductor thin film on an insulating substrate; a step of exposing the semiconductor thin film to gas plasma; and a step of exfoliating an insulating film formed on the semiconductor thin film in the step of exposing to the gas plasma. And a step of coating a gate insulating film on the semiconductor thin film from which the insulating film has been peeled off. 2. The method according to claim 1, wherein the gaseous plasma contains at least one of oxygen and nitrogen. 3. The step of exposing to gas plasma at 650 ° C.
3. The method according to claim 2, wherein the temperature is as follows. A step of forming a semiconductor thin film on the insulating substrate; a step of forming a gate insulating film on the semiconductor thin film; a step of forming a conductor film on the gate insulating film; And a step of simultaneously etching the conductor film. 5. The step of forming a semiconductor thin film on an insulating substrate, the step of forming a gate insulating film on the semiconductor thin film, and the step of forming a conductor film on the gate insulating film are performed in a vacuum. 5. The method for manufacturing a thin film transistor according to claim 4, wherein the thin film is formed consistently.