JPH11250001A - Memory drive device, memory module and personal computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flexibly design a transmission line to memory modules. SOLUTION: A memory driving device 10 is provided with driving means (buffer circuit) 52 which simultaneously drive the arbitrary number of driving means #1-#m connected to a transmission line 53 having prescribed impedances 55-57. A plurality of driving means 52 are especially provided. A plurality of switches 1 which selectively validate the outputs of a plurality of driving means 52 and an output control means 2 which detects the whole capacity of the memory modules #1-#m connected to the transmission line 53 and selectively connects a plurality of switches 1 so that the outputs of a plurality of driving means 52 are matched with detection capacity by the relation of the transmission line and the impedances 55-57 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a personal computer, a memory driving device and a memory module included therein.

[0002]

2. Description of the Related Art In recent personal computers, as the speed of CPUs and system buses increases, transmission line designs using advanced circuit technology are required. The key to transmission line design is to optimally combine the driving capability of the buffer circuit with the impedance on the transmission line. In this regard, in the memory circuit, since the electric load capacity changes as the user changes the memory capacity, a design corresponding to a wide impedance is required. Hereinafter, the design of a conventional memory circuit will be described with reference to FIG.

FIG. 3 is a block diagram showing a conventional memory circuit. In FIG. 3, reference numeral 51 indicates a conventional memory drive device. Inside the memory driving device 51,
A single buffer circuit 52 is provided as driving means. The output terminal of the buffer circuit 52 is connected to a transmission line 53, and the end of the transmission line 53 is branched into a plurality. Memory modules # 1 to #m (m = 2, 3, 4,...) Are connected to the respective branch ends of the transmission line 53 via the memory slots 54, respectively. Here, parasitic impedances such as 55 to 57 can be assumed at the ends of the transmission lines 51 connected to the memory modules # 1 to #m.

In this case, in the minimum configuration of the system to which only the memory module # 1 is connected, the parasitic impedance in the circuit is only the one indicated by reference numeral 55. On the other hand, when a memory module is added, another impedance 56
Appear, and a complicated distributed constant circuit is formed according to the expansion situation. In the design of such complex transmission lines,
An optimal impedance has been determined by using a circuit simulator or the like.

[0005]

However, in the above conventional example, since the output of the buffer circuit as the driving means is fixed, it is difficult to cope with a change in impedance caused by a change in memory capacity. However, there is a disadvantage that the design cannot be performed flexibly. For example, when a transmission path is designed in accordance with the maximum memory capacity, the driving capability of the buffer circuit is too large in a configuration with a small memory capacity, and there is a disadvantage that a waveform problem due to reflection on the transmission path easily occurs.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to improve the disadvantages of the prior art and, in particular, to provide a memory drive device capable of flexibly designing a transmission path to a memory module.
It is an object to provide a memory module and a personal computer.

[0007]

According to a first aspect of the present invention, there is provided a memory driving apparatus for driving a plurality of memory modules connected to a transmission line having a predetermined impedance. Have. In particular, a plurality of switches for providing the plurality of driving means and selectively enabling the outputs of the plurality of driving means,
Output control means for detecting the total capacity of the memory module connected to the transmission path and selectively connecting a plurality of switches so that the outputs of the plurality of driving means match the detected capacity in relation to the impedance of the transmission path; With the configuration.

According to a second aspect of the present invention, a plurality of driving means are connected to a transmission line in a ladder shape, and a plurality of switches are connected between output terminals of the plurality of driving means. I am taking it.

According to a third aspect of the present invention, the output control means detects the total capacity of the memory modules based on information on the memory capacity output from each memory module.

According to a fourth aspect of the present invention, the memory module is a memory module that can be attached to and detached from a transmission line, and outputs information of its own memory capacity to an external device for use in driving control of a memory module connected to the transmission line. It has the function to do.

According to a fifth aspect of the present invention, a transmission line having a constant impedance, a plurality of memory slots connected in parallel to one end of the transmission line for connecting a memory module, A plurality of driving means connected to the other end of the transmission path so that the connected memory module can be driven via the transmission path;
A plurality of switches for selectively enabling the outputs of the plurality of driving means; and a total capacity of a memory module connected to the transmission path, and detecting the outputs of the plurality of driving means in relation to the impedance of the transmission path. Output control means for selectively connecting a plurality of switches to match the capacity,
The configuration is adopted.

According to a sixth aspect of the present invention, there is provided a personal computer, comprising: a memory drive device according to the first or fifth aspect; an input device connection interface; an output device connection interface; The control CPU and the CPU are provided on a bus.

Thus, the above-mentioned object is achieved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
It will be described based on. The difference from the related art is that one buffer circuit is divided into a plurality of buffer circuits, switches for selectively enabling their outputs are provided, and output control means for turning on / off the switches are provided. That is, each memory module has a function of outputting information on the memory capacity.

In FIG. 1, a plurality of buffer circuits 52 as driving means are provided. Here, the driving capability of each buffer circuit is I1, I2,..., In (n = 3, 4,
5, ...). In addition, a plurality of switches 1 for selectively making the output valid are connected to the plurality of buffer circuits 52. Each switch 1 is provided with an output control means 2. The output control means 2 detects the total capacity of the memory modules # 1 to #m, and switches the plurality of switches 1 such that the driving capability of the plurality of buffer circuits 52 matches the detected capacity in relation to the impedance of the transmission line 53. It has a function to connect selectively.

In the present embodiment, the plurality of buffer circuits 52 are connected to the transmission line 53 in a ladder shape. The switches 1 are connected between the output terminals of the buffer circuits 52. The output control means 2 has a function of detecting the total capacity of the memory modules based on the information on the memory capacity output from each of the memory modules # 1 to #m. On the other hand, each of the memory modules # 1 to #m is a memory module that can be attached to and detached from the transmission line 53, and uses the information of its own memory capacity for driving control of the memory module connected to the transmission line 53. It has a function to output to the outside.

At the end of each branch of the branched transmission line 53,
Memory slots 3 for connecting the memory modules # 1 to #m are connected in parallel. Each memory slot 3 has a terminal for transmitting information on the memory capacity output from the memory modules # 1 to #m to the output control means 2. In FIG. 1, each of the memory modules # 1 to #
Although the information of the memory capacity output from m is illustrated as being collected on a single signal line and input to the output control means 2, the information is input to the output control means 2 via independent signal lines from each memory module. May be configured. Each switch 1 may be a relay switch or a semiconductor switch.

Next, the operation of this embodiment will be described.

When the entire device is set to the operating state, the memory modules # 1 to #
The information of the memory capacity is output from m and input to the output control means 2 via each memory slot 3. The output control means 2 calculates the total capacity of the memory based on the information on the memory capacity input from each of the memory modules # 1 to #m, and calculates the optimum driving capability of the entire buffer circuit based on the result. . And the output control means 2
The switch to be connected is selected so that the driving capability of the entire buffer circuit becomes the calculated optimal driving capability. Here, the calculation of the optimum driving capability and the selection of the switch to be connected for that can be performed by referring to a conversion table prepared based on actual measurement. For example, it is conceivable to record switch connection patterns corresponding to the information patterns of the memory capacities from the memory modules # 1 to #m in the conversion table.

Here, when no switch 1 is connected, only the buffer circuit having the driving ability I1 functions, but when one or more switches 1 are connected, some buffer circuits are connected to the memory modules # 1 to # 1. #M at the same time, and an appropriate current is driven. For example, when only the memory module # 1 is connected to the memory slot 3, the output control circuit 2 sets all the switches 1 to the disconnected state, and drives the memory module with the minimum driving capability I1. On the other hand, when m memory modules # 1 to #m are connected, the output control circuit 2 sets all the switches to the connected state, and sets I1 + I2 +.
The memory module is driven with the driving capability of.

According to this, the driving capability of the buffer circuit is optimally adjusted according to the total capacity of the memory module, so that the transmission line itself can be designed more flexibly than before.

Here, the present invention is not limited to the above embodiment. In FIG. 1, a plurality of switches 1
Are connected in series to the main line of the transmission line 53, but they may be connected in parallel to the main line of the transmission line 53. In this case, a switch can also be provided at the output stage of the buffer circuit (driving means) having the driving capability I1. The output control means 2 may increase the driving capability by gradually increasing the number of buffer circuits for enabling the output, or may sequentially switch the buffer circuits for enabling the output, similarly to the above embodiment. The driving ability may be increased by using the above. Of course,
Both may be used together. The same applies to the case where the driving capability is reduced. Further, although each buffer circuit is connected in a ladder shape, each buffer circuit may be connected in parallel to the main line of the transmission line 53 by an independent signal line branched from the main line of the transmission line.

In the above embodiment, each memory module may simply output a signal indicating that the memory module is being connected. In this case, the output control means is configured to detect the number of connected memories based on the signal indicating that the memory modules are being connected and output from each memory module, and to detect the total memory capacity as a result. For example, it can be adopted when the capacity of each connected memory module is fixed beforehand.

Next, another embodiment of the present invention will be described with reference to FIG.

The personal computer shown in FIG. 2 is a memory drive device 10 having the configuration shown in the previous embodiment.
And an input device connection interface 11, an output device connection interface 12, and a CPU 13 for controlling the calculation and input / output of data transmitted and received between these units. These elements are connected to the same bus 14, respectively. Memory modules # 1 to #m are connected to the memory driving device 10 as in the embodiment of FIG. In FIG. 2, reference numeral 15 indicates a memory module. The CPU 13 sends a control signal to the memory driving device 10 to drive the memory module 15 to write or read predetermined data. At this time, the memory driving device 10 drives the memory module 15 by the same operation as the previous embodiment. For example, the CPU 13 records data input from an input device connected to the input device connection interface 11 in the memory module 15. Also,
The CPU 13 operates by sequentially processing the programs read from the memory module 15. The CPU 13
Outputs the data read from the memory module 15 to an output device connected to the output device connection interface 12.

With this configuration, it is possible to provide a personal computer which can provide the same functions and effects as those of the above embodiment and can flexibly design a transmission line.

[0027]

The present invention is constructed and functions as described above. According to this, the driving capability of the driving means is optimally adjusted according to the total capacity of the memory module. This can be performed more flexibly and easily than before. This effect becomes greater as the transmission speed between the memory drive device and the memory module increases.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory drive device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a personal computer showing another embodiment of the present invention.

FIG. 3 is a circuit diagram of a memory drive device showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Switch 2 Output control means 3 Memory slot 10 Memory drive device 11 Input device connection interface 12 Output device connection interface 13 CPU 14 Bus 52 Buffer circuit (drive means) 53 Transmission path 55-57 Transmission path impedance # 1- # m Memory module

Claims (6)

[Claims] 1. A memory drive device comprising a drive unit for simultaneously driving an arbitrary number of memory modules connected to a transmission line having a predetermined impedance, wherein a plurality of the drive units are provided, and a plurality of the drive units are provided. A plurality of switches for selectively enabling outputs, and detecting a total capacity of a memory module connected to the transmission line, and matching outputs of the plurality of driving means with the detected capacitance in relation to an impedance of the transmission line. And an output control means for selectively connecting the plurality of switches. 2. The system according to claim 1, wherein said plurality of driving means are connected to the transmission line in a ladder shape, and said plurality of switches are connected between respective output terminals of said plurality of driving means. Memory drive. 3. The memory drive device according to claim 1, wherein said output control means detects a total capacity of the memory module based on information on a memory capacity output from each of said memory modules. 4. A memory module detachable from a transmission line, the memory module having a function of outputting information on its own memory capacity to the outside for use in drive control of a memory module connected to the transmission line. A memory module characterized by the following. 5. A transmission line having a constant impedance, a plurality of memory slots connected in parallel to one end of the transmission line for connecting a memory module, and a memory module connected to the memory slots. A plurality of driving means connected to the other end of the transmission path so as to be drivable via the transmission path, a plurality of switches for selectively enabling outputs of the plurality of driving means, Output control means for detecting the total capacity of the connected memory module and selectively connecting the plurality of switches so that the outputs of the plurality of driving means match the detected capacity in relation to the impedance of the transmission line; A memory drive device comprising: 6. A bus comprising: a memory drive device according to claim 1 or 5; an input device connection interface; an output device connection interface; and a CPU for controlling calculation and input / output of data transmitted and received between these units. A personal computer provided on top.