JP3266098B2 - Expansion slot connection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an expansion slot connection circuit, and more particularly to a method for connecting an expansion slot to a bus in a computer device having a predetermined total number of slots.

[0002]

2. Description of the Related Art Conventionally, in this type of computer, expansion cards are inserted due to restrictions on the hardware configuration of the computer, especially restrictions on the computer main body (mainly on the size of the housing). The total number of slots is determined.

A primary bus (Primary-bus: primary bus) and a secondary bus (Secondary-bus: secondary bus) are provided in a computer device.
In the case of controlling by an output processor, it is necessary to consider the number of slots connected to each of the primary bus and the secondary bus.

Although the control of the secondary bus by the IOP as described above has been conventionally used, in recent years, I ₂ O
(Intelligent I / O) technology is in the spotlight.

As described above, in the primary bus and the secondary bus, the controlling processor is a CPU (Cent).
ral Processing Unit)
Alternatively, if the IOPs are different, it is necessary to increase the number of slots of each bus depending on the purpose of use of the computer. There is no problem when the number of slots in each bus is sufficient, but there is a problem when the total number of slots is determined by the limitation of the computer main body (mainly, the limitation of the housing shape).

[0006]

The above-described conventional expansion slot connection method has a problem in that when the number of slots needs to be increased depending on the purpose of use of the computer, the hardware must be redesigned.

An object of the present invention is to solve the above-mentioned problems and to provide an expansion slot connection circuit capable of changing a slot configuration without changing the design of a housing and hardware.

[0008]

SUMMARY OF THE INVENTION An expansion slot connection circuit according to the present invention is connected to first and second buses respectively controlled by different control systems, and connects an electronic circuit to each of the first and second buses. look including a plurality of expansion slots for connecting to said first and second bus each Basuburi'
An expansion slot connection circuit for a computer device connected to a processor bus through a first bus switch for connecting a specific expansion slot of the plurality of expansion slots to the first bus; A second bus switch for connecting a specific expansion slot to the second bus;
And a bus selection means to enable one of said first and second bus switches according to an external instruction, the bus selection
The first and second bus switches which are made effective by the selector means
By switching, it is connected to each of the first and second buses.
The number of expansion slots is changed .

Another expansion slot connection circuit according to the present invention is controlled by different control systems, respectively, and is mutually first.
And a plurality of buses connected to each of the first and second buses and for connecting an electronic circuit to each of the first and second buses. and an expansion slot seen including, the first and second bus each
Is connected to the processor bus via the second bus bridge.
An expansion slot connection circuit for a computer device, comprising: a first bus switch for connecting a specific expansion slot among the plurality of expansion slots to the first bus;
Wherein comprises a second bus switch that connects a particular expansion slot to said second bus, and a bus selection means to enable one of said first and second bus switches according to an external instruction, wherein The first and the second to be effective by the bus selecting means
By switching the second bus switch, the first and second bus switches are switched.
Change the number of expansion slots connected to each bus
I am.

That is, in the expansion slot connection circuit of the present invention, the connection portion of the expansion slot in the computer main unit is connected to each of the primary bus and the secondary bus by the bus switch, and the switching operation by the bus switch is controlled by the bus selection circuit. I have.

More specifically, a bus bridge (Bus bridge)
bridge), and each bus has an expansion slot (Additiona).
In a computer hardware configuration having a lslot, a bus selection circuit (Bus Selector) and a bus switch (Bus Switch) are provided, and an expansion slot is connected to each bus through the bus switch.

This bus selection circuit provides a bus selection signal (Sel)
ect signal), switch the bus switch,
The operation of switching the bus to which the expansion slot connected under the bus switch is connected is executed. Therefore, a specific slot can be connected to a required one of the primary bus and the secondary bus as required.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an expansion slot connection circuit according to one embodiment of the present invention.
In the figure, a CPU (Central Processing Unit) 1 and a bus bridge 2 are connected to a processor bus 100, and bus bridges 2 and 3, a bus switch 4, and an expansion slot (Additional) are connected to a primary bus (Primary-bus: primary bus) 200. slots) 11 to 13 are connected to the secondary bus 300 (Secondary).
The bus bridge 3, the bus switch 5, and the expansion slots 15 to 17 are connected to -bus (secondary bus).

The bus bridge 2 is connected to the processor bus 100 and the primary bus 200, and can connect the CPU 1 on the processor bus 100 to the expansion slots 11 to 13 and the bus switch 4 on the primary bus 200.

The bus bridge 3 is a primary bus 200
And the secondary bus 300, the bus bridge 2 on the primary bus 200, and the expansion slots 11-1.
3. The bus switch 4 can be connected to the expansion slots 15 to 17 and the bus switch 5 on the secondary bus 300.

Here, the expansion slot 14 is connected to the primary bus 200 via the bus switch 4 and to the secondary bus 300 via the bus switch 5. The bus selection circuit 6 enables one of the bus switches 4 and 5 according to the selection signal 101.

Therefore, by instructing the bus selection circuit 6 with the selection signal 101 to connect the expansion slot 14 to the bus requiring the expansion slot 14, the expansion slot 14 can be connected to the primary bus 200 or the secondary bus 300. . Therefore, a specific slot, that is, the expansion slot 14 can be connected to a required one of the primary bus 200 and the secondary bus 300 as needed.

FIG. 2 is a block diagram showing a hardware configuration of a computer device according to another embodiment of the present invention.
In the figure, a CPU 1, a bus bridge 2, and a main memory controller 22 are connected to a processor bus 100, and a main memory 2 is connected to the main memory controller 22.
1 is connected.

The primary bus 200 has a bus bridge 2, a bus switch 4, expansion slots 11 to 13, and I / Os.
Controller 23, I / O bus bridge 24, bus bridge & IOP (Input Output Process)
Ssor) 25 is connected.

The secondary bus 300 has a bus switch 5, expansion slots 15 to 17, bus bridge & IOP2
5 and the I / O controller 29 are connected. I /
The O bus 400 includes a bus bridge & IOP 25, an IOP memory controller 26, and an IOP firmware (RO
M: read only memory) 28, and the IOP memory controller 26 is connected to an IOP memory 27.

The low-speed I / O bus 500 is connected to the I / O bus bridge 24, the expansion slots 18, 19, the I / O controller 30, and the buffer 31, and the buffer 31 is connected to the CPU firmware (ROM) 32. ing.

The bus bridge 2 is connected to the processor bus 100 and the primary bus 200, and is connected to the CPU 1 and the main memory controller 22 on the processor bus 100.
, A bus switch 4 on the primary bus 200, expansion slots 11 to 13, an I / O controller 23, an I / O
The bus bridge 24 and the bus bridge & IOP 25 can be connected.

The bus bridge & IOP 25 includes a primary bus 200, a secondary bus 300, and an I / O bus 40.
0, the bus bridge 2 on the primary bus 200, the bus switch 4, the expansion slots 11 to 13, I
The I / O controller 23, the bus switch 5 on the secondary bus 300, the expansion slots 15 to 17, the I / O controller 29, and the IOP memory controller 26 and the IOP firmware 28 on the I / O bus 400 can be connected.

The I / O bus bridge 24 is connected to the primary bus 200 and the low-speed I / O bus 500, and has a bus bridge 2, a bus switch 4, expansion slots 11 to 13, and an I / O controller 23 on the primary bus 200.
And expansion slots 18 and 1 on low-speed I / O bus 500
9, the IO controller 30, and the buffer 31 can be connected.

Here, the expansion slot 14 is connected to the primary bus 200 via the bus switch 4 and to the secondary bus 300 via the bus switch 5. The bus selection circuit 6 enables one of the bus switches 4 and 5 according to a selection signal from the selection switch 33.

Therefore, by instructing the bus selection circuit 6 from the selection switch 33 to connect the expansion slot 14 to the bus requiring the expansion slot 14, the expansion slot 14 can be connected to the primary bus 200 or the secondary bus 300. . Therefore, a specific slot, that is, the expansion slot 14 is allocated to the primary bus 200 as necessary.
And the secondary bus 300 can be connected to a required one.

In another embodiment of the invention described above, the IOP
Bridge and IOP with integrated bus bridge
25 are arranged, but they may be separated. The CPU 1 has a main memory 2 for the CPU.
1 and RO containing firmware (FW) for CPU
M32 and bus bridge & IOP25 have I
OP memory 27 and ROM with firmware
28 are prepared, and each bus (primary bus 200, secondary bus 300, low-speed I / O bus 5
00) are connected to I / O controllers 23, 29 and 30.

The I / O controllers 23 and 29 and the expansion slots 11 to 13 and 15 to 17 connected to the primary bus 200 and the secondary bus 300 shown in FIG. Connectable I / O expansion board (Additi
An internal board (not shown) can also be connected to the secondary bus 300.

However, the positions of the primary bus 200 and the secondary bus 300 are different from each other in that the primary bus 200 is controlled by the CPU 1 and the secondary bus 300 is controlled by the IOP 25.

With respect to the above-mentioned hardware configuration, the expansion slot 14 provided according to another embodiment of the present invention is controlled by the bus switches 4 and 5 selectively controlled by the bus selection circuit 6 so that the primary bus 200 and the secondary bus 3 are switched.
00 is connected to the selected bus.

In the above-described configuration, the primary bus 200 and the IOP
25, which expansion slot is required, and the selection switch 3
Switch 3

At this time, if it is switched to the primary bus 200 side, the bus selection circuit 6 switches the secondary bus 3 on the opposite side of the bus switched by the selection switch 33.
00 bus switch 5 is disabled (disab
After that, the bus switch 4 on the primary bus 200 side is enabled.

Bus switch 5 on the disabled side
Separates all signals supplied to the expansion slot 14 from the expansion slot 14. The enabled bus switch 4 connects all signals to the expansion slot 14.

As described above, the expansion slot 1 is limited by the limitation of the main body of the computer (mainly, the limitation of the dimensions of the housing, etc.)
If the total number of 1 to 19 is determined, C
When it is desired to increase the number of expansion slots of either the primary bus 200 or the secondary bus 300 controlled by different processors PU1 and IOP25, respectively, the expansion slot 14 is connected to the side of the primary bus 200 and the secondary bus 300 that has a connection request. It is possible to do.

Therefore, it is possible to increase the required number of expansion slots on the bus side. Therefore, the configuration of the number of expansion slots can be adjusted without changing the housing or changing the design of the logic board.

FIG. 3 is a block diagram showing a hardware configuration of a computer according to another embodiment of the present invention.
In the figure, a CPU 1, a bus bridge 2, and a main memory controller 22 are connected to a processor bus 100, and a main memory 2 is connected to the main memory controller 22.
1 is connected.

The primary bus 200 includes a bus bridge 2, a bus switch 4, a bus selection circuit 6, and an expansion slot 1.
1 to 13, an I / O controller 23, an I / O bus bridge 24, and a bus bridge & IOP 25 are connected.

The secondary bus 300 has a bus switch 5, expansion slots 15 to 17, a bus bridge & IOP2
5 and the I / O controller 29 are connected. I /
The O bus 400 includes a bus bridge & IOP 25, an IOP memory controller 26, and an IOP firmware (RO
M) 28 and the IOP memory controller 26
Is connected to an IOP memory 27.

The low-speed I / O bus 500 is connected to the I / O bus bridge 24, the expansion slots 18, 19, the I / O controller 30, and the buffer 31, and the buffer 31 is connected to the CPU firmware (ROM) 32. ing.

The bus bridge 2 is connected to the processor bus 100 and the primary bus 200, and is connected to the CPU 1 and the main memory controller 22 on the processor bus 100.
Bus switch 4, bus selection circuit 6, expansion slots 11 to 13, I / O controller 23, I / O bus bridge 24, bus bridge & I on primary bus 200
OP25 can be connected.

The bus bridge & IOP 25 includes a primary bus 200, a secondary bus 300, and an I / O bus 40.
0, the bus bridge 2 on the primary bus 200, the bus switch 4, the bus selection circuit 6, the expansion slots 11 to 13, the I / O controller 23, the bus switch 5 on the secondary bus 300, and the expansion slots 15 to 15.
17, the I / O controller 29 can be connected to the IOP memory controller 26 and the IOP firmware 28 on the I / O bus 400.

The I / O bus bridge 24 is connected to the primary bus 200 and the low-speed I / O bus 500, and has a bus bridge 2, a bus switch 4, a bus selection circuit 6, expansion slots 11 to 13, and I on the primary bus 200. / O
Controller 23, expansion slots 18 and 19 on low-speed I / O bus 500, IO controller 30, buffer 3
1 can be connected.

Here, the expansion slot 14 is connected to the primary bus 200 via the bus switch 4 and to the secondary bus 300 via the bus switch 5. The bus selection circuit 6 enables one of the bus switches 4 and 5 according to a selection signal on the primary bus 200.

Therefore, by outputting a selection signal on the primary bus 200 to instruct the bus selection circuit 6 to connect to the bus requiring the expansion slot 14,
The expansion slot 14 can be connected to the primary bus 200 or the secondary bus 300. Therefore,
A specific slot, that is, an expansion slot 14 is allocated to the primary bus 200 and the secondary bus 300 as necessary.
Can be connected to the required one.

In another embodiment of the present invention, the basic configuration is as described above, but the bus selection circuit 6 is connected to the primary bus 200, and a bus switching register (not shown) is connected to the bus selection circuit 6. It is also possible to prepare and switch the bus by writing to the switching register.

As described above, in another embodiment of the present invention, the bus can be switched by software control. Therefore, dynamic switching of the expansion slot in a computer equipped with a plug-and-play OS (operating system) can be performed. Can be.

As described above, the primary bus 20 connected by the bus bridge 3 or the bus bridge & IOP 25
0 and the secondary bus 300 have expansion slots 11 respectively.
In the computer hardware configuration having ~ 19,
A bus selection circuit 6 and bus switches 4 and 5 are provided.
And the bus selection circuit 6 switches the bus switches 4 and 5 in accordance with the bus selection signal, and switches the bus to which the expansion slot 14 connected below the bus switches 4 and 5 is connected, so that a specific expansion slot is connected. 14 can be connected to the primary bus 200 or the secondary bus 300 as required.

[0048]

As described above, according to the present invention, an electronic circuit is connected to each of the first and second buses and is connected to each of the first and second buses respectively controlled by different control systems. Bus device for connecting a specific expansion slot of the plurality of expansion slots to a first bus, and connecting a specific expansion slot to a second bus. By making any one of the second bus switch valid according to an external instruction, there is an effect that the slot configuration can be changed without changing the design of the housing and the hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an expansion slot connection circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a hardware configuration of a computer device according to another embodiment of the present invention.

FIG. 3 is a block diagram illustrating a hardware configuration of a computer device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2,3 Bus bridge 4,5 Bus switch 6 Bus selection circuit 11-19 Expansion slot 21 Main memory 22 Main memory controller 23,29,30 I / O controller 24 I / O bus bridge 25 Bus bridge & IOP 26 IOP memory Controller 27 IOP memory 28 IOP firmware 31 Buffer 32 CPU firmware 33 Selection switch

Claims (6)

(57) [Claims] 1. A saw including a plurality of expansion slots for connecting the first and second are connected to a bus respectively and the electronic circuits which are respectively controlled by the first and second bus each by a different control system, Each of the first and second buses is a bus bridge.
An expansion slot connection circuit for a computer device connected to a processor bus through a first bus switch for connecting a specific expansion slot of the plurality of expansion slots to the first bus; A second bus switch for connecting a specific expansion slot to the second bus;
Possess a bus selection means to enable one of said first and second bus switches according to an external instruction, the bus selection
The first and second bus switches which are made effective by the selector means
By switching, it is connected to each of the first and second buses.
An expansion slot connection circuit, wherein the number of expansion slots is changed . 2. An output unit for outputting an instruction signal for instructing which one of the first and second buses to connect the specific expansion slot to the bus selection unit in response to an external instruction. The expansion slot connection circuit according to claim 1, wherein 3. The bus selection unit according to claim 2, wherein said bus selection unit is configured to enable one of said first and second bus switches in response to an instruction signal output to said first bus and connected to said first bus. 2. The expansion slot connection circuit according to claim 1, wherein the expansion slot connection circuit is configured as described above. 4. First and second buses respectively controlled by different control systems and connected to each other via a first bus bridge, and an electronic circuit connected to each of the first and second buses and having an electronic circuit. look including a plurality of expansion slots for connecting to said first and second bus respectively, the first and second
Are connected to the processor bus via the second bus bridge.
An expansion slot connection circuit of a computer device connected to a first bus switch for connecting a specific expansion slot of the plurality of expansion slots to the first bus; a second bus switch that connects to the second bus, possess a bus selection means to enable one of said first and second bus switches according to an external instruction, effective in the bus selection means And said
By switching the first and second bus switches, the first bus is switched.
And change the number of expansion slots connected to the second bus each to
An expansion slot connection circuit characterized in that: 5. An output unit for outputting to the bus selection unit an instruction signal for instructing which of the first and second buses the particular expansion slot is connected to in response to an external instruction. The expansion slot connection circuit according to claim 4, wherein 6. The bus selecting means enables one of the first and second bus switches in response to an instruction signal connected to the first bus and output to the first bus. The expansion slot connection circuit according to claim 4, wherein the expansion slot connection circuit is configured as described above.