JPH04134552A - System bus control system - Google Patents

Abstract

PURPOSE:To miniaturize a device and to improve reliability by providing a bus switch control communication line, bus defect detecting means, auxiliary bus line and signal line switching circuit. CONSTITUTION:This device is equipped with a bus switch control communication line 11 to connect plural devices 13-18, a bus defect detection circuit 12 to detect the defect of a system bus 1 and to output a prescribed control signal to the bus switch control communication line 11, and an auxiliary bus line 10 composed of signal lines less than the number of signal lines constituting the system bus 1. Further, a signal line switching circuit 20 is provided to connect the signal lines in the devices 13-18, which are connected to the signal lines constituting the system bus 1, and the signal lines constituting the auxiliary bus line 10 based on the control signal applied through the bus switch control communication line 11. Thus, the device can be miniaturized, reliability can be improved and energy consumption can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a system bus control method for a device equipped with a microprocessor, and more particularly to a system bus control method for increasing the reliability of the system bus. be.

[Conventional technology]

Conventionally, devices equipped with microprocessors and the like require high reliability, so if the device needs to continue operating without shutting off the power even if a failure occurs, the configuration of the device must be changed. A method was adopted in which two systems of elements were provided and the system bus was also duplicated. An example of such a device is shown in FIG. The basic components of this device are a main CPU that performs major control and calculations, a processor that controls input and output devices, and memory that stores various control information and processing and calculation results. In order to do this, main CPU A3,10 processor A4. Memory A5, main CPU B6,10 processor B7. A memory B8 is provided, and these are connected to a dual system bus, that is, a system bus A1 and a system bus B2, respectively. Each component 3 to 8 includes a fourth
As shown in the figure, a bus selector 9 is provided to select the signal line to be connected to the system bus in each element from the system bus A1.
or system bus B2. And while using system bus A1,
When a failure occurs in one or more signal lines constituting the system bus A1, the path selector 9 switches the system bus to be used to the system bus B2.

Note that the output stage of the system selector 9 is provided with a drive circuit for driving the system bus A1 and a drive circuit for driving the system bus B2. Further, each component is usually configured by mounting parts on a printed wiring board, and is connected to the system bus through connection terminals provided on the board.

[Problem to be solved by the invention]

As described above, in the conventional type of apparatus, the reliability of the apparatus is improved by simply providing two system buses, and therefore, there are the following drawbacks.

(1) The total number of signal lines constituting the system bus is doubled, which is disadvantageous for downsizing the device.

(2) Since the number of terminals for connecting each component to the system bus is doubled, this is disadvantageous for miniaturizing the device and also reduces reliability.

(3) Since the number of circuits for driving the system bus is doubled, the power consumption increases. Furthermore, since this is a portion with large power consumption, it is difficult to implement it into an LSI, which is disadvantageous for miniaturizing the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system bus control method that eliminates these drawbacks and allows devices to be made smaller, have higher reliability, and lower power consumption.

[Means to solve the problem]

The present invention provides a control method for a system bus that connects a plurality of devices including a CPU, which includes: a bus switching control communication line that connects the plurality of devices; a defect in the system bus is detected and a predetermined control signal is transmitted to the bus Each of the devices is equipped with a bus defect detection means for outputting to a switching control communication line, an auxiliary bus line constituted by a number of signal lines smaller than the number of signal lines constituting the system bus, and the system bus is a signal line switching circuit that connects a signal line in the device to be connected to the constituent signal line and a signal line forming the auxiliary bus line based on the control signal given through the bus switching control communication line; It is characterized by providing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a device constructed based on the system bus control method of the present invention. The basic components of this device are the main C
PU, the ■0 processor that controls input/output devices, and the memory that stores each control information, processing and calculation results, etc. In order to have two systems, the main CPU1
3. I0 processor A14, memory A15, and main C
A PUB 16, an IO processor B17, and a memory 81B are provided. These components 13 to 18 are each connected to a system bus A1 composed of address lines, data lines, control lines, and the like. Incidentally, since the system bus A is the same as the system bus A shown in FIG. 3, the same number is given to it. This device further includes an auxiliary bus line 1O configured with a smaller number of signal lines than the number of signal lines configuring the system bus A1, and a bus switching control communication line 11. It is connected to a bus line 10 and a control communication line 11, respectively.

The bus defect detection circuit 12 is connected to the system bus A1, the bus switching control communication line 11, and the auxiliary bus line 10,
Together with the main CPU, B13.16, or any of the 10 processors ASB14.17, it detects the defective part of the system bus A1, identifies the signal line to be switched on the system bus A1, and transfers the control signal to the control communication line 11. Output to.

As shown in FIG. 2, each component 13 to 18 is provided with a buffer circuit 19 and a signal line switching circuit 20, respectively. The buffer circuit 19 connects the signal line to be connected to the system bus A1 in each component and the system bus A1, and connects the signal line switching circuit 20 from the system bus A1.
It is provided to eliminate the impact on The signal line switching circuit 20 switches the signal line in each component connected to the defective signal line of the system bus A1 to an auxiliary bus based on a control signal given from the bus defect detection circuit 12 through the bus switching control communication line 11. Connect to line 10 signal line.

Next, the operation will be explained. The bus defect detection circuit 12 is the main C
PUA, B13, 16 or 107”
Either of the 0-fr connectors A and B14.17 constantly detects a defective location on the system bus A1, and when a defect is detected and the signal line to be switched on the system bus A1 is identified, a control signal is sent to the control communication line 11. Output. Upon receiving this control signal, the signal line switching circuit 2 of each component 13 to 1B switches the signal line in each component connected to the defective signal line of the designated system bus A1 to the auxiliary bus line. 1
Connect to the 0 signal line. As a result, each component can send and receive signals through the newly connected signal line of the auxiliary bus line 10 instead of the signal line of the failed system bus A1, and the device can operate normally. becomes.

Note that when a system bus failure occurs, it is extremely rare for all of the signal lines that make up the system bus to fail at the same time, and in most cases, some of the signal lines that make up the system bus fail. be.

Further, failures in each signal line are often caused by failures in the interface between the system bus and each device. Therefore, the number of signal lines forming the auxiliary bus line can be made smaller than the number of signal lines of the system bus. The number of signal lines that make up the auxiliary bus line is determined by predicting the reliability of the system bus.If the reliability is expected to be high, fewer signal lines may be needed, and conversely, if the reliability is expected to be low, need to do more.

Additionally, when switching the system bus to an auxiliary bus line, it is also possible to divide the system bus signal lines into blocks, and when a failure occurs in a signal line, all signal lines in the block including that signal line are switched. . In this case, the configuration of the device becomes simple, which is advantageous in terms of miniaturization of the device, lower power consumption, and number of terminals connecting each component to the system bus. However, in terms of reliability, the method of switching for each failed signal line as in this embodiment is the best.

〔Effect of the invention〕

As explained above, the present invention provides a control system for a system bus that connects a plurality of devices including a CPU. A bus failure detection means for outputting a signal to the bus switching control communication line, an auxiliary bus line composed of a number of signal lines smaller than the number of signal lines constituting the system bus, and each device is equipped with the device, and the system bus is A signal line switching circuit is provided that connects a signal line in the device to be connected to the constituent signal line and a signal line forming the auxiliary bus line based on a control signal given through a bus switching control communication line.

Therefore, according to the present invention, (1) the number of signal lines constituting the system bus including auxiliary bus lines can be reduced, making it possible to downsize the device;

(2) Since the number of terminals for connecting each component to the system bus can be reduced, the device can be made smaller and reliability can be improved.

(3) Since the circuit for driving the system bus can be reduced, power consumption can be reduced, and since it is a part that consumes a large amount of power, its reduction makes it easier to integrate into an LSI, making it easier to miniaturize the device.

[Brief explanation of drawings]

Is Fig. 1 a system bus system according to the present invention? A block diagram showing an example of a device configured based on the H method, FIG. 2 is a block diagram showing an example of a device configured based on a conventional system bus control method, and FIGS. 3 and 4 show conventional technology. It is a block diagram. 1...System bus A 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, ・Auxiliary bus line・Bus switching control communication line・Bus defect detection circuit・Main CPU・10 Processor A ・Memory A ・Main CPUB ・10 Processor B ・Memory B ・Buffer circuit/Signal line switching circuit

Claims (1)

[Claims] (1) A control method for a system bus that connects a plurality of devices including a CPU, including a bus switching control communication line that connects the plurality of devices, and detecting a defect in the system bus and transmitting a predetermined control signal to switch the bus. A bus failure detection means for outputting to a control communication line, and an auxiliary bus line constituted by a number of signal lines smaller than the number of signal lines constituting the system bus, and each of the devices is equipped to constitute the system bus. a signal line switching circuit that connects a signal line in the device to be connected to a signal line that is to be connected to a signal line that constitutes the auxiliary bus line based on the control signal provided through the bus switching control communication line; A system bus control method characterized by: