KR100356514B1 - Baseboard circuit - Google Patents

Abstract

The present invention relates to a baseboard circuit, and the input / output module mounted on the baseboard is connected to the outside and is affected by electrical disturbance, which may cause a malfunction of itself and a path through which the disturbance is transmitted to the bus on the baseboard. Sometimes. For this reason, a filter is installed at the bus interface in the module, which affects the speed of the common bus. Accordingly, the CAPI module also needs to slow down the access speed according to the maximum signal delay, so that a large amount of time is required when receiving a large amount of data between the CPI modules, thereby reducing the control speed of the entire system. Accordingly, the present invention provides a transmission speed of each bus between a high speed unit that enables high-speed data transmission by grouping modules that require high speed, such as a CPI module, and a low speed unit that transmits data at low speed, such as an input / output module. In order to prevent the failure due to the difference, the high speed part and the low speed part are separated into circuits, and a bus buffer part made up of a buffer for buffering and transmitting control signals, address signals, and data between the high speed part and the low speed part, respectively, is configured. Therefore, when using the high speed module and the low speed module together on one board, the effect of the low speed module does not affect the high speed module so that high speed and large capacity data can be received without degrading the performance of the high speed module.

Description

Baseboard Circuitry {BASEBOARD CIRCUIT}

The present invention relates to a baseboard for mounting various functional modules in a system configuration, and more particularly, to a baseboard circuit suitable for high speed and dual function buses.

Systems that can be used with various functional modules provide a baseboard for mounting the modules.

On this baseboard, a common line (bus) for exchanging information between modules as shown in Fig. 1; Connectors 1 are provided for allowing each module to be connected to a common line.

At this time, the bus is provided as a standard, but companies that provide industrial control systems usually use a dedicated bus because of inadequate price or function, and in particular, a method different from the standard bus is used in terms of reliability. .

Conventional baseboards provide several slots for mounting functional modules and the bus timing is constant when accessing each module.

This timing is designed to take into account the load when modules are installed in all slots. The buses provided as a standard specify the maximum load for each module, and the designer of the module must design the module accordingly.

In the case of constructing a bus by itself, a filter (HF) is used as shown in FIG. 2 to increase the coping ability against electric disturbance. In this case, as shown in FIG. 3, an additional dedicated bus SB may be further provided to increase access speed between modules that need to exchange large amounts of data or access at high speed.

In general, a system composed of a baseboard is composed of a master module (usually a CPU module) that manages and uses a bus as shown in FIG. 4 and an input / output module in which data in the module is simply read or written by the master module. The bus is commonly connected to all modules with the same wiring.

Here, the power supply module 10 supplies power to all modules mounted on the baseboard, and each input / output module 30a to 30e is data of a form that the CPI module can process external switches, sensors, and analog signals. On the contrary, it converts the result value output from the process of control operation of CPI into a strong, pulse or analog signal that can be received by an external actuator.

Next, the CPI module 20a to 20d performs a control operation according to the written program. At this time, the state of the external input is required by accessing the data of the I / O module through the common bus, and the operation result is again inputted and output through the common bus. The external device is controlled by transmitting to the module.

In addition, there may be several CPI modules or large-capacity data processing modules as described above, and may receive data through a common bus according to mutual needs.

However, the input / output module mounted on the baseboard is connected to the outside and is affected by the electric disturbance, which may cause a malfunction of itself or a path through which the disturbance is transmitted to the bus on the baseboard. For this reason, a filter is installed at the bus interface in the module, which affects the speed of the common bus.

5 is a waveform diagram showing an example of signal delay when an I / O module with a built-in filter is mounted, and when 0, 1, 2, 3, and 4 I / O modules are mounted, respectively, the signal diagrams are 0, 1, 2, 3, respectively. Since the CPI module needs to slow down the access speed according to the maximum signal delay, it takes a lot of time to receive a large amount of data between CPI modules, resulting in a decrease in the control speed of the entire system.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems. When the high speed module and the low speed module are used together on one board, the effect of the low speed module does not affect the high speed module. Its purpose is to provide a baseboard circuit that can receive large amounts of data at high speed without compromising performance.

1 is an exemplary view showing the shape of a general baseboard.

2 is a block diagram showing an interface relationship between a bus of a baseboard and a function module;

3 is a block diagram showing a relationship between a bus and a function module when adding a dedicated bus for high-speed access.

4 is a block diagram showing a connection relationship between a plurality of function modules and a bus when a system is constructed by a baseboard.

5 is a waveform diagram showing an example of signal delay according to an increase in an input / output module.

Figure 6 is a block diagram showing an example of the circuit configuration of the baseboard according to the present invention.

Figure 7 is a block diagram showing an embodiment of a redundancy system configured by applying the present invention.

*** Description of the symbols for the main parts of the drawings ***

100: bus buffer unit 200: redundancy module

The present invention for achieving the above object, between the high-speed unit to enable high-speed data transfer to a group that requires high speed, such as CPI module, and a low-speed unit that performs data transmission at a low speed, such as input and output modules In order to prevent the failure caused by the difference in transmission speed of each bus, the circuit consists of a buffer that separates the high speed part and the low speed part, and buffers and transmits control signals, address signals, and data that travel between the high speed part and the low speed part, respectively. It is characterized by including a bus buffer unit.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

Figure 6 is a block diagram showing an example of the circuit configuration of the baseboard according to the present invention, a high speed unit to enable high-speed data transfer to a group of modules that require high speed, such as CPI modules (20a to 20d), The bus buffer unit 100 further includes a bus buffer unit 100 that prevents a failure due to a difference in transmission speeds of the respective buses between the low speed units that transmit data at low speed, such as the input / output modules 30a to 30f.

Referring to the operation of the present invention configured as described above are as follows.

First, each bus (control signal bus, address bus, data bus, etc.) is connected to the bus of the high speed part and the bus of the low speed part via the bus buffer part 100.

Therefore, the CUP module 20a to 20d connected to the high speed unit can be accessed at high speed. When the CPI module 20a to 20d accesses the input / output module 30a to 30f, the bus buffer unit 100 is opened. It is accessed through the low speed bus.

In addition, since the disturbance of the common bus by the I / O module of the low speed part is blocked by the bus buffer part 100 during the bus access of the high speed part, there is no obstacle.

High-speed modules represented by CPI module adjust access speed by applying different weight when CPI module and I / O module are accessed.

In addition, at a high speed bus access, the bus buffer is disabled and operates to transfer a signal to the low speed bus only during a low speed bus access. [0030] The operation according to an embodiment of the present invention will be described in more detail. Although not specifically shown, the unit 100 may be composed of three buffer circuits: a control signal bus buffer, an address bus buffer, and a data bus buffer. Each buffer circuit may include a switching element such as a transistor, or the like. In this case, the control signal bus buffer and the address bus buffer are unidirectional buffers. The enable terminal (not shown) is an inverting terminal connected to ground, and an input terminal is provided. The terminal (not shown) is connected to the high speed part and the output terminal (not shown) is connected to the low speed part. Therefore, the control signal data (rear) is always enabled. / Write command, etc.) is transmitted from the high speed unit to the low speed unit only via the control signal bus buffer, and address data is transmitted only from the high speed unit to the low speed unit via the address bus buffer. The enable terminal is connected only to the low speed part and is enabled only when a ready signal (a response signal indicating that control signal data and address data from the high speed part has been correctly received, also known as an acknowledgment signal) is received from the low speed part input / output module. For example, the data bus buffer is a buffer that is enabled only when a ready signal is received from the low speed I / O module. Thus, the ready signal is received from the low speed I / O module at the enable terminal of the data bus buffer. Can be used to transfer data from the low speed unit to the high speed unit and vice versa. I.e. when communication between ssipiyu communication module does not have available for the low-speed unit is ready signal from the low-speed input and output parts of the module are not being transmitted to the enable terminal of the buffer between the data bus, a two-way communication via the buffer data bus is cut off.

Figure 7 is a block diagram showing an embodiment of a redundancy system configured by applying the present invention, in which two systems are installed on a single baseboard in duplicate to form a redundancy system in the middle for exchanging data between the two systems. It is further provided with a duplication module 200 that serves as a medium.

Of course, even at this time, since each system includes a module (CPI module) operating at a high speed and a module (communication module, an expansion module) operating at a low speed, the bus buffer units 100a and 100b according to the present invention between the respective buses. By separating the high speed and the low speed bus by inserting a), the effect of the low speed module of the high speed module is minimized. For convenience of explanation, another embodiment will be described. Promised by the code of digital 1 and 0 which separates the parts, the buffer has two enable terminals respectively connected to the high speed part and the low speed part, and is disabled when a code signal of 1 designating the high speed part is received from the high speed part. When the 0 code signal specifying the low speed part is received from the high speed part, it is enabled. If the cable is, the code signal of one high-speed specifying unit from the low speed reception unit may be configured to be enabled.

As described above, when the high speed module and the low speed module are used together on one board, the baseboard circuit of the present invention prevents the influence of the low speed module from reaching the high speed module so that high speed and large capacity data can be obtained without degrading the performance of the high speed module. It has the effect of being able to pass.

Claims (2)

In constructing a system by mounting several functional modules having various characteristics on one board, such as a high speed unit that enables high-speed data transmission by using a module requiring high speed, such as a CPI module, and an input / output module. In order to prevent the fault caused by the difference in the transfer speed of each bus between the low speed parts where data is transmitted at low speed, the control signal, the address signal, and the data between the high speed part and the low speed part are separated in a circuit. A baseboard circuit comprising a bus buffer comprising a buffer for transmitting each buffered. The bus buffer unit of claim 1, wherein the bus buffer unit is transmitted from the high speed unit to the low speed unit by the control signal and the address signal buffer, and the data buffer is enabled when data transfer is performed from the low speed unit to the high speed unit or vice versa. And disabling the communication unit between the high speed unit and intercepting the communication path between the high speed unit and the low speed unit.