JPH11233543A - Forming method for bump and electronic part with bump - Google Patents
Forming method for bump and electronic part with bumpInfo
- Publication number
- JPH11233543A JPH11233543A JP10030733A JP3073398A JPH11233543A JP H11233543 A JPH11233543 A JP H11233543A JP 10030733 A JP10030733 A JP 10030733A JP 3073398 A JP3073398 A JP 3073398A JP H11233543 A JPH11233543 A JP H11233543A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- bumps
- ball
- wire
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子などの
電子部品を基板など他の電子部品にの電気的に接続する
場合に使用されるバンプを形成する方法、及びそのバン
プを形成した半導体素子などの電子部品に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a bump used when an electronic component such as a semiconductor device is electrically connected to another electronic component such as a substrate, and a semiconductor device having the bump formed thereon. For electronic components such as.
【0002】[0002]
【従来の技術】現在、ICチップなどの半導体素子を各
種の基板などに電気的に接続する場合には、半導体素子
の電極バッドと外部電極との間を金線などのボディング
ワイヤで接続するワイヤボンディング方式が主に用いら
れている。2. Description of the Related Art At present, when a semiconductor element such as an IC chip is electrically connected to various substrates or the like, an electrode pad of the semiconductor element and an external electrode are connected by a bonding wire such as a gold wire. The wire bonding method is mainly used.
【0003】しかし、近年における半導体デバイスの小
型化や薄型化の要求に応えるためには、デバイス内部の
限られたスペースに、より多くの素子や回路を設ける必
要があるため、ボディングワイヤを張り渡すワイヤボン
ディング方式の限界が指摘されている。However, in order to meet the recent demand for smaller and thinner semiconductor devices, it is necessary to provide more elements and circuits in a limited space inside the device. The limitations of the passing wire bonding method are pointed out.
【0004】そこで、ワイヤボンディングに代わる接続
方法として、半導体素子の電極バッド上に金属の突起物
(バンプ)を形成し、このバンプに外部電極を接続する
方法が知られている。このバンプによる接続方法によれ
ば、ボディングワイヤを用いることなく、対向させた電
極パッドと外部電極をバンプを介して直接接続すること
ができるので、素子や回路の高密度化が可能となる。Therefore, as a connection method instead of wire bonding, a method of forming a metal projection (bump) on an electrode pad of a semiconductor element and connecting an external electrode to the bump is known. According to this connection method using bumps, the opposed electrode pads and external electrodes can be directly connected via the bumps without using a boding wire, so that the density of elements and circuits can be increased.
【0005】上記のごとくバンプを形成した半導体素子
は、バンプを各種基板などの外部電極と対向させ、加圧
接続することにより実装される。例えば、TAB(Tape
Automated Bonding)方式ではフィルムキャリアに実装
され、フリップチップ方式ではプリント基板やガラス基
板に実装される。[0005] The semiconductor element having the bumps formed thereon as described above is mounted by pressing the bumps to external electrodes such as various substrates and connecting them under pressure. For example, TAB (Tape
In the case of the Automated Bonding method, it is mounted on a film carrier, and in the case of the flip chip method, it is mounted on a printed circuit board or a glass substrate.
【0006】また、半導体素子にバンプを設けるのでは
なく、上記の各種基板やフィルムキャリア、あるいはフ
レキシブルプリント回路などにバンプを形成し、これに
半導体素子の電極パッドを接続することも行われてい
る。Also, instead of providing bumps on a semiconductor element, bumps are formed on the above-mentioned various substrates, film carriers, flexible printed circuits, or the like, and electrode pads of the semiconductor element are connected to the bumps. .
【0007】[0007]
【発明が解決しようとする課題】上記したバンプによる
半導体素子などの実装であっても、近年の高密度化ある
いは多ピン化の進行に伴って、安定した実装が困難にな
る傾向にある。Even with the mounting of semiconductor elements and the like using bumps as described above, stable mounting tends to become difficult with the recent progress of higher density and more pins.
【0008】即ち、フィルムキャリアや基板などの平坦
度にバラツキがあったり、傾きや反りなどが発生した場
合、バンプ高さが低いと、電極パッドとフィルムキャリ
アや基板などの全体を接合に必要な荷重で加圧すること
ができない。このため、多数のバンプの中に、部分的に
接合不良が発生しやすかった。That is, when the flatness of the film carrier or the substrate is uneven, or the inclination or warpage occurs, if the bump height is low, the electrode pad and the entire film carrier or the substrate are required for bonding. Cannot be pressurized by load. For this reason, it is easy for partial bonding failure to occur in many bumps.
【0009】また、近年の多ビン化によりパッドのピッ
チが一層狭くなる傾向にあり、これに伴ってバンプもよ
り小さく制御する必要がある。しかし、バンプを小さく
するほど、接続すべき電極パッドと外部電極の間の間隔
に余裕がなくなるため、バンプによる実装が非常に難し
くなる傾向にある。Further, the pitch of pads tends to be narrower due to the recent increase in the number of bins, and accordingly, it is necessary to control the bumps to be smaller. However, as the size of the bump is reduced, the space between the electrode pad to be connected and the external electrode becomes smaller, so that mounting with the bump tends to be very difficult.
【0010】本発明は、このような従来の問題点を解決
すべくなされたものであり、フィルムキャリアや基板な
どの平坦度にバラツキがあったり、傾きや反りが発生し
た場合でも、部分的な接合不良を起こさずに安定した接
合ができ、しかも狭パッドピッチ化によるバンプの小型
化に対応でき、バンプによる実装が容易で歩留り向上を
達成できるバンプの形成方法を提供するものである。The present invention has been made in order to solve such a conventional problem, and even if the flatness of a film carrier, a substrate, or the like is varied, or if a tilt or a warp occurs, a partial area of the film carrier or a substrate is generated. An object of the present invention is to provide a bump forming method capable of performing stable bonding without causing a bonding defect, and being able to cope with miniaturization of bumps by narrowing the pad pitch, easily mounting with bumps, and improving yield.
【0011】[0011]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、電子部品の電気的接続に用いるバンプの
形成方法において、電子部品の導体部上に第1のバンプ
を形成し、引き続いて該第1のバンプの上に第2のバン
プを重ねて形成することを特徴とするバンプの形成方法
を提供するものである。In order to achieve the above object, the present invention provides a method for forming a bump used for electrical connection of an electronic component, wherein a first bump is formed on a conductor portion of the electronic component. And forming a second bump on the first bump by stacking the second bump on the first bump.
【0012】上記バンプの形成方法の一例としては、ボ
ールボンディング用ワイヤボンダーを用いて、そのキャ
ピラリーに移送されたワイヤの先端を加熱溶融してボー
ルを形成し、キャピラリーを下降させて該ボールを電子
部品の導体部上に当接させ、荷重と超音波を印加して該
導体部上に第1のバンプを形成した後、同様にして該第
1のバンプの上に第2のバンプを重ねて形成する。As an example of the method of forming the bump, a ball bonding wire bonder is used to heat and melt the tip of the wire transferred to the capillary to form a ball, and then lower the capillary to dispose the ball. After the first bump is formed on the conductor by applying a load and an ultrasonic wave to the conductor of the component and applying a load and an ultrasonic wave, the second bump is similarly superimposed on the first bump. Form.
【0013】また、本発明のバンプ付き電子部品は、電
子部品の導体部上に設けた第1のバンプと、該第の1バ
ンプの上に重ねて形成された第2のバンプとを備えるこ
とを特徴とするものである。Further, the electronic component with a bump according to the present invention includes a first bump provided on a conductor portion of the electronic component, and a second bump formed on the first bump. It is characterized by the following.
【0014】尚、ここで電子部品とは、半導体素子の外
に、プリント基板やガラス基板等の各種基板、フィルム
キャリア、フレキシブルプリント回路などであり、その
電極パッドや外部電極その他の導体部に、接続用のバン
プを形成し得るものを含む意味で使用する。Here, the electronic components include various substrates such as a printed circuit board and a glass substrate, a film carrier, a flexible printed circuit, etc., in addition to the semiconductor element. It is used in a sense that includes those that can form connection bumps.
【0015】[0015]
【発明の実施の形態】本発明では、通常のバンプの上
に、更に第2のバンプを重ねて形成する。従って、バン
プの直径に対する高さの比率を従来よりも大きくするこ
とができる。例えば、バンプの直径が従来と同じ場合に
はバンプの高さを従来よりも高くでき、バンプの高さが
従来と同じ場合にはバンプの直径を従来よりも小さくす
ることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a second bump is further formed on a normal bump. Therefore, the ratio of the height to the diameter of the bump can be made larger than before. For example, when the diameter of the bump is the same as the conventional one, the height of the bump can be made higher than before, and when the height of the bump is the same as the conventional one, the diameter of the bump can be made smaller than before.
【0016】そのため、フィルムキャリアや基板などの
平坦度にバラツキがあったり、傾きや反りなどが発生し
た場合であっても、バンプの高さが高いので、バンプを
挟んだ両側の電子部品全体を接合に必要な荷重で加圧す
ることができ、部分的な接合不良を防ぎ、全てのバンプ
について安定した接合を得ることができる。Therefore, even if the flatness of the film carrier or the substrate is varied, or if the inclination or warpage occurs, the height of the bumps is high. Pressure can be applied with a load necessary for bonding, partial bonding failure can be prevented, and stable bonding can be obtained for all bumps.
【0017】更に、狭パッドピッチ化によりバンプを小
さくした場合でも、バンプの直径の対して高さを十分高
くできるため、バンプを挟んで対向する電子部品の電極
パッドと外部電極などとの間に十分な余裕を持たせるこ
とが可能となる。その結果、一層の高密度化や多ピン化
が進行しても、バンプ付き電子部品の実装が困難になら
ず、実装の歩留り向上が期待できる。Further, even when the bumps are made smaller by reducing the pad pitch, the height can be made sufficiently higher than the diameter of the bumps. It is possible to provide a sufficient margin. As a result, even if the density and the number of pins are further increased, mounting of electronic components with bumps does not become difficult, and an improvement in mounting yield can be expected.
【0018】[0018]
【実施例】本発明によるバンプを、ボールボンディング
用ワイヤボンダーを用いて半導体素子の電極パッド上に
形成する場合について、図面を参照して説明する。ま
ず、図1に示すように、ボールボンディング用ワイヤボ
ンダーのキャピラリー2に金線などのワイヤ1を移送
し、その先端を放電電極3との放電により加熱して溶触
させ、ワイヤ1の先端にボール4を形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A case in which a bump according to the present invention is formed on an electrode pad of a semiconductor device using a wire bonder for ball bonding will be described with reference to the drawings. First, as shown in FIG. 1, a wire 1 such as a gold wire is transferred to a capillary 2 of a wire bonding wire bonder, and the tip of the wire 1 is heated by a discharge with a discharge electrode 3 to be welded. 4 is formed.
【0019】次に、図2に示すように、キャピラリー2
を下降させて上記ボール4を押し下げ、予め加熱した半
導体素子5の電極パッド6に当接させる。そのままボー
ル4を圧し潰しながら荷重と超音波を印加して、電極パ
ッド6に接合させる。接合が終了すると、図3に示すよ
うに、キャピラリー2の上方に設置されたクランパー7
でワイヤ1を挟持して、キャピラリー2と共にクランパ
ー7を上昇させ、ワイヤ1を引き千切って第1のバンプ
8aを形成する。Next, as shown in FIG.
Is lowered to push down the ball 4 so that the ball 4 comes into contact with the electrode pad 6 of the semiconductor element 5 which has been heated in advance. The load and the ultrasonic wave are applied while crushing the ball 4 as it is, and the ball 4 is bonded to the electrode pad 6. When the joining is completed, as shown in FIG. 3, the clamper 7 installed above the capillary 2
Then, the clamper 7 is moved up together with the capillary 2 by holding the wire 1 and the wire 1 is cut apart to form the first bump 8a.
【0020】その後、引き続き上記の操作を再度繰り返
して、第1のバンプの上に第2のバンプを形成する。即
ち、図4に示すように、ワイヤ1の先端に形成したボー
ル4を第1のバンプ8aの上に当接させ、上記と同様に
ボール4を圧し潰して接合させる。次に、キャピラリー
2と共にクランパー7を上昇させてワイヤ1を引き千切
り、図5に示すように、第1のバンプ8aの上に重ねて
第2のバンプ8bを形成する。Thereafter, the above operation is repeated again to form a second bump on the first bump. That is, as shown in FIG. 4, the ball 4 formed at the tip of the wire 1 is brought into contact with the first bump 8a, and the ball 4 is crushed and joined as described above. Next, the clamper 7 is moved up together with the capillary 2 to cut the wire 1 apart, and as shown in FIG. 5, the second bump 8b is formed on the first bump 8a.
【0021】このようにして形成した図5に示す本発明
のバンプ8は、第1のバンプ8aと第2のバンプ8bと
からなるので、従来のバンプ(図3に示す第1のバンプ
8aと同じ)に比べて、バンプ高さhを高くすることが
できる。また、バンプ8の直径を小さくした場合でも、
従来の一重のバンプに比べてバンプ高さhが相対的に高
くなる。The bump 8 of the present invention thus formed as shown in FIG. 5 is composed of the first bump 8a and the second bump 8b, so that the conventional bump (the first bump 8a shown in FIG. The same applies to (b), so that the bump height h can be increased. Also, even when the diameter of the bump 8 is reduced,
The bump height h is relatively higher than the conventional single bump.
【0022】上記第1のバンプ8aと第2のバンプ8b
とからなるバンプ8を備えた半導体素子5は、図6に示
すように、その電極パッド6上のバンプ8を例えば基板
9上の外部電極10に対向させ、加圧接合して互いに接
続することにより、通常のごとく実装して半導体装置を
構成することができる。The first bump 8a and the second bump 8b
As shown in FIG. 6, the semiconductor element 5 provided with the bumps 8 is formed by connecting the bumps 8 on the electrode pads 6 to, for example, the external electrodes 10 on the substrate 9 by pressure bonding. Accordingly, the semiconductor device can be configured by mounting as usual.
【0023】[0023]
【発明の効果】本発明によれば、バンプ高さを従来より
も高くできるので、半導体素子を接合すべきフィルムキ
ャリアや基板などの平坦度にバラツキがあったり、傾き
や反りなどが発生した場合でも、全体を接合に必要な荷
重で加圧することができ、接合不良のない良好な接合を
達成することができる。According to the present invention, since the bump height can be made higher than before, the flatness of the film carrier or the substrate to which the semiconductor element is to be bonded varies, and the bump or the tilt is generated. However, the whole can be pressurized with a load necessary for joining, and good joining without joining defects can be achieved.
【0024】また、多ビン化によりパッドのピッチが一
層狭くするために、バンプを小さくした場合でも、バン
プの直径に対して高さを相対的に高くできるので、電極
パッドと外部電極などとの間の間隔に余裕を持たせるこ
とができ、バンプによる実装を比較的簡単に行うことが
できる。Further, since the pitch of the pads is further narrowed by increasing the number of bins, the height can be relatively increased with respect to the diameter of the bumps even when the bumps are reduced. A margin can be given to the space between the bumps, and mounting by bumps can be performed relatively easily.
【0025】従って、バンプによる接続に部分的不良が
発生せず、高い歩留りで、簡単且つ確実に実装すること
ができるので、半導体装置の小型化及び高密度化、多ピ
ン化の要望に十分に対応することが可能となる。[0025] Therefore, no partial failure occurs in the connection by the bumps, and the mounting can be performed easily and reliably at a high yield, which is sufficient for the demand for miniaturization, high density, and multi-pin of the semiconductor device. It is possible to respond.
【図1】本発明方法におけるボール形成の工程を示す概
略の一部切欠側面図である。FIG. 1 is a schematic partially cutaway side view showing a ball forming step in the method of the present invention.
【図2】本発明方法におけるボール接合の工程を示す概
略の一部切欠側面図である。FIG. 2 is a schematic partially cutaway side view showing a ball joining step in the method of the present invention.
【図3】本発明方法における第1のバンプ形成の工程を
示す概略の一部切欠側面図である。FIG. 3 is a schematic partially cutaway side view showing a step of forming a first bump in the method of the present invention.
【図4】本発明方法における第2のバンプのためのボー
ル接合の工程を示す概略の一部切欠側面図である。FIG. 4 is a schematic partially cutaway side view showing a step of ball bonding for a second bump in the method of the present invention.
【図5】本発明のバンプ付き半導体素子を示す概略の側
面図である。FIG. 5 is a schematic side view showing a semiconductor device with bumps of the present invention.
【図6】本発明のバンプ付き半導体素子を基板に接続し
た状態を示す概略の側面図である。FIG. 6 is a schematic side view showing a state where the semiconductor device with bumps of the present invention is connected to a substrate.
【図7】従来のバンプ付き半導体素子を基板に接続した
状態を示す概略の側面図である。FIG. 7 is a schematic side view showing a state where a conventional semiconductor device with bumps is connected to a substrate.
1 ワイヤ 2 キャピラリー 3 放電電極 4 ボール 5 半導体素子 6 電極パッド 7 クランパー 8 パッド 8a 第1のパッド 8b 第2のパッド 9 基板 10 外部電極 Reference Signs List 1 wire 2 capillary 3 discharge electrode 4 ball 5 semiconductor element 6 electrode pad 7 clamper 8 pad 8a first pad 8b second pad 9 substrate 10 external electrode
Claims (3)
形成方法において、電子部品の導体部上に第1のバンプ
を形成し、引き続いて該第1のバンプの上に第2のバン
プを重ねて形成することを特徴とするバンプの形成方
法。In a method of forming a bump used for electrical connection of an electronic component, a first bump is formed on a conductor portion of the electronic component, and then a second bump is stacked on the first bump. A method of forming a bump, characterized in that the bump is formed.
用いて、そのキャピラリーに移送されたワイヤの先端を
加熱溶融してボールを形成し、キャピラリーを下降させ
て該ボールを電子部品の導体部上に当接させ、荷重と超
音波を印加して該導体部上に第1のバンプを形成した
後、該第1のバンプの上に第2のバンプを重ねて形成す
ることを特徴とする、請求項1に記載のバンプの形成方
法。2. A ball bonding wire bonder is used to heat and melt the tip of the wire transferred to the capillary to form a ball, and the capillary is lowered to bring the ball into contact with the conductor of the electronic component. And applying a load and ultrasonic waves to form a first bump on the conductor, and then forming a second bump on the first bump. 3. The method for forming a bump according to 1.
プと、該第の1バンプの上に重ねて形成された第2のバ
ンプとを備えることを特徴とするバンプ付き電子部品。3. An electronic component with bumps, comprising: a first bump provided on a conductor of the electronic component; and a second bump formed on the first bump.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10030733A JPH11233543A (en) | 1998-02-13 | 1998-02-13 | Forming method for bump and electronic part with bump |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10030733A JPH11233543A (en) | 1998-02-13 | 1998-02-13 | Forming method for bump and electronic part with bump |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11233543A true JPH11233543A (en) | 1999-08-27 |
Family
ID=12311882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10030733A Pending JPH11233543A (en) | 1998-02-13 | 1998-02-13 | Forming method for bump and electronic part with bump |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11233543A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7285854B2 (en) | 2004-03-18 | 2007-10-23 | Denso Corporation | Wire bonding method and semiconductor device |
-
1998
- 1998-02-13 JP JP10030733A patent/JPH11233543A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7285854B2 (en) | 2004-03-18 | 2007-10-23 | Denso Corporation | Wire bonding method and semiconductor device |
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