JPH0997816A - Mounting method and mounting structure of semiconductor device - Google Patents

Mounting method and mounting structure of semiconductor device

Info

Publication number
JPH0997816A
JPH0997816A JP19215096A JP19215096A JPH0997816A JP H0997816 A JPH0997816 A JP H0997816A JP 19215096 A JP19215096 A JP 19215096A JP 19215096 A JP19215096 A JP 19215096A JP H0997816 A JPH0997816 A JP H0997816A
Authority
JP
Japan
Prior art keywords
mounting
semiconductor device
mounting pad
substrate
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19215096A
Other languages
Japanese (ja)
Other versions
JP2770821B2 (en
Inventor
Asao Murakami
朝夫 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19215096A priority Critical patent/JP2770821B2/en
Publication of JPH0997816A publication Critical patent/JPH0997816A/en
Application granted granted Critical
Publication of JP2770821B2 publication Critical patent/JP2770821B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent faulty connections together with maintaining a good connection state for a long time. SOLUTION: A semiconductor element 105 is provided with a bump electrode 107 having a plurality of pointed tails 106 at least on its one surface. On the other hand, a circuit board 101 is formed of a laminated structure having an inner layer circuit 102, and a pad 103 for mounting is formed on the board 101. A pad 103 for mounting has a recessed part and the base 110 of the recessed part is in contact with a part of the inner layercircuit 102. Further, sealing resin 109 is in advance provided on the board 101. The tail 106 is deformed by pressing the bump electrode 107 on the recessed base 110 of the pad 103 for mounting so that a contact part between the bump electrode 107 and the pad 103 for mounting may gradually expand from a point to a surface. After the tail 106 is sufficiently deformed, sealing resin 10 is cured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置を基板
に実装する方法およびその実装構造に関し、特に、フリ
ップチップ方式による半導体装置を基板に実装する方法
およびその実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor device on a substrate and its mounting structure, and more particularly to a method of mounting a semiconductor device by a flip chip method on a substrate and its mounting structure.

【0002】[0002]

【従来の技術】近年、電子機器の小型化、低価格化に伴
い、半導体素子を基板に高密度で実装するための構造が
簡略化されてきている。このような簡略化された構造を
有する半導体素子の高密度実装構造としてフリップチッ
プ方式が提案されている。
2. Description of the Related Art In recent years, with the miniaturization and cost reduction of electronic equipment, the structure for mounting semiconductor elements on a substrate at high density has been simplified. A flip-chip method has been proposed as a high-density mounting structure of a semiconductor device having such a simplified structure.

【0003】フリップチップ方式は、複数のバンプ電極
が少なくとも一つの面に実装された半導体素子を、その
面をフェイスダウンさせて回路基板に接続するものであ
り、特開平4−82241号公報に開示されている。
The flip-chip method is a method for connecting a semiconductor element having a plurality of bump electrodes mounted on at least one surface to a circuit board with the surface facing down, and is disclosed in JP-A-4-82241. Has been done.

【0004】図9(A)および(B)を参照して、従来
のフリップチップ実装構造について説明する。
A conventional flip-chip mounting structure will be described with reference to FIGS. 9 (A) and 9 (B).

【0005】基板1上に、ゴム等の弾性回復力を有する
物質からなる絶縁性樹脂層2が形成されている。さら
に、絶縁性樹脂層2上にスパッタリング法あるいは蒸着
法により実装用パッド3が形成されている。絶縁性樹脂
層2上の半導体素子4が基板1に固定される領域であっ
て、基板1上の実装用パッド3が形成される領域も含む
領域に封止樹脂5が塗布されている。一方、半導体素子
4の基板1側の面には、複数のバンプ電極6が形成され
ている。
An insulating resin layer 2 made of a substance having an elastic recovery force such as rubber is formed on a substrate 1. Further, the mounting pad 3 is formed on the insulating resin layer 2 by the sputtering method or the vapor deposition method. The sealing resin 5 is applied to a region where the semiconductor element 4 on the insulating resin layer 2 is fixed to the substrate 1, including a region where the mounting pad 3 is formed on the substrate 1. On the other hand, a plurality of bump electrodes 6 are formed on the surface of the semiconductor element 4 on the substrate 1 side.

【0006】まず、半導体素子4の下面に設けられる複
数のバンプ電極6と基板1上の実装用パッド3との位置
合わせを行い、次いで、半導体素子4が基板1上に加圧
圧接される。この際、半導体素子4のバンプ電極6と基
板1上の実装用パッド3との間に存在していた封止樹脂
5が押し出されるため、バンプ電極6と実装用パッド3
とが電気的に接続される。この従来のフリップチップ実
装構造では、基板1と実装用パッド3との間に弾性回復
力を有する絶縁性樹脂層2が形成されているために、絶
縁性樹脂層2の弾性回復力と封止樹脂5の収縮力によっ
てバンプ電極6と実装用パッド3との電気的接続が安定
して保持される。
First, the plurality of bump electrodes 6 provided on the lower surface of the semiconductor element 4 are aligned with the mounting pads 3 on the substrate 1, and then the semiconductor element 4 is pressed and pressed onto the substrate 1. At this time, since the sealing resin 5 existing between the bump electrode 6 of the semiconductor element 4 and the mounting pad 3 on the substrate 1 is extruded, the bump electrode 6 and the mounting pad 3 are extruded.
And are electrically connected. In this conventional flip-chip mounting structure, since the insulating resin layer 2 having an elastic recovery force is formed between the substrate 1 and the mounting pad 3, the elastic recovery force of the insulating resin layer 2 and sealing The contraction force of the resin 5 stably maintains the electrical connection between the bump electrode 6 and the mounting pad 3.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この従
来のフリップチップ実装構造では、温度サイクル試験等
の加速試験において絶縁性樹脂層2の弾性回復力および
封止樹脂5の収縮力が劣化しやすく、結果として、封止
樹脂5の熱膨張量がその収縮力および絶縁性樹脂層2の
弾性回復力を上回り、バンプ電極6と実装用パッド3の
間に隙間が形成される。したがって、バンプ電極6と実
装用パッド3との間に形成された隙間が原因で、半導体
素子4と基板1とが接続不良を起こす。
However, in this conventional flip chip mounting structure, the elastic recovery force of the insulating resin layer 2 and the contracting force of the sealing resin 5 are easily deteriorated in an accelerated test such as a temperature cycle test. As a result, the thermal expansion amount of the sealing resin 5 exceeds its contracting force and the elastic recovery force of the insulating resin layer 2, and a gap is formed between the bump electrode 6 and the mounting pad 3. Therefore, due to the gap formed between the bump electrode 6 and the mounting pad 3, the semiconductor element 4 and the substrate 1 have a poor connection.

【0008】さらに、この従来のフリップチップ実装構
造では、実装用パッド3および絶縁性樹脂層2を弾性変
形させた状態で、半導体素子4と基板1とを接続させて
いる。そのため、温度変化により封止樹脂5の収縮力と
絶縁性樹脂層2の弾性回復力とのバランスが変化した場
合、それに伴って実装用パッド3の変形状態も変化す
る。このように、温度変化により、実装用パッド3にか
なりのストレスが加わることになり、その結果、実装用
パッド3が損傷して、断線等が生じるケースもある。
Further, in this conventional flip chip mounting structure, the semiconductor element 4 and the substrate 1 are connected to each other with the mounting pad 3 and the insulating resin layer 2 elastically deformed. Therefore, when the balance between the contracting force of the sealing resin 5 and the elastic recovery force of the insulating resin layer 2 changes due to the temperature change, the deformation state of the mounting pad 3 also changes accordingly. As described above, due to the temperature change, a considerable amount of stress is applied to the mounting pad 3, and as a result, the mounting pad 3 may be damaged, causing disconnection or the like.

【0009】さらに、従来のフリップチップ構造では、
基板1上に弾性回復力を有する絶縁性樹脂層2を形成す
る必要があるために、製造工程の複雑化、高コスト化を
避けることはできない。
Further, in the conventional flip chip structure,
Since it is necessary to form the insulating resin layer 2 having the elastic recovery force on the substrate 1, it is inevitable that the manufacturing process is complicated and the cost is increased.

【0010】さらに、従来のフリップリップ実装構造で
は、球状のバンプ電極を予め塗布された封止樹脂中に埋
入させて、このバンプ電極と実装用パッドとの接続を図
っているために、バンプ電極と実装用パッドとの間に封
止樹脂が残留した状態で両者が接続されてしまう。した
がって、バンプ電極と実装用パッドとの間に不要な封止
樹脂が残留しているために、接続状態が極めて不安定で
あるという問題点もある。
Further, in the conventional flip-lip mounting structure, since the spherical bump electrode is embedded in the sealing resin applied in advance to connect the bump electrode and the mounting pad, The sealing resin remains between the electrode and the mounting pad, and the two are connected. Therefore, there is a problem that the connection state is extremely unstable because the unnecessary sealing resin remains between the bump electrode and the mounting pad.

【0011】[0011]

【課題を解決するための手段】上記問題点を解決するた
めに、本発明の半導体装置の実装方法は、複数の突起電
極を有する半導体装置を基板に実装する方法であって、
基板上には実装用パッドが予め形成されているととも
に、基板上の前記半導体装置が実装される領域上には封
止樹脂が予め備えられ、突起電極を実装用パッドに押し
つけて、突起電極の先端を突起電極と実装用パッドとの
接触面積が点から面に拡大するように変形させた後、封
止樹脂を硬化させるものである。
In order to solve the above problems, a semiconductor device mounting method according to the present invention is a method of mounting a semiconductor device having a plurality of protruding electrodes on a substrate.
A mounting pad is formed in advance on the substrate, and a sealing resin is preliminarily provided on a region of the substrate where the semiconductor device is mounted. The protruding electrode is pressed against the mounting pad to remove the protruding electrode. The tip end is deformed so that the contact area between the bump electrode and the mounting pad is expanded from the point to the surface, and then the sealing resin is cured.

【0012】また、本発明の半導体装置の実装構造は、
基板上に設けられる実装用パッドと、半導体装置の基板
側の面に設けられ、略球状の第1の部分と実装用パッド
に加圧圧接されて該実装用パッドとの接触部分が点から
面へと拡大するように変形された第2の部分とを含んで
形成される複数の突起電極と、基板と半導体装置との間
に配置される封止樹脂とを備えるものである。
The semiconductor device mounting structure of the present invention is
The mounting pad provided on the substrate and the surface of the semiconductor device on the substrate side are pressed from the substantially spherical first portion and the mounting pad under pressure to contact the mounting pad from a point. A plurality of projecting electrodes formed to include a second portion that has been deformed so as to expand to and a sealing resin disposed between the substrate and the semiconductor device.

【0013】[0013]

【発明の実施の形態】本発明の第1の実施形態につい
て、図1(A)〜(C)を参照して詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described in detail with reference to FIGS.

【0014】図1(A)を参照すると、内層回路102
を有する積層構造の回路基板101上には、底面110
が内層回路102と接するような凹状の実装用パッド1
03が設けられている。一方、半導体素子105の回路
基板101側の面には、尖状のテール106を有する複
数のバンプ電極107が電極108を介して設けられて
いる。
Referring to FIG. 1A, the inner layer circuit 102.
On the circuit board 101 having a laminated structure having
Mounting pad 1 having a concave shape such that the pad contacts the inner layer circuit 102
03 is provided. On the other hand, on the surface of the semiconductor element 105 on the circuit board 101 side, a plurality of bump electrodes 107 having pointed tails 106 are provided via electrodes 108.

【0015】図1(A)では、回路基板101上に封止
樹脂109が供給され、実装用パッド103にバンプ電
極107を対向させるように、半導体素子105が回路
基板101に対して位置合わせされている。
In FIG. 1A, the sealing resin 109 is supplied onto the circuit board 101, and the semiconductor element 105 is aligned with the circuit board 101 so that the bump electrodes 107 face the mounting pads 103. ing.

【0016】図1(B)を参照すると、半導体素子10
5を回路基板101に対し押しつけて、バンプ電極10
7のテール106を封止樹脂109中に埋入させる。埋
入したテール106の先端は、実装用パッド103の底
面110に当接する。さらに、半導体素子105を回路
基板101に対して押圧して、図1(C)に示すよう
に、バンプ電極107のテール106を塑性変形させて
実装用パッド103の底面110に圧接させる。そし
て、封止樹脂109を半導体素子105のバンプ電極1
03が設置された面にも接着させた状態で、封止樹脂1
09を加熱硬化させる。
Referring to FIG. 1B, the semiconductor device 10
5 is pressed against the circuit board 101, and the bump electrode 10
The tail 106 of No. 7 is embedded in the sealing resin 109. The tip of the embedded tail 106 contacts the bottom surface 110 of the mounting pad 103. Further, the semiconductor element 105 is pressed against the circuit board 101, and as shown in FIG. 1C, the tail 106 of the bump electrode 107 is plastically deformed and brought into pressure contact with the bottom surface 110 of the mounting pad 103. Then, the sealing resin 109 is used as the bump electrode 1 of the semiconductor element 105.
03 is also attached to the surface on which the sealing resin 1 is attached.
09 is cured by heating.

【0017】本実施形態では、半導体素子105のバン
プ電極107が回路基板101の実装用パッド103上
に接触した後、さらに、バンプ電極107を実装用パッ
ド103に強く押しつけたとしても、実装用パッド10
3の底面110に接して下層に形成された内層回路10
2が、バンプ電極107による実装用パッド103への
押圧力を分散させる。したがって、実装用パッド103
がその押圧力により変形することはなく、バンプ電極1
07のテール106のみが塑性変形するために、実装用
パッド103の損傷に対する信頼性を保持したまま、確
実にバンプ電極107を実装用パッド103に接続する
ことができる。
In the present embodiment, even if the bump electrode 107 of the semiconductor element 105 contacts the mounting pad 103 of the circuit board 101 and then the bump electrode 107 is strongly pressed against the mounting pad 103, the mounting pad 103 10
The inner layer circuit 10 formed in the lower layer in contact with the bottom surface 110
2 disperses the pressing force applied to the mounting pad 103 by the bump electrode 107. Therefore, the mounting pad 103
Is not deformed by the pressing force, and the bump electrode 1
Since only the tail 106 of 07 is plastically deformed, the bump electrode 107 can be reliably connected to the mounting pad 103 while maintaining reliability against damage to the mounting pad 103.

【0018】また、本実施形態では、圧接工法用樹脂の
特性として硬化収縮率が熱膨張率よりも大きいものを封
止樹脂109として用いている。この封止樹脂109を
介して半導体素子105を回路基板101に高温加熱加
圧して実装すると、封止樹脂109は高い収縮率を得て
バンプ電極107と実装用パッド103とを確実に接続
させることができる。また、高温環境下においても硬化
収縮率が熱膨張率を上回っているためバンプ電極107
を実装用パッド103から離そうとする力が働かず、し
たがって、接続状態が不安定になることはない。
Further, in the present embodiment, as the characteristic of the resin for the pressure welding method, a resin having a curing shrinkage ratio larger than the thermal expansion coefficient is used as the sealing resin 109. When the semiconductor element 105 is mounted on the circuit board 101 by heating and pressurizing it at a high temperature via the sealing resin 109, the sealing resin 109 obtains a high shrinkage ratio and the bump electrode 107 and the mounting pad 103 are securely connected. You can In addition, since the curing shrinkage rate exceeds the thermal expansion rate even in a high temperature environment, the bump electrode 107
Does not act to separate the mounting pad 103 from the mounting pad 103, so that the connection state does not become unstable.

【0019】また、半導体素子105のバンプ電極10
7のテール106の形状が尖状であるために、バンプ電
極107を実装用パッド103に押しつけてテール10
6を変形させることにより、バンプ電極107の先端と
実装用パッド103との接触部分が点から面へ広がる。
したがって、実装用パッド103上に存在していた封止
樹脂109が、確実にテール106とパッド103との
接触部分から排除される。バンプ電極107と実装用パ
ッド103の挟雑物のない確実な接続を得ることができ
る。
The bump electrode 10 of the semiconductor element 105 is also included.
7 has a pointed shape, the bump electrode 107 is pressed against the mounting pad 103 so that the tail 10
By deforming 6, the contact portion between the tip of the bump electrode 107 and the mounting pad 103 spreads from the point to the surface.
Therefore, the sealing resin 109 existing on the mounting pad 103 is reliably removed from the contact portion between the tail 106 and the pad 103. It is possible to obtain a reliable connection between the bump electrode 107 and the mounting pad 103 without foreign matter.

【0020】次に、本発明の第1の実施形態を図2
(A)〜(D)、図3(A)〜(D)、図4(A)、
(B)および図5を参照して、さらに詳細に説明する。
Next, a first embodiment of the present invention will be described with reference to FIG.
(A)-(D), FIG. 3 (A)-(D), FIG. 4 (A),
This will be described in more detail with reference to (B) and FIG.

【0021】図2(A)には、半導体素子が実装されて
いない状態の回路基板が示される。回路基板101上に
設けれた実装用パッド103は凹形状を有しており、そ
の凹部の底面110が回路基板の内層回路102と接続
されている。
FIG. 2A shows a circuit board in which a semiconductor element is not mounted. The mounting pad 103 provided on the circuit board 101 has a concave shape, and the bottom surface 110 of the concave portion is connected to the inner layer circuit 102 of the circuit board.

【0022】ここで、このような実装用パッドが設けら
れた回路基板の製造方法について図3(A)〜(D)を
参照して説明する。
Now, a method of manufacturing a circuit board provided with such mounting pads will be described with reference to FIGS.

【0023】回路基板は、プリント配線基板上に樹脂層
を積みフォトビアホールで各層の接続を取るような、い
わゆる、ビルドアップ工法におけるフォトビアホールの
形成方法を適用して、製造することができる。
The circuit board can be manufactured by applying a method of forming a photo via hole in a so-called build-up method in which a resin layer is stacked on a printed wiring board and each layer is connected by a photo via hole.

【0024】回路基板101は、エポキシを含む材料か
らなる基板111上に内層回路102が形成される積層
板を用いる。図3(A)を参照すると、内層回路102
上には、感光性樹脂112が塗布されている。さらに、
図3(B)に示すように、感光性樹脂112表面の一部
に斜光材113を配置し、上方から一様に光114を照
射する。すると、図3(C)に示すとおり、光114が
照射された領域における感光性樹脂112は、内層回路
102上で硬化し、一方、斜光材113が設けられた部
分のみ、光114が照射されないため、樹脂112は硬
化せずに除去され、内層回路102の一部が露出され
る。さらに、その感光性樹脂112上および露出した内
層回路102上に、めっき工法等により、実装用パッド
103を形成する。最後に、実装用パッドの表面に対し
て研磨が施される。
As the circuit board 101, a laminated board in which the inner layer circuit 102 is formed on the board 111 made of a material containing epoxy is used. Referring to FIG. 3A, the inner layer circuit 102.
A photosensitive resin 112 is applied on the top. further,
As shown in FIG. 3B, the oblique light material 113 is arranged on a part of the surface of the photosensitive resin 112, and the light 114 is uniformly irradiated from above. Then, as shown in FIG. 3C, the photosensitive resin 112 in the region irradiated with the light 114 is cured on the inner layer circuit 102, while the light 114 is not irradiated only in the portion provided with the oblique light material 113. Therefore, the resin 112 is removed without being cured, and a part of the inner layer circuit 102 is exposed. Further, the mounting pad 103 is formed on the photosensitive resin 112 and the exposed inner layer circuit 102 by a plating method or the like. Finally, the surface of the mounting pad is polished.

【0025】凹状に形成された実装用パッド103を備
える回路基板101の形成方法は、フォトビア法に限ら
れるものではなく、レーザ光を用いた穴開け技術を適用
しても良い。
The method of forming the circuit board 101 having the mounting pads 103 formed in a concave shape is not limited to the photo via method, and a drilling technique using laser light may be applied.

【0026】実装用パッド103の厚みに関しては、周
知のめっき工法により所望の厚みを得ることができるた
め、特に限定されないが、本実施形態では、例えば、2
0μm程度とする。また、実装用パッド103の凹部形
状は、特に限定されるものではないが、本実施形態で
は、開口径を90μm、底面の直径を50μmの円形状
のものを採用する。
The thickness of the mounting pad 103 is not particularly limited because a desired thickness can be obtained by a known plating method, but in the present embodiment, for example, 2
It is about 0 μm. Further, the concave shape of the mounting pad 103 is not particularly limited, but in the present embodiment, a circular shape having an opening diameter of 90 μm and a bottom surface diameter of 50 μm is adopted.

【0027】図2(B)を参照すると、回路基板101
上の半導体素子105を搭載する領域に封止樹脂109
が供給される。封止樹脂の供給方法としては、スクリー
ン印刷工法を適用することができるが、この工法に限定
されるものではなく、他の公知の方法、例えば、ディス
ペンサーを用いて封止樹脂109を回路基板101上に
供給する方法等も適用することができる。また、封止樹
脂109としては、エポキシ系の熱硬化型即硬化性樹脂
で硬化収縮率の値が熱膨張率の値よりも大きい樹脂が使
用される。本実施形態では、例えば、封止樹脂109と
して、270゜Cの加熱を30秒ほど行うことにより硬化
が完了するものを使用する。
Referring to FIG. 2B, the circuit board 101
An encapsulating resin 109 is formed on the region where the semiconductor element 105 is mounted.
Is supplied. As a method for supplying the sealing resin, a screen printing method can be applied, but the method is not limited to this method, and another known method, for example, the sealing resin 109 is applied to the circuit board 101 by using a dispenser. A method of supplying the above can also be applied. Further, as the sealing resin 109, an epoxy-based thermosetting type immediate curable resin having a curing shrinkage value larger than that of the thermal expansion coefficient is used. In this embodiment, for example, as the sealing resin 109, one that is cured by heating at 270 ° C. for about 30 seconds is used.

【0028】なお、本実施形態において、封止樹脂とし
ては、加熱硬化するものに限らず、紫外線を照射するこ
とにより硬化する樹脂等も用いることができる。
In the present embodiment, the encapsulating resin is not limited to one that is heat-curable, but a resin that is cured by irradiating ultraviolet rays can be used.

【0029】次に、図2(C)に示すように、半導体素
子105の下面に形成された複数のバンプ電極107と
回路基板101上の実装用パッド103の底面110と
の位置とが対応するように位置合わせが行われる。
Next, as shown in FIG. 2C, the positions of the plurality of bump electrodes 107 formed on the lower surface of the semiconductor element 105 and the bottom surface 110 of the mounting pad 103 on the circuit board 101 correspond to each other. The alignment is performed as follows.

【0030】ここで、テールを有するバンプ電極の形成
方法は、図4(A)および(B)に示すとおり、ワイヤ
ボンディング法を適用して形成することができる。バン
プ電極を形成するためのワイヤの材質としては、金ある
いは金を含む合金が適用される。特に、99.999%
高純度の金に特定の元素添加と熱処理を行うことによっ
て生成された材料が用いられる。
Here, the bump electrode having a tail can be formed by applying a wire bonding method as shown in FIGS. 4 (A) and 4 (B). Gold or an alloy containing gold is applied as the material of the wire for forming the bump electrode. Especially 99.999%
A material produced by adding a specific element and performing heat treatment on high-purity gold is used.

【0031】図4(A)を参照すると、先端が球状に形
成されたボンディングワイヤ115がツール116によ
り、電極108上に所定の押圧力で圧接される。次に、
図4(B)に示すとおり、ツール116を所定の力で、
電極108に対して真上に引き上げることによって、一
定の高さでボンディングワイヤ115を破断させ、略球
状の部分に高さばらつきのない尖状形状のテールが備え
られたバンプ電極107を電極108上に形成すること
ができる。
Referring to FIG. 4A, the bonding wire 115 having a spherical tip is pressed against the electrode 108 by a predetermined pressing force by the tool 116. next,
As shown in FIG. 4B, the tool 116 is applied with a predetermined force.
The bonding wire 115 is broken at a constant height by pulling it up right above the electrode 108, and the bump electrode 107 having a pointed tail with no height variation in a substantially spherical portion is provided on the electrode 108. Can be formed.

【0032】また、本実施形態のバンプ電極107の形
状としては、図5に示すとおり、バンプ径が80μm、
テール径20μm、バンプ厚40μmおよびテール長5
0μmとする。しかしながら、これらのサイズは、特に
これに限定されるものではなく、例えば、バンプ径は、
半導体素子105上に設けれる電極108の大きさに応
じて適宜設計され、また、テール径も、所望のバンプ径
に応じて用いられるボンディングワイヤ115の径にほ
ぼ一致する。また、テール長は、これは、バンプ全長、
バンプ厚とテール長の合計である、に対し、40%から
70%程度に設計されることが可能であるが、好ましく
は、50%から60%程度の高さとすることが好まし
い。テール長が、バンプ全長に対して、短すぎたり、あ
るいは長すぎたりする場合には、半導体素子と回路基板
を接続する際に、バンプ電極の高さにばらつきが生じ易
く、結果として、良好な接続状態を得ることができな
い。
As shown in FIG. 5, the bump electrode 107 of the present embodiment has a bump diameter of 80 μm,
Tail diameter 20 μm, bump thickness 40 μm and tail length 5
0 μm. However, these sizes are not particularly limited, and for example, the bump diameter is
The tail diameter is appropriately designed according to the size of the electrode 108 provided on the semiconductor element 105, and the diameter of the bonding wire 115 used according to the desired bump diameter is substantially the same. Also, the tail length is the total bump length,
The total thickness of the bump thickness and the tail length can be designed to be 40% to 70%, but preferably 50% to 60%. If the tail length is too short or too long with respect to the entire length of the bump, the height of the bump electrode tends to vary when connecting the semiconductor element and the circuit board, and as a result, good Cannot get connection status.

【0033】さらに、図2(D)を参照すると、半導体
素子105が、回路基板101に加圧・加熱される。こ
こで、加圧量は、バンプ電極107が変形するのに十分
な量とし、本実施形態では、バンプ電極1071個当た
り30グラムとする。また、加熱量は、半導体素子10
5側を270度、回路基板101側を80度で、保持時
間30秒とする。なお、バンプ電極107の変形量は、
テール106のほぼ全体が変形することが好ましいが、
塑性変形後のテール106の高さが、変形前のテール長
の少なくとも50%以下となるようにする。
Further, referring to FIG. 2D, the semiconductor element 105 is pressed and heated on the circuit board 101. Here, the amount of pressurization is set to an amount sufficient to deform the bump electrode 107, and in the present embodiment, 30 grams per one bump electrode 107. Further, the heating amount is the semiconductor element 10
The 5 side is 270 degrees, the circuit board 101 side is 80 degrees, and the holding time is 30 seconds. The amount of deformation of the bump electrode 107 is
Although it is preferable that substantially the entire tail 106 be deformed,
The height of the tail 106 after plastic deformation is at least 50% or less of the tail length before deformation.

【0034】テール107と実装用パッド103の底面
110との接触面積が、テール106の塑性変形に進行
につれて、点から面へ拡大されていく。したがって、バ
ンプ電極107と実装用パッド103との接触部から完
全に封止樹脂109を排除することができ、接続状態を
良好にすることができる。さらに、接触面積が拡大され
るため、安定した接続状態を得ることができる。
The contact area between the tail 107 and the bottom surface 110 of the mounting pad 103 expands from a point to a surface as the plastic deformation of the tail 106 progresses. Therefore, the sealing resin 109 can be completely removed from the contact portion between the bump electrode 107 and the mounting pad 103, and the connection state can be improved. Furthermore, since the contact area is expanded, a stable connection state can be obtained.

【0035】また、バンプ電極107から実装用パッド
103が受ける押圧力は、実装用パッド103の下層に
配置される内層回路102で分散される。したがって、
実装用パッド103の変形を低減することができる。
Further, the pressing force received by the mounting pad 103 from the bump electrode 107 is dispersed in the inner layer circuit 102 arranged in the lower layer of the mounting pad 103. Therefore,
The deformation of the mounting pad 103 can be reduced.

【0036】次に、本発明の第2の実施形態について図
6(A)〜(C)および図7(A)〜(D)を参照して
詳細に説明する。
Next, a second embodiment of the present invention will be described in detail with reference to FIGS. 6 (A)-(C) and FIGS. 7 (A)-(D).

【0037】図6(A)を参照すると、半導体素子10
5および半導体素子105に配置されるテール106を
有する複数のバンプ電極107は、前述の第1の実施形
態の構成と同様である。したがって、バンプ電極107
の形成方法も、図4(A)および(B)で示した方法を
適用することができ、また、バンプ電極107の形状
も、図5に示した形状を適用できる。一方、内層回路1
02を有する積層構造の回路基板101には、底面11
7が内層回路102と接するような凹状の実装用パッド
118が設けられている。実装用パッド118の凹部の
断面形状は、図6(A)に示すとおり、台形状であり、
底面117の径が凹部の開口の径よりも大きい。このよ
うな形状を有する実装用パッド118を設けた回路基板
101の形成方法は、基本的には、図3(A)〜(D)
で示したプリント基板に対するビルドアップ工法のフォ
トビアホールの形成方法を適用することができるが、本
実施形態では、実装用パッド118の凹部の断面形状を
台形とするために、フォトビアホールの形成時に研磨量
を調整する必要がある。
Referring to FIG. 6A, the semiconductor device 10
5 and the plurality of bump electrodes 107 having tails 106 arranged on the semiconductor element 105 are similar to those of the first embodiment described above. Therefore, the bump electrode 107
The method shown in FIGS. 4 (A) and 4 (B) can be applied to the method of forming the above, and the shape shown in FIG. 5 can be applied to the bump electrode 107. On the other hand, the inner layer circuit 1
The circuit board 101 having a laminated structure including 02 has a bottom surface 11
A concave mounting pad 118 is provided so that 7 contacts the inner layer circuit 102. The cross-sectional shape of the recess of the mounting pad 118 is trapezoidal as shown in FIG.
The diameter of the bottom surface 117 is larger than the diameter of the opening of the recess. The method of forming the circuit board 101 provided with the mounting pad 118 having such a shape is basically the same as that shown in FIGS.
The method of forming a photo via hole of the build-up method for the printed circuit board shown in can be applied. The amount needs to be adjusted.

【0038】本実施形態では、実装用パッド118の凹
部の形状として、開口径が40μm、底面の直径が50
μmである円形状のものを使用する。
In this embodiment, the recess of the mounting pad 118 has an opening diameter of 40 μm and a bottom surface diameter of 50.
A circular one having a size of μm is used.

【0039】本実施形態における半導体素子105を回
路基板101に実装する工程は、図1(A)〜(C)お
よび図2(A)〜(D)で示した第1の実施形態と同様
である。しかしながら、半導体素子105を回路基板1
01に加熱・加圧して、バンプ電極107を塑性変形さ
せる場合、変形後のテール106の最大径が、実装用パ
ッド118の開口径よりも大きくすることが好ましい。
こうすることにより、バンプ電極107が実装用パッド
118の開口部分に引っかかり、実装用パッド118の
凹部内部に固定される。したがって、バンプ電極107
と実装用パッド118との接続保持力が、封止樹脂10
9の収縮力のみではなく、構造的な係止作用による物理
的な保持力が加わるため、接続信頼性をさらに向上させ
ることができる。本実施形態では、構造的な接続保持力
を得ることができるため、封止樹脂として硬化収縮率の
値が熱膨張率の値よりも小さいものでも使用することが
できる。
The steps of mounting the semiconductor element 105 on the circuit board 101 in this embodiment are the same as those in the first embodiment shown in FIGS. 1A to 1C and 2A to 2D. is there. However, when the semiconductor element 105 is connected to the circuit board 1
When the bump electrode 107 is plastically deformed by heating and pressurizing to 01, it is preferable that the maximum diameter of the deformed tail 106 be larger than the opening diameter of the mounting pad 118.
By doing so, the bump electrode 107 is caught in the opening portion of the mounting pad 118 and fixed inside the recess of the mounting pad 118. Therefore, the bump electrode 107
The connection holding force between the mounting pad 118 and the mounting pad 118 is
Not only the contracting force of 9 but also the physical holding force by the structural locking action is applied, so that the connection reliability can be further improved. In the present embodiment, a structural connection holding force can be obtained, and thus a sealing resin having a curing shrinkage value smaller than a thermal expansion coefficient value can also be used.

【0040】本発明の第1の実施形態および第2の実施
形態では、実装用パッドが凹状に形成され、さらに、回
路基板として、内層回路を有する積層構造のものを使用
する例を示したが、本発明は、これらに限定されるもの
ではない。
In the first and second embodiments of the present invention, an example is shown in which the mounting pads are formed in a concave shape, and a circuit board having a laminated structure having an inner layer circuit is used. However, the present invention is not limited to these.

【0041】図8(A)〜(C)に示す本発明の第3の
実施形態では、基板119は、内層回路を有しおらず、
その上面に実装用パッド120が形成されている。ま
た、実装用パッド120は、凹状に形成されてはいな
い。一方、半導体素子105に形成されるバンプ電極1
07は、その形成方法および形状ともに、既に説明され
た本発明の第1および第2の実施形態のバンプ電極と同
様のものである。
In the third embodiment of the present invention shown in FIGS. 8A to 8C, the substrate 119 has no inner layer circuit,
The mounting pad 120 is formed on the upper surface thereof. Moreover, the mounting pad 120 is not formed in a concave shape. On the other hand, the bump electrode 1 formed on the semiconductor element 105
No. 07 has the same formation method and shape as those of the bump electrodes of the first and second embodiments of the present invention described above.

【0042】なお、図8(A)から(C)に示される半
導体素子105を基板119に実装する工程は、基本的
に、図1(A)〜(C)で示された方法と同様である。
本実施形態では、基板119が内層回路を有していない
ため、半導体素子105による基板119への押圧力を
大きくし過ぎると、実装用パッド120の変形を招くた
めに注意が必要である。一方、バンプ電極107の塑性
変形を利用して、バンプ電極107と実装用パッド12
0との接触面積が点から面へ拡大するために、バンプ電
極107と実装用パッド120との間に余計な封止樹脂
が残留することを防ぐことができ、従来の実装構造と比
較して、接続状態を良好にすることができる。
The process of mounting the semiconductor element 105 shown in FIGS. 8A to 8C on the substrate 119 is basically the same as the method shown in FIGS. 1A to 1C. is there.
In the present embodiment, since the substrate 119 does not have an inner layer circuit, it should be noted that if the pressing force of the semiconductor element 105 on the substrate 119 is excessively large, the mounting pad 120 may be deformed. On the other hand, by utilizing the plastic deformation of the bump electrode 107, the bump electrode 107 and the mounting pad 12
Since the contact area with 0 expands from the point to the surface, it is possible to prevent excess sealing resin from remaining between the bump electrode 107 and the mounting pad 120, and compared with the conventional mounting structure. , The connection state can be improved.

【0043】[0043]

【発明の効果】以上説明したとおり、本発明の半導体装
置の実装方法および実装構造では、半導体装置に設けれ
たバンプ電極の先端に尖状のテールを設け、このテール
と実装用パッドとの接触面積が、テールの塑性変形に進
行につれて、点から面へ拡大されるように、半導体装置
を基板に押しつけて、両者を接続している。したがっ
て、バンプ電極と実装用パッドとの接触部から完全に封
止樹脂を排除することができ、接続状態を良好にするこ
とができる。さらに、接触面積が拡大されるため、安定
した接続状態を得ることができる。
As described above, according to the mounting method and mounting structure of the semiconductor device of the present invention, the tip of the bump electrode provided in the semiconductor device is provided with a pointed tail, and the tail is brought into contact with the mounting pad. The semiconductor device is pressed against the substrate so that the area is enlarged from the point to the surface as the plastic deformation of the tail progresses, and the two are connected. Therefore, the sealing resin can be completely removed from the contact portion between the bump electrode and the mounting pad, and the connection state can be improved. Furthermore, since the contact area is expanded, a stable connection state can be obtained.

【0044】さらに、基板として、内層回路を有する積
層構造の基板を使用し、その基板状に形成される実装用
パッドを、底面が内層回路と接触するような凹部形状と
することによって、バンプ電極から実装用パッドが受け
る押圧力は、実装用パッドの下層に配置される内層回路
で分散される。したがって、実装用パッドの変形を低減
することができ、接続状態を良好に保つことができる。
Further, a substrate having a laminated structure having an inner layer circuit is used as the substrate, and the mounting pad formed on the substrate is formed into a concave shape whose bottom surface contacts the inner layer circuit. The pressing force received by the mounting pad from is dispersed in the inner layer circuit arranged below the mounting pad. Therefore, the deformation of the mounting pad can be reduced, and the connection state can be kept good.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施形態の主要部の構成および
実装工程を示す図である。
FIG. 1 is a diagram showing a configuration and a mounting process of a main part of a first embodiment of the present invention.

【図2】本発明の第1の実施形態の構成および実装工程
を示す図である。
FIG. 2 is a diagram showing a configuration and a mounting process of the first embodiment of the present invention.

【図3】本発明の第1の実施形態における回路基板の構
成および形成工程を示す図である。
FIG. 3 is a diagram showing a configuration and a forming process of a circuit board according to the first embodiment of the present invention.

【図4】本発明の第1の実施形態におけるテールを有す
るバンプ電極の形成工程を説明する図である。
FIG. 4 is a diagram illustrating a step of forming a bump electrode having a tail according to the first embodiment of the present invention.

【図5】本発明の第1の実施形態におけるテールを有す
るバンプ電極の寸法を示す図である。
FIG. 5 is a diagram showing dimensions of bump electrodes having tails according to the first embodiment of the present invention.

【図6】本発明の第2の実施形態の主要部の構成および
実装工程を示す図である。
FIG. 6 is a diagram showing a configuration and a mounting process of a main part of a second embodiment of the present invention.

【図7】本発明の第2の実施形態の構成および実装工程
を示す図である。
FIG. 7 is a diagram showing a configuration and a mounting process of a second embodiment of the present invention.

【図8】本発明の第3の実施形態の構成および実装工程
を示す図である。
FIG. 8 is a diagram showing a configuration and a mounting process of a third embodiment of the present invention.

【図9】従来のフリップチップ方式による半導体素子を
回路基板に実装した構成を示す図である。
FIG. 9 is a diagram showing a configuration in which a semiconductor element by a conventional flip chip method is mounted on a circuit board.

【符号の説明】[Explanation of symbols]

101 回路基板 102 内層回路 103 実装用パッド 105 半導体素子 106 テール 107 バンプ電極 108 電極 109 封止樹脂 110 底面 101 Circuit Board 102 Inner Layer Circuit 103 Mounting Pad 105 Semiconductor Element 106 Tail 107 Bump Electrode 108 Electrode 109 Sealing Resin 110 Bottom

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 複数の突起電極を備える半導体装置を、
実装用パッドが形成された基板に実装する方法であっ
て、 前記基板上の半導体装置が実装される領域上に、前記突
起電極と前記実装用パッドとを接触させる前に、封止樹
脂を予め供給し、 前記突起電極を前記実装用パッドに押しつけて、前記突
起電極の先端を該突起電極と前記実装用パッドとの接触
面積が点から面に拡大するように変形させた後、前記封
止樹脂を硬化させることを特徴とする半導体装置の実装
方法。
1. A semiconductor device comprising a plurality of protruding electrodes,
A method of mounting on a substrate on which mounting pads are formed, in which a sealing resin is preliminarily applied to a region where a semiconductor device on the substrate is mounted, before contacting the protruding electrodes with the mounting pads. Supply, press the protruding electrode against the mounting pad, deform the tip of the protruding electrode so that the contact area between the protruding electrode and the mounting pad expands from a point to a surface, and then seal A method for mounting a semiconductor device, which comprises curing a resin.
【請求項2】 前記突起電極は、変形前は、略球状の部
材と該球状部材の先端に配置された尖状の部材とを備え
ており、 該突起電極を前記実装用パッドに押しつけることによっ
て、前記尖状部材をつぶすように変形することを特徴と
する前記請求項1に記載の半導体装置の実装方法。
2. The projecting electrode comprises a substantially spherical member and a pointed member arranged at the tip of the spherical member before deformation, and the projecting electrode is pressed against the mounting pad. The method of mounting a semiconductor device according to claim 1, wherein the pointed member is deformed so as to be crushed.
【請求項3】 前記尖状部材を、変形前の該尖状部材の
長さの少なくとも50パーセント以下の長さになるま
で、変形することを特徴とする前記請求項2に記載の半
導体装置の実装方法。
3. The semiconductor device according to claim 2, wherein the pointed member is deformed to a length of at least 50% or less of a length of the pointed member before deformation. How to implement.
【請求項4】 前記封止樹脂に対し所定の熱量を加える
か、あるいは該封止樹脂に対し紫外光を照射することに
よって、該封止樹脂を硬化することを特徴とする前記請
求項1に記載の半導体装置の実装方法。
4. The encapsulating resin is cured by applying a predetermined amount of heat to the encapsulating resin or by irradiating the encapsulating resin with ultraviolet light. A method for mounting a semiconductor device as described above.
【請求項5】 基板上の半導体装置が実装される領域上
に、前記半導体装置に設けられる突起電極と前記基板上
に形成された実装用パッドとを接触させる前に封止樹脂
を予め供給し、 前記突起電極を前記実装用パッドに押しつけて、前記突
起電極の先端を該突起電極と前記実装用パッドとの接触
面積が点から面に拡大するように変形させた後、前記封
止樹脂を硬化させる半導体装置の実装方法であって、 前記基板は、その内部に、前記突起電極から前記実装用
パッドへ加わる押圧力を分散させる内層部材を有する積
層構造により形成され、 前記実装用パッドは、凹部を有し、該凹部の底面が前記
内部導電層の一部と接触するものであって、 前記突起電極は、前記実装用パッドの凹部底面に対して
加圧圧接されることを特徴とする半導体装置の実装方
法。
5. A sealing resin is pre-supplied on a region of a substrate on which a semiconductor device is mounted, before a bump electrode provided on the semiconductor device and a mounting pad formed on the substrate are brought into contact with each other. After pressing the protruding electrode against the mounting pad and deforming the tip of the protruding electrode so that the contact area between the protruding electrode and the mounting pad expands from a point to a surface, the sealing resin is applied. A mounting method of a semiconductor device to be cured, wherein the substrate is formed by a laminated structure having an inner layer member that disperses a pressing force applied from the protruding electrode to the mounting pad, wherein the mounting pad is A concave portion, a bottom surface of the concave portion being in contact with a part of the internal conductive layer, and the bump electrode being pressed against the concave portion bottom surface of the mounting pad. Semiconductor device Implementation method.
【請求項6】 前記実装用パッドの凹部の開口部分の大
きさは、該凹部の底面の大きさよりも小さく形成されて
おり、 前記突起電極の先端の径を、前記開口部分の径よりも大
きくなるまで、該先端を変形させることを特徴とする前
記請求項5に記載の半導体装置の実装方法。
6. The size of the opening of the recess of the mounting pad is smaller than the size of the bottom of the recess, and the diameter of the tip of the bump electrode is larger than the diameter of the opening. The mounting method for a semiconductor device according to claim 5, wherein the tip is deformed until the above.
【請求項7】 半導体装置を基板に実装した構造であっ
て、 前記基板上に設けられる実装用パッドと、 前記半導体装置の前記基板側の面に設けられ、略球状の
第1の部分と該第1の部分の先端に配置され前記実装用
パッドに加圧圧接されて該実装用パッドとの接触部分が
点から面へと拡大するように変形された第2の部分とを
含んで形成される複数の突起電極と、 前記基板と前記半導体装置との間に配置される封止樹脂
とを備える半導体装置の実装構造。
7. A structure in which a semiconductor device is mounted on a substrate, wherein a mounting pad provided on the substrate, a substantially spherical first portion provided on a surface of the semiconductor device on the substrate side, and And a second portion which is arranged at the tip of the first portion and is pressed against the mounting pad and deformed so that the contact portion with the mounting pad expands from a point to a surface. A mounting structure for a semiconductor device, comprising: a plurality of protruding electrodes; and a sealing resin disposed between the substrate and the semiconductor device.
【請求項8】 前記第2の部分は、変形前は、尖状形状
を有しており、変形後の長さは、該変形前の長さの少な
くとも50パーセント以下であることを特徴とする前記
請求項7に記載の半導体装置の実装構造。
8. The second portion has a pointed shape before deformation, and the length after deformation is at least 50% or less of the length before deformation. The semiconductor device mounting structure according to claim 7.
【請求項9】 前記基板は、その内部に導電層を有する
積層構造により形成され、 前記実装用パッドは、凹部を有し、該凹部の底面が前記
内部導電層の一部と接触し、 前記突起電極は、前記実装用パッドの凹部底面に接触し
ていることを特徴とする前記請求項8に記載の半導体装
置の実装構造。
9. The substrate is formed by a laminated structure having a conductive layer therein, the mounting pad has a recess, and a bottom surface of the recess is in contact with a part of the internal conductive layer, 9. The mounting structure for a semiconductor device according to claim 8, wherein the protruding electrode is in contact with the bottom surface of the recess of the mounting pad.
【請求項10】 前記実装用パッドの凹部の開口部分の
大きさは、該凹部の底面の大きさよりも小さく形成され
ており、 前記第2の部分の径は、前記開口部分の径よりも大きい
ことを特徴とする前記請求項9に記載の半導体装置の実
装構造。
10. The size of the opening of the recess of the mounting pad is smaller than the size of the bottom of the recess, and the diameter of the second part is larger than the diameter of the opening. 10. The mounting structure for a semiconductor device according to claim 9, wherein the mounting structure is a semiconductor device.
JP19215096A 1995-07-27 1996-07-22 Semiconductor device mounting method and mounting structure Expired - Lifetime JP2770821B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19215096A JP2770821B2 (en) 1995-07-27 1996-07-22 Semiconductor device mounting method and mounting structure

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP19173795 1995-07-27
JP7-191737 1995-07-27
JP19215096A JP2770821B2 (en) 1995-07-27 1996-07-22 Semiconductor device mounting method and mounting structure

Publications (2)

Publication Number Publication Date
JPH0997816A true JPH0997816A (en) 1997-04-08
JP2770821B2 JP2770821B2 (en) 1998-07-02

Family

ID=26506870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19215096A Expired - Lifetime JP2770821B2 (en) 1995-07-27 1996-07-22 Semiconductor device mounting method and mounting structure

Country Status (1)

Country Link
JP (1) JP2770821B2 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0821408A2 (en) * 1996-07-25 1998-01-28 Sharp Kabushiki Kaisha A structure of mounting a semiconductor element onto a substrate and a mounting method thereof
WO1998030073A1 (en) * 1996-12-27 1998-07-09 Matsushita Electric Industrial Co., Ltd. Method and device for mounting electronic component on circuit board
US6214446B1 (en) 1998-03-03 2001-04-10 Nec Corporation Resin film and a method for connecting electronic parts by the use thereof
JP2001237268A (en) * 2000-02-22 2001-08-31 Nec Corp Method for mounting semiconductor element and apparatus for manufacturing the same
JP2003526937A (en) * 2000-03-10 2003-09-09 チップパック,インク. Flip chip bonding structure
US6674178B1 (en) 1999-09-20 2004-01-06 Nec Electronics Corporation Semiconductor device having dispersed filler between electrodes
EP1204136A4 (en) * 1999-07-16 2004-10-13 Matsushita Electric Ind Co Ltd Package of semiconductor device and method of manufacture thereof
US7687319B2 (en) 2005-10-06 2010-03-30 Fujitsu Microelectronics Limited Semiconductor device and manufacturing method thereof
US7755203B2 (en) 2006-08-18 2010-07-13 Fujitsu Semiconductor Limited Circuit substrate and semiconductor device
WO2011037185A1 (en) * 2009-09-24 2011-03-31 京セラ株式会社 Mounting substrate, light emitting body, and method for manufacturing mounting substrate
JP4768188B2 (en) * 2000-01-14 2011-09-07 東レエンジニアリング株式会社 Chip mounting method and apparatus
JP2012109481A (en) * 2010-11-19 2012-06-07 Toray Ind Inc Method of manufacturing semiconductor device and semiconductor device
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0821408A3 (en) * 1996-07-25 1999-12-01 Sharp Kabushiki Kaisha A structure of mounting a semiconductor element onto a substrate and a mounting method thereof
EP0821408A2 (en) * 1996-07-25 1998-01-28 Sharp Kabushiki Kaisha A structure of mounting a semiconductor element onto a substrate and a mounting method thereof
US6981317B1 (en) 1996-12-27 2006-01-03 Matsushita Electric Industrial Co., Ltd. Method and device for mounting electronic component on circuit board
WO1998030073A1 (en) * 1996-12-27 1998-07-09 Matsushita Electric Industrial Co., Ltd. Method and device for mounting electronic component on circuit board
US6214446B1 (en) 1998-03-03 2001-04-10 Nec Corporation Resin film and a method for connecting electronic parts by the use thereof
US6311888B1 (en) 1998-03-03 2001-11-06 Nec Corporation Resin film and a method for connecting electronic parts by the use thereof
US7090482B2 (en) 1999-07-16 2006-08-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device package manufacturing method and semiconductor device package manufactured by the method
EP1204136A4 (en) * 1999-07-16 2004-10-13 Matsushita Electric Ind Co Ltd Package of semiconductor device and method of manufacture thereof
US6674178B1 (en) 1999-09-20 2004-01-06 Nec Electronics Corporation Semiconductor device having dispersed filler between electrodes
JP4768188B2 (en) * 2000-01-14 2011-09-07 東レエンジニアリング株式会社 Chip mounting method and apparatus
JP2001237268A (en) * 2000-02-22 2001-08-31 Nec Corp Method for mounting semiconductor element and apparatus for manufacturing the same
JP4903966B2 (en) * 2000-03-10 2012-03-28 スタッツ・チップパック・インコーポレイテッド Flip chip bonding structure and method for forming flip chip bonding structure
US7994636B2 (en) 2000-03-10 2011-08-09 Stats Chippac, Ltd. Flip chip interconnection structure
JP2003526937A (en) * 2000-03-10 2003-09-09 チップパック,インク. Flip chip bonding structure
US8697490B2 (en) 2000-03-10 2014-04-15 Stats Chippac, Ltd. Flip chip interconnection structure
US10388626B2 (en) 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
US7687319B2 (en) 2005-10-06 2010-03-30 Fujitsu Microelectronics Limited Semiconductor device and manufacturing method thereof
US7755203B2 (en) 2006-08-18 2010-07-13 Fujitsu Semiconductor Limited Circuit substrate and semiconductor device
WO2011037185A1 (en) * 2009-09-24 2011-03-31 京セラ株式会社 Mounting substrate, light emitting body, and method for manufacturing mounting substrate
JPWO2011037185A1 (en) * 2009-09-24 2013-02-21 京セラ株式会社 Mounting substrate, light emitter, and manufacturing method of mounting substrate
JP2012109481A (en) * 2010-11-19 2012-06-07 Toray Ind Inc Method of manufacturing semiconductor device and semiconductor device

Also Published As

Publication number Publication date
JP2770821B2 (en) 1998-07-02

Similar Documents

Publication Publication Date Title
US6449838B2 (en) Method of mounting a semiconductor device to a substrate
US5574311A (en) Device having pins formed of hardened mixture of conductive metal particle and resin
US7015131B2 (en) Semiconductor device using bumps, method for fabricating same, and method for forming bumps
JP3297254B2 (en) Semiconductor package and manufacturing method thereof
JP4056424B2 (en) Manufacturing method of semiconductor device
JP2000036520A (en) Method for mounting flip chip and device therefor
JP2770821B2 (en) Semiconductor device mounting method and mounting structure
JPH1145954A (en) Method and structure for flip-chip connection and electronic device employing it
KR100376336B1 (en) Semiconductor device and method for manufacturing same
US6528889B1 (en) Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
JP3262728B2 (en) Semiconductor device and manufacturing method thereof
JP2003273160A (en) Semiconductor mounted module
JP3116926B2 (en) Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method
JP2002170853A (en) Flip chip mounting method
JP3319269B2 (en) Electronic component joining method
JPH09172021A (en) Semiconductor device and manufacturing method and packaging method thereof
JPH07153796A (en) Semiconductor mounting device and manufacturing method of it
JP2004247621A (en) Semiconductor device and its manufacturing method
JP3552660B2 (en) Method for manufacturing semiconductor device
JP2002016104A (en) Mounting method of semiconductor device and manufacturing method of semiconductor device mounted assembly
JP4026732B2 (en) Semiconductor device and manufacturing method thereof
JPH11204572A (en) Mounting structure of semiconductor device and manufacture thereof
JP3168998B2 (en) Element mounting method and semiconductor device
JP2009212492A (en) Method of manufacturing package substrate, and method of manufacturing semiconductor package
JP2001127102A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19980317

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080417

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090417

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100417

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110417

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 15

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 15

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140417

Year of fee payment: 16

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term