JP2002016168A - Substrate for mounting and semiconductor module using the same - Google Patents
Substrate for mounting and semiconductor module using the sameInfo
- Publication number
- JP2002016168A JP2002016168A JP2000194401A JP2000194401A JP2002016168A JP 2002016168 A JP2002016168 A JP 2002016168A JP 2000194401 A JP2000194401 A JP 2000194401A JP 2000194401 A JP2000194401 A JP 2000194401A JP 2002016168 A JP2002016168 A JP 2002016168A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor device
- electrode
- electrode pad
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は情報通信分野や半導
体分野等において半導体素子や半導体素子を半導体素子
収納用パッケージに収容して成る半導体デバイス等の半
導体装置をいわゆるフリップチップ実装法により実装す
るのに好適な、実装の際の信頼性と良品率を高めた実装
用基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device such as a semiconductor device or a semiconductor device in which a semiconductor device is housed in a semiconductor device housing package by a so-called flip-chip mounting method in the field of information communication and the semiconductor field. More particularly, the present invention relates to a mounting board which is suitable for mounting and has improved reliability and non-defective rate at the time of mounting.
【0002】[0002]
【従来の技術】近年、回路基板や半導体素子収納用パッ
ケージ等の配線基板として用いられる実装用基板に半導
体素子や半導体素子を収容した半導体デバイス等の半導
体装置を実装する方法として、いわゆるフリップチップ
実装法が多用されるようになっている。この実装法は、
例えば、半導体装置の実装面側の電極上に金や半田材料
等から成る突起電極を設け、一方、この半導体装置が搭
載される実装用基板にはこの突起電極に対向する位置に
電極パッドを設けておき、半導体装置の突起電極と実装
用基板の電極パッドとを位置合わせして半導体装置を載
置した後に加熱加圧することにより、または半導体装置
を介して突起電極と電極パッドに超音波エネルギーを印
加することにより突起電極と電極パッドとを接合して、
半導体装置を実装用基板にいわゆるフェースダウンで実
装するものである。2. Description of the Related Art In recent years, as a method of mounting a semiconductor device such as a semiconductor device or a semiconductor device containing a semiconductor device on a mounting substrate used as a wiring substrate such as a circuit board or a package for housing a semiconductor device, a so-called flip-chip mounting method is used. The law is becoming heavily used. This technique is
For example, a protruding electrode made of gold, a solder material, or the like is provided on an electrode on a mounting surface side of a semiconductor device, and an electrode pad is provided on a mounting substrate on which the semiconductor device is mounted, at a position facing the protruding electrode. In advance, the semiconductor device is placed with the projecting electrodes of the semiconductor device and the electrode pads of the mounting substrate aligned and then heated and pressed, or ultrasonic energy is applied to the projecting electrodes and the electrode pads via the semiconductor device. By applying, the protruding electrode and the electrode pad are joined,
The semiconductor device is mounted face-down on a mounting substrate.
【0003】このようなフリップチップ実装において実
装用基板の電極パッドと半導体装置の突起電極とを機械
的に接合し、かつ電気的に接続する方法には、様々な方
法が用いられている。In such flip-chip mounting, various methods are used for mechanically bonding and electrically connecting the electrode pads of the mounting substrate and the protruding electrodes of the semiconductor device.
【0004】例えば、図4(a)に側面図で示すよう
に、半導体装置としての半導体素子1を、その下面に形
成された突起電極2の先端に例えば銀ペースト5を塗布
して実装用基板3の上面の素子実装領域に形成された電
極パッド4と当接させて載置した後、同図(b)に同様
の側面図で示すように、半導体素子1の上からツール
(加圧加熱手段)6により加熱加圧して、突起電極2と
電極パッド4とを銀ペースト5等を介して接続する方法
がある。For example, as shown in a side view of FIG. 4A, a semiconductor element 1 as a semiconductor device is prepared by applying, for example, a silver paste 5 to the tip of a protruding electrode 2 formed on the lower surface thereof. 3 is placed in contact with the electrode pad 4 formed in the element mounting area on the upper surface of the semiconductor element 1, and as shown in the same side view in FIG. Means 6) There is a method in which the projecting electrode 2 and the electrode pad 4 are connected via the silver paste 5 or the like by heating and pressing by 6.
【0005】さらに、半導体素子の突起電極を金で形成
し、実装用基板の搭載部に形成された電極パッドも金で
形成して、銀ペーストやはんだ材料を用いずに突起電極
と電極パッドとを位置合わせしてこれに超音波をかける
ことが可能なツールにより超音波を印加して、超音波と
加熱のみで接続する方法もある。Further, the protruding electrode of the semiconductor element is formed of gold, and the electrode pad formed on the mounting portion of the mounting substrate is also formed of gold, so that the protruding electrode and the electrode pad can be formed without using silver paste or a solder material. There is also a method in which ultrasonic waves are applied by a tool capable of aligning the ultrasonic waves and applying ultrasonic waves thereto, and the ultrasonic waves are connected to the ultrasonic waves only by heating.
【0006】これらの方法において半導体装置を信頼性
良く実装するためには、半導体装置の突起電極の高さが
一様に揃っていることと、実装用基板上の電極パッドの
高さが揃っていることおよびそれら電極パッドの表面が
平坦になっていることが非常に重要となる。In order to mount a semiconductor device with high reliability in these methods, it is necessary that the heights of the projecting electrodes of the semiconductor device are uniform and the heights of the electrode pads on the mounting board are uniform. It is very important that the electrode pads have a flat surface.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、上記の
ようなフリップチップ実装法に用いられる従来の実装用
基板においては、半導体装置に形成された突起電極には
わずかな高さばらつきがあることに加えて、実装用基板
上に形成された電極パッドの高さばらつきおよび平坦度
ばらつきがあったため、これに半導体装置の突起電極を
接合させる際に、突起電極と電極パッドとを良好に接触
させることができなくなり、突起電極と電極パッドとの
接続不良を発生させることがあるという問題点があっ
た。However, in the conventional mounting substrate used in the above-described flip-chip mounting method, the bump electrodes formed on the semiconductor device have a slight variation in height. As a result, the height variation and the flatness variation of the electrode pads formed on the mounting substrate were varied, so that when the bump electrodes of the semiconductor device were joined to the bumps, the bump electrodes and the electrode pads could be brought into good contact. There is a problem in that the connection between the protruding electrode and the electrode pad may be failed.
【0008】これに対しては、半導体装置の突起電極と
実装用基板の電極パッドとを位置合わせする前に、金属
やガラス等から成る平坦度の良いステージ上で半導体装
置の突起電極を加圧してレベリングすることにより、突
起電極の高さを揃えることが行なわれていた。In order to cope with this, before the projecting electrodes of the semiconductor device are aligned with the electrode pads of the mounting substrate, the projecting electrodes of the semiconductor device are pressed on a stage of good flatness made of metal, glass or the like. In this case, the height of the protruding electrodes is made uniform by leveling.
【0009】しかしながら、実装用基板側については、
その電極パッドの高さを揃えてしかも表面を平坦にする
ためには、十分に平坦度を小さくした基板を用いて、さ
らに電極パッドや配線導体を薄膜で形成して高さおよび
平坦度を制御することが必要であった。そこで、基板表
面の平坦度を小さくために鏡面研磨を行ない、また薄膜
プロセスによって電極パッドや配線導体を形成すること
により、基板の平坦度を高め、電極パッドの高さばらつ
きと平坦度ばらつきもない実装用基板としての配線基板
や半導体素子収納用パッケージを作製することが行なわ
れている。However, on the mounting substrate side,
In order to make the height of the electrode pads uniform and to make the surface flat, use a substrate with a sufficiently low flatness, and further control the height and flatness by forming electrode pads and wiring conductors with thin films. It was necessary to do. Therefore, mirror polishing is performed to reduce the flatness of the substrate surface, and the flatness of the substrate is increased by forming electrode pads and wiring conductors by a thin film process, and there is no variation in height and flatness of the electrode pads. 2. Description of the Related Art A wiring board as a mounting board and a package for housing a semiconductor element have been manufactured.
【0010】しかしながら、この場合には、そのような
実装用基板の作製には非常に複雑かつ長い工程が必要と
なり、実装用基板の作製に長時間を要し、作製のコスト
も高くなってしまうという問題点があった。However, in this case, the production of such a mounting substrate requires a very complicated and long process, and the production of the mounting substrate takes a long time and the production cost increases. There was a problem.
【0011】本発明は上記従来技術における問題点に鑑
みてなされたものであり、その目的は、半導体素子を始
めとする半導体装置を配線基板または半導体素子収納用
パッケージ等に用いられる実装用基板にいわゆるフリッ
プチップ実装する際に、信頼性良くかつ高い良品率で半
導体装置の突起電極と実装用基板の電極パッドとを接合
でき、しかも短時間かつ低コストで作製可能な実装用基
板を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a semiconductor device including a semiconductor element in a wiring board or a mounting board used for a package for housing a semiconductor element. To provide a mounting substrate that can be reliably and at a high yield rate and that can bond a bump electrode of a semiconductor device to an electrode pad of a mounting substrate during so-called flip-chip mounting, and that can be manufactured in a short time and at low cost. It is in.
【0012】また、本発明の目的は、信頼性良くかつ高
い良品率で半導体装置の突起電極と実装用基板の電極パ
ッドとを接合してフリップチップ実装することができ、
短時間かつ低コストで作製可能な実装用基板を用いた半
導体モジュールを提供することにある。Another object of the present invention is to provide a flip chip mounting method in which a protruding electrode of a semiconductor device and an electrode pad of a mounting substrate are bonded with high reliability and a high yield rate.
An object of the present invention is to provide a semiconductor module using a mounting substrate that can be manufactured in a short time and at low cost.
【0013】[0013]
【課題を解決するための手段】本発明の実装用基板は、
絶縁基板の上面に、下面に突起電極を有する半導体装置
が実装される装置実装領域を備え、この装置実装領域に
前記突起電極と対応する電極パッドが形成された実装用
基板であって、前記電極パッドの表面が加圧平坦化手段
の平坦面で加圧して平坦にされていることを特徴とする
ものである。According to the present invention, there is provided a mounting board comprising:
A mounting substrate on which a semiconductor device having a projecting electrode on a lower surface is mounted on an upper surface of an insulating substrate, and an electrode pad corresponding to the projecting electrode is formed in the device mounting region; The surface of the pad is flattened by pressing with a flat surface of the pressing flattening means.
【0014】また、本発明の実装用基板は、上記構成に
おいて、前記装置実装領域に前記電極パッドと電気的に
接続された配線導体が形成され、この配線導体の表面も
前記加圧平坦化手段の平坦面で加圧して平坦にされてい
ることを特徴とするものである。Further, in the mounting board of the present invention, in the above structure, a wiring conductor electrically connected to the electrode pad is formed in the device mounting area, and the surface of the wiring conductor is also formed by the pressing flattening means. Characterized by being flattened by pressing on the flat surface.
【0015】また、本発明の半導体モジュールは、上記
各構成の実装用基板の前記装置実装領域に、下面に突起
電極を有する半導体装置を、前記突起電極を前記電極パ
ッドに接合させて実装したことを特徴とするものであ
る。Further, in the semiconductor module of the present invention, a semiconductor device having a protruding electrode on a lower surface is mounted in the device mounting area of the mounting substrate having the above-described configuration by bonding the protruding electrode to the electrode pad. It is characterized by the following.
【0016】[0016]
【発明の実施の形態】本発明の実装用基板によれば、装
置実装領域に形成された、半導体装置の突起電極と対向
する電極パッドの表面が、加圧平坦化手段の平坦面で加
圧して平坦にされていることから、従来のように複雑か
つ長い工程で電極パッドの表面が平坦な実装用基板を作
製するのに対して、平坦面が必要な装置実装領域の電極
パッドの表面だけについて、厚膜印刷法等で形成された
電極パッドに対しても装置実装領域の全体にわたって簡
単かつ容易に表面の高さを揃えた所望の平坦な実装面を
形成することができるので、半導体装置の突起電極を安
定して確実に接合させることができ、半導体装置を信頼
性良くまた高い良品率で実装することができる。According to the mounting substrate of the present invention, the surface of the electrode pad formed in the device mounting area and facing the bump electrode of the semiconductor device is pressed by the flat surface of the pressing flattening means. Because of the flatness of the electrode pad, a conventional mounting substrate with a flat surface of the electrode pad is manufactured in a complicated and long process, but only the surface of the electrode pad in the device mounting area where a flat surface is required. As for the semiconductor device, it is possible to easily and easily form a desired flat mounting surface having a uniform surface height over the entire device mounting region even with respect to an electrode pad formed by a thick film printing method or the like. Can be bonded stably and reliably, and the semiconductor device can be mounted with high reliability and a high yield rate.
【0017】また、装置実装領域に電極パッドと電気的
に接続された配線導体が形成されている場合に、電極パ
ッドとともにその配線導体の表面も加圧平坦化手段の平
坦面で加圧して平坦にしたことにより、平坦面が必要な
装置実装領域の電極パッドおよび配線導体の表面だけに
ついて、厚膜印刷法等で形成された配線導体に対しても
電極パッドとともに装置実装領域の全体にわたって簡単
かつ容易に表面の高さを揃えた所望の平坦な実装面を形
成することができるので、装置実装領域の配線導体の表
面の高さばらつきや平坦度ばらつきが原因で発生する配
線導体と半導体装置との接触や短絡等の不具合が発生す
ることがなく、半導体装置の突起電極を安定して確実に
接合させることができ、半導体装置を信頼性良くまた高
い良品率で実装することができる。When a wiring conductor electrically connected to the electrode pad is formed in the device mounting area, the surface of the wiring conductor is flattened by pressing the flat surface of the pressing flattening means together with the electrode pad. With this arrangement, only the surface of the electrode pads and wiring conductors in the device mounting area where a flat surface is required, the wiring conductors formed by the thick film printing method and the electrode pads can be easily and simply spread over the entire device mounting area. Since a desired flat mounting surface having the same surface height can be easily formed, the wiring conductor and the semiconductor device, which are generated due to the height variation and the flatness variation of the surface of the wiring conductor in the device mounting area, can be formed. The bumps of the semiconductor device can be stably and surely joined without causing troubles such as contact or short circuit of the semiconductor device, and the semiconductor device can be mounted with high reliability and a high yield rate. It is possible.
【0018】また、本発明の半導体モジュールによれ
ば、このような本発明の実装用基板に半導体装置を実装
していることから、半導体装置の突起電極と実装用基板
の電極パッドとを安定かつ確実に接合して良好な接続状
態で半導体装置を実装することができ、信頼性が高い半
導体モジュールとなり、また高い良品率で作製すること
ができる。According to the semiconductor module of the present invention, since the semiconductor device is mounted on the mounting substrate of the present invention, the projecting electrodes of the semiconductor device and the electrode pads of the mounting substrate can be stably and reliably mounted. The semiconductor device can be mounted in a good connection state by reliable bonding, a highly reliable semiconductor module can be manufactured, and a high yield rate can be achieved.
【0019】以下、図面に基づいて本発明を詳細に説明
する。図1は本発明の実装用基板およびそれを用いた半
導体モジュールの実施の形態の一例を示す側面図であ
り、実装用基板3の装置実装領域に半導体装置1を実装
している状態を示している。Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a side view showing an example of an embodiment of a mounting substrate of the present invention and a semiconductor module using the same, showing a state where the semiconductor device 1 is mounted in a device mounting area of the mounting substrate 3. I have.
【0020】図1において、1は半導体素子や半導体素
子を半導体素子収納用パッケージに収容して成る半導体
デバイス等の半導体装置であり、下面に複数の突起電極
2が形成されている。3は絶縁基板に所定の回路配線が
形成されて成り、上面に半導体装置1が実装される装置
実装領域を備える実装用基板、4は実装用基板3の上面
の装置実装領域に半導体装置1の突起電極2にそれぞれ
対応させて形成された複数の電極パッドである。この電
極パッド4は薄膜プロセスを用いずに例えば厚膜印刷法
等により形成され、装置実装領域から外部に導出するた
めの配線導体も一体的に形成されている。このように厚
膜印刷法等により形成された電極パッド4ならびに配線
導体は、装置実装領域の外側で示されているように、通
常は微視的にみて膜厚にばらつきがあるため、形成され
たままの状態ではその表面は平坦となっていない。本発
明の実装用基板3においては、突起電極2が接合される
電極パッド4の表面は、半導体装置1の実装前に、加圧
平坦化手段(図示せず)の平坦面を押し当てて加圧する
ことによって微視的にみても平坦にされていることか
ら、装置実装領域の電極パッド4は表面が平坦な断面形
状をしている。In FIG. 1, reference numeral 1 denotes a semiconductor device such as a semiconductor device or a semiconductor device in which the semiconductor device is housed in a semiconductor device housing package, and a plurality of projecting electrodes 2 are formed on the lower surface. Reference numeral 3 denotes a mounting substrate having predetermined circuit wiring formed on an insulating substrate, and a mounting substrate having a device mounting area on the upper surface on which the semiconductor device 1 is mounted. There are a plurality of electrode pads formed corresponding to the protruding electrodes 2, respectively. The electrode pad 4 is formed by, for example, a thick film printing method without using a thin film process, and a wiring conductor for leading out from the device mounting area to the outside is also integrally formed. The electrode pads 4 and the wiring conductors formed by the thick film printing method or the like as described above are usually formed because there is a variation in the film thickness microscopically, as shown outside the device mounting area. The surface is not flat when left as it is. In the mounting substrate 3 of the present invention, the surface of the electrode pad 4 to which the bump electrode 2 is bonded is pressed against the flat surface of the pressure flattening means (not shown) before the semiconductor device 1 is mounted. Since the electrode pad 4 in the device mounting area has a flat cross-sectional shape since it is flattened microscopically by pressing.
【0021】この結果、厚膜印刷法等で形成された電極
パッド4に対しても装置実装領域の全体にわたって簡単
かつ容易に表面の高さを揃えた所望の平坦な実装面を形
成することができ、突起電極2がいずれも良好な状態で
安定して電極パッド4表面に当接されて確実に接合され
ることとなり、信頼性良くかつ高い良品率で半導体装置
1を実装することができる。また、このような実装用基
板3に半導体装置1を実装して成る半導体モジュール
は、同様に信頼性が高くかつ高い良品率で作製すること
ができる。As a result, it is possible to easily and easily form a desired flat mounting surface having the same surface height over the entire device mounting area even for the electrode pad 4 formed by the thick film printing method or the like. As a result, all the protruding electrodes 2 are stably brought into contact with the surface of the electrode pad 4 in a good state and are securely joined, and the semiconductor device 1 can be mounted with high reliability and a high yield. In addition, a semiconductor module in which the semiconductor device 1 is mounted on such a mounting substrate 3 can be similarly manufactured with high reliability and a high yield.
【0022】このような本発明の実装用基板3につい
て、その装置実装領域における電極パッド4の表面を平
坦にする方法の例について、図2および図3を用いて説
明する。図2および図3は、いずれもその方法の例を示
す側面図である。An example of a method of flattening the surface of the electrode pad 4 in the device mounting area of the mounting substrate 3 of the present invention will be described with reference to FIGS. 2 and 3 are side views each showing an example of the method.
【0023】図2において、3は絶縁基板に所定の回路
配線が形成されてなる実装用基板、4は実装用基板3の
上面の装置実装領域に半導体装置1の下面の突起電極2
にそれぞれ対応させて形成された複数の電極パッドであ
る。この電極パッド4は低コストで作製できる実装用基
板3を得るため、薄膜プロセスを用いずにこれに電気的
に接続される配線導体とともに厚膜印刷法で形成されて
いるので、微視的にみて膜厚ばらつきが非常に大きくな
っている。7は実装用基板3の上面の装置実装領域とほ
ぼ同サイズの平坦面を有するように加工された加圧平坦
化手段を示している。本発明の実装用基板3において
は、その装置実装領域の電極パッド4の表面を、この加
圧平坦化手段7の平坦面で加圧することによって、所望
の高さおよび平坦度に平坦にされる。また、このような
加圧平坦化手段7によれば、装置実装領域に電極パッド
4とともにこれに電気的に接続された配線導体が形成さ
れている場合に、この配線導体の表面もその平坦面で加
圧して電極パッド4の表面と同様の高さおよび平坦度の
平坦にすることができる。In FIG. 2, reference numeral 3 denotes a mounting substrate in which predetermined circuit wiring is formed on an insulating substrate, and 4 denotes a projecting electrode 2 on the lower surface of the semiconductor device 1 in a device mounting area on the upper surface of the mounting substrate 3.
And a plurality of electrode pads respectively formed in correspondence with. The electrode pads 4 are formed by a thick-film printing method together with wiring conductors electrically connected thereto without using a thin-film process in order to obtain a mounting substrate 3 that can be manufactured at low cost. As can be seen, the film thickness variation is very large. Reference numeral 7 denotes a pressure flattening means processed to have a flat surface having substantially the same size as the device mounting area on the upper surface of the mounting substrate 3. In the mounting substrate 3 of the present invention, the surface of the electrode pad 4 in the device mounting area is flattened to a desired height and flatness by pressing the flat surface of the pressing flattening means 7. . Further, according to the pressure flattening means 7, when the electrode pad 4 and the wiring conductor electrically connected thereto are formed in the device mounting area, the surface of the wiring conductor also has a flat surface. To flatten the same height and flatness as the surface of the electrode pad 4.
【0024】図3においても、3は実装用基板、4は図
2に示すものと同様の電極パッドである。8は実装用基
板3上の電極パッド4とほぼ同サイズで同一位置に平坦
面を持つように加工された加圧平坦化手段である。この
ような加圧平坦化手段8を用いれば、装置実装領域の電
極パッド4について選択的にその表面を平坦にすること
ができる。In FIG. 3, reference numeral 3 denotes a mounting substrate, and reference numeral 4 denotes electrode pads similar to those shown in FIG. Reference numeral 8 denotes a pressure flattening means which is processed so as to have a flat surface at the same position as the electrode pad 4 on the mounting substrate 3 at substantially the same size. By using such a pressure flattening means 8, the surface of the electrode pad 4 in the device mounting area can be selectively flattened.
【0025】このような加圧平坦化手段7・8を用いて
装置実装領域の電極パッド4の表面、ならびに装置実装
領域の配線導体の表面をその平坦面で加圧することによ
り、図1に示すように、電極パッド4の表面を半導体装
置1の突起電極2が接合される面が所望の高さおよび平
坦度に揃えられた平坦なものとすることができ、この電
極パッド4に接続された配線導体の表面も高さばらつき
や凹凸をなくした平坦のものとすることができる。By pressing the surface of the electrode pad 4 in the device mounting area and the surface of the wiring conductor in the device mounting area with the flat surface by using such pressure flattening means 7 and 8 as shown in FIG. As described above, the surface of the electrode pad 4 can be made flat so that the surface to which the protruding electrode 2 of the semiconductor device 1 is joined is adjusted to a desired height and flatness, and is connected to the electrode pad 4. The surface of the wiring conductor can also be made flat without height variations or irregularities.
【0026】このように電極パッド4の表面を加圧平坦
化手段7・8で加圧して平坦にする場合、その各表面の
高さのばらつきならびに平坦度のばらつきは、例えば20
μm以内とすることが望ましい。高周波用半導体素子等
の半導体装置1についてその動作の高速化および高周波
化が進められているなか、そのような半導体装置1に設
けられる突起電極2の大きさは、直径が80μm程度、高
さが40μm程度のものが用いられるようになってきてい
る。このようなサイズの突起電極2の高さばらつきを抑
えるためにこれら突起電極2を平坦面で加圧して高さを
揃える場合、金やはんだ等から成る突起電極2を加圧し
て変形させるときはその高さの50%程度までは比較的容
易に変形させることができるが、それ以上の加圧を行な
うと半導体装置1側に変形や破壊を発生させるおそれが
ある。したがって、突起電極2の高さを揃える場合には
約20μm程度までの加圧にとどめておくことが好まし
く、このような高さの突起電極2に対して良好な接合状
態を得るためには、電極パッド4の高さばらつきならび
に平坦度ばらつきを20μm以内としておくことが望まし
い。When the surface of the electrode pad 4 is flattened by the pressing and leveling means 7 and 8 as described above, the variation in height and the variation in flatness of each surface are, for example, 20.
It is desirable to be within μm. As the operation speed and the frequency of the semiconductor device 1 such as a high-frequency semiconductor element have been increased, the size of the protruding electrode 2 provided on such a semiconductor device 1 has a diameter of about 80 μm and a height of about 80 μm. Those having a size of about 40 μm have been used. In order to suppress the variation in height of the projecting electrodes 2 having such a size, when the projecting electrodes 2 are pressed on a flat surface to make the height uniform, when the projecting electrodes 2 made of gold, solder, or the like are deformed by pressing. Deformation can be made relatively easily up to about 50% of its height, but if pressure is applied further, deformation or destruction may occur on the semiconductor device 1 side. Therefore, when the heights of the protruding electrodes 2 are made uniform, it is preferable to limit the pressure to about 20 μm. In order to obtain a good bonding state with respect to the protruding electrodes 2 having such a height, It is desirable to keep the height variation and the flatness variation of the electrode pad 4 within 20 μm.
【0027】本発明の実装用基板3において、電極パッ
ド4ならびにそれに電気的に接続される配線導体は、突
起電極2をAuで形成し、それが熱圧着等で接合される
電極パッド4の表面もAuで形成しておくことが好まし
いことから、例えばW/Ni/Auを順次積層して成る
導体やMo/Ni/Auを順次積層して成る導体等が用
いられる。In the mounting board 3 of the present invention, the electrode pad 4 and the wiring conductor electrically connected thereto are formed by forming the protruding electrode 2 of Au, and the surface of the electrode pad 4 to which it is joined by thermocompression bonding or the like. Since it is preferable that the conductor is also formed of Au, a conductor formed by sequentially laminating W / Ni / Au, a conductor formed by sequentially laminating Mo / Ni / Au, or the like is used.
【0028】また、加圧平坦化手段7・8としては、電
極パッド4の表面を加圧する平坦面を鏡面に仕上げた、
例えばセラミックツールまたはSUSや超硬合金等から
成る金属ツール等を用いればよい。As the pressure flattening means 7 and 8, the flat surface for pressing the surface of the electrode pad 4 is mirror-finished.
For example, a ceramic tool or a metal tool made of SUS or cemented carbide may be used.
【0029】加圧平坦化手段7・8で電極パッド4を平
坦にする際の加圧の大きさとしては、電極パッド4の材
料や大きさ・厚み等に応じ、また所望の高さばらつきや
平坦度ばらつきの値に応じて適宜設定すればよい。ま
た、加圧する際に同時に電極パッド4を加熱して行なっ
てもよい。The magnitude of the pressure when the electrode pads 4 are flattened by the pressure flattening means 7 and 8 depends on the material, size, thickness, etc. of the electrode pads 4, as well as desired height variations and the like. What is necessary is just to set suitably according to the value of the flatness variation. Further, the electrode pad 4 may be heated at the same time as the pressing.
【0030】[0030]
【実施例】次に、本発明の実装用基板およびそれを用い
た半導体モジュールについて具体例を説明する。Next, specific examples of the mounting board of the present invention and a semiconductor module using the same will be described.
【0031】まず、実装用基板の絶縁基板として厚さ0.
6mmのアルミナセラミック基板を用い、この基板上の
装置実装領域に、半導体装置としての半導体素子の下面
に形成された突起電極と対向する位置に表面のAu層の
膜厚が5μmで全体の膜厚が25μmのW/Ni/Au層
から成る電極パッドを設けた。また、装置実装領域に電
極パッドの他に同じく表面のAu層の膜厚が5μmで全
体の膜厚が25μmのW/Ni/Au層から成るバイアス
配線および高周波伝送用のRF配線も設けた。この電極
パッド・バイアス配線およびRF配線は、いずれも薄膜
プロセスを用いず、厚膜印刷法で形成した。First, as the insulating substrate of the mounting substrate, a thickness of 0.
A 6 mm alumina ceramic substrate was used. In the device mounting area on the substrate, the Au layer on the surface was 5 μm thick at a position facing the protruding electrodes formed on the lower surface of the semiconductor element as the semiconductor device. Was provided with an electrode pad made of a 25 μm W / Ni / Au layer. In addition, in the device mounting area, in addition to the electrode pads, a bias wiring and an RF wiring for high-frequency transmission were also formed of a W / Ni / Au layer having an Au layer on the surface having a thickness of 5 μm and an overall thickness of 25 μm. Each of the electrode pad / bias wiring and the RF wiring was formed by a thick film printing method without using a thin film process.
【0032】一方、半導体装置としての半導体素子は、
素子材料が厚さ0.1mmのGaAsであり、その下面に
直径が60μmの金から成る複数の突起電極が形成されて
いるものを用いた。また、装置実装領域の電極パッドの
表面を平坦にするための加圧平坦化手段には、半導体素
子と同サイズで表面を鏡面研磨した平坦面を有するセラ
ミックツールを用意した。On the other hand, a semiconductor element as a semiconductor device
The device material used was GaAs having a thickness of 0.1 mm, on the lower surface of which a plurality of protruding electrodes made of gold having a diameter of 60 μm were formed. Further, as a pressure flattening means for flattening the surface of the electrode pad in the device mounting area, a ceramic tool having the same size as the semiconductor element and having a flat surface whose surface was mirror-polished was prepared.
【0033】そして、この実装用基板をフリップチップ
実装機のステージに載せ、このセラミックツールを実装
機のチップ実装用ヘッドに搭載して、約200N(SI単
位系で表示する必要があります。1kgfは約9.8Nで
す。)の加圧力で装置実装領域の電極パッドおよび配線
導体の表面を加圧して平坦にし、それらの平坦度および
高さばらつきを向上させた。Then, the mounting substrate is mounted on a stage of a flip chip mounting machine, and the ceramic tool is mounted on a chip mounting head of the mounting machine, and it is necessary to display about 200 N (in SI unit system. The surface of the electrode pads and wiring conductors in the device mounting area was flattened with a pressure of about 9.8 N.) to improve their flatness and height variation.
【0034】その工程の後、基板を200℃に加熱しなが
ら、半導体素子を位置合わせして各突起電極をそれぞれ
に対応する電極パッドに当接させ、超音波を半導体素子
に印加することにより突起電極を電極パッドに接合して
半導体素子をフリップチップ実装し、本発明の実装用基
板を用いた本発明の半導体モジュールAを作製した。After the step, while the substrate is heated to 200 ° C., the semiconductor elements are aligned, and the respective projecting electrodes are brought into contact with the corresponding electrode pads, and ultrasonic waves are applied to the semiconductor elements. The semiconductor element was flip-chip mounted by bonding the electrode to the electrode pad, and the semiconductor module A of the present invention using the mounting substrate of the present invention was manufactured.
【0035】また、比較例として、上記と同じ半導体素
子と実装用基板を用いて、装置実装領域の電極パッドの
表面を平坦にする工程を行なわなかったものを用意し
た。この実装用基板をフリップチップ実装機のステージ
に載せ、基板を200℃に加熱しながら、半導体素子を位
置合わせして各突起電極をそれぞれに対応する電極パッ
ドに当接させ、超音波を半導体素子に印加することによ
り突起電極を電極パッドに接合して半導体素子をフリッ
プチップ実装し、半導体モジュールBを作製した。As a comparative example, a device was prepared using the same semiconductor element and mounting substrate as described above, but without performing the step of flattening the surface of the electrode pad in the device mounting area. This mounting substrate is placed on the stage of a flip chip mounting machine, and while the substrate is heated to 200 ° C., the semiconductor elements are aligned and each protruding electrode is brought into contact with the corresponding electrode pad, and ultrasonic waves are applied to the semiconductor element. The semiconductor element was flip-chip mounted by bonding the protruding electrode to the electrode pad by applying a voltage to the semiconductor chip B, thereby producing a semiconductor module B.
【0036】さらに、他の比較例として、上記と同じ半
導体素子と薄膜プロセスにて電極パッドおよび配線導体
を形成した実装用基板を用いて、装置実装領域の電極パ
ッドの表面を平坦にするための工程を行なわなかったも
のを用意した。この実装用基板をフリップチップ実装機
のステージに載せ、基板を200℃に加熱しながら、半導
体素子を位置合わせして各突起電極をそれぞれに対応す
る電極パッドに当接させ、超音波を半導体素子に印加す
ることにより突起電極を電極パッドに接合して半導体素
子をフリップチップ実装し、半導体モジュールCを作製
した。Further, as another comparative example, using the same semiconductor element and the mounting substrate on which the electrode pads and the wiring conductors are formed by the thin film process as described above, the surface of the electrode pads in the device mounting area is flattened. Those which did not perform the process were prepared. This mounting substrate is placed on the stage of a flip chip mounting machine, and while the substrate is heated to 200 ° C., the semiconductor elements are aligned and each protruding electrode is brought into contact with the corresponding electrode pad, and ultrasonic waves are applied to the semiconductor element. The semiconductor element was flip-chip mounted by bonding the protruding electrode to the electrode pad by applying the voltage to the semiconductor chip C, thereby producing a semiconductor module C.
【0037】そして、これらの各半導体モジュールA・
BおよびCについて、実装不良の発生の有無について調
べたところ、半導体モジュールAにおいては実装不良の
発生は無かったが、半導体モジュールBにおいては約80
%の接合箇所において電極パッドの高さばらつきに起因
する接合不良が生じ、実装不良の発生が見られた。な
お、半導体モジュールCにおいては、本発明の半導体モ
ジュールAと同様に、実装不良の発生は見られなかっ
た。Each of these semiconductor modules A
When B and C were examined for the presence or absence of mounting failure, no mounting failure occurred in the semiconductor module A, but about 80% in the semiconductor module B.
%, A bonding failure was caused due to a variation in the height of the electrode pad, and a mounting failure was observed. In addition, in the semiconductor module C, as in the case of the semiconductor module A of the present invention, no occurrence of mounting failure was observed.
【0038】この結果より、本発明の半導体モジュール
Aによれば、装置実装領域を平坦にする工程を行なわな
かった半導体モジュールBと比べて、実装不良の発生が
なく、接続信頼性が向上していることが分かる。本発明
の半導体モジュールAによれば、加圧平坦化手段で装置
実装領域の電極パッドの表面を平坦化するという簡単か
つ容易な工程を行なうだけで、工程が非常に複雑でコス
トも高くかかる薄膜プロセスによる電極パッドおよび配
線導体を形成した実装用基板を用いた半導体モジュール
Cと同等の信頼性でもって半導体素子を実装できること
が分かった。As a result, according to the semiconductor module A of the present invention, as compared with the semiconductor module B in which the step of flattening the device mounting area was not performed, no mounting failure occurred and the connection reliability was improved. You can see that there is. According to the semiconductor module A of the present invention, a thin film whose process is very complicated and costly is high only by performing a simple and easy process of flattening the surface of the electrode pad in the device mounting area by the pressure flattening means. It has been found that the semiconductor element can be mounted with the same reliability as the semiconductor module C using the mounting substrate on which the electrode pads and the wiring conductors are formed by the process.
【0039】なお、半導体モジュールAにおいては、そ
の半導体素子の突起電極と実装用基板の電極パッドとの
接合強度は、半導体モジュールCと同等の十分な接合強
度であった。In the semiconductor module A, the bonding strength between the protruding electrode of the semiconductor element and the electrode pad of the mounting substrate was a sufficient bonding strength equivalent to that of the semiconductor module C.
【0040】これにより、本発明の実装用基板によれ
ば、高い良品率で、かつ高い接続信頼性を有する半導体
モジュールを作製できることが確認できた。Thus, it was confirmed that according to the mounting substrate of the present invention, a semiconductor module having a high yield rate and a high connection reliability can be manufactured.
【0041】なお、以上はあくまで本発明の実施の形態
の例示であって、本発明はこれらに限定されるものでは
なく、本発明の要旨を逸脱しない範囲で種々の変更や改
良を加えることは何ら差し支えない。例えば、実施例で
は加圧平坦化手段にはセラミックツールを用いたが、金
属製のツールを用いてもよいことは言うまでもない。It should be noted that the above is only an example of the embodiment of the present invention, and the present invention is not limited to the embodiment. Various changes and improvements may be made without departing from the gist of the present invention. No problem. For example, in the embodiment, a ceramic tool is used for the pressure flattening means, but it goes without saying that a metal tool may be used.
【0042】[0042]
【発明の効果】以上のように、本発明の実装用基板によ
れば、装置実装領域に形成された、半導体装置の突起電
極と対向する電極パッドの表面が、加圧平坦化手段の平
坦面で加圧して平坦にされていることから、平坦面が必
要な装置実装領域の電極パッドの表面だけについて厚膜
印刷法等で形成された電極パッドに対しても装置実装領
域の全体にわたって簡単かつ容易に所望の平坦な実装面
を形成することができるので、半導体装置の突起電極を
安定して確実に接合させることができ、半導体装置を信
頼性良くまた高い良品率で実装することができる。As described above, according to the mounting board of the present invention, the surface of the electrode pad formed in the device mounting area, which faces the bump electrode of the semiconductor device, is formed by the flat surface of the pressure flattening means. Because it is flattened by pressurizing, the surface of the electrode pad in the device mounting area that requires a flat surface can be easily and easily applied to the electrode pad formed by thick film printing etc. over the entire device mounting area. Since a desired flat mounting surface can be easily formed, the bump electrodes of the semiconductor device can be stably and surely joined, and the semiconductor device can be mounted with high reliability and a high yield rate.
【0043】また、装置実装領域に電極パッドと電気的
に接続された配線導体が形成されている場合にその配線
導体の表面も加圧平坦化手段の平坦面で加圧して平坦に
したことにより、平坦面が必要な装置実装領域の電極パ
ッドおよび配線導体の表面だけについて厚膜印刷法等で
形成された配線導体に対しても電極パッドとともに装置
実装領域の全体にわたって簡単かつ容易に所望の平坦な
実装面を形成することができるので、装置実装領域の配
線導体の表面の高さばらつきや平坦度ばらつきが原因で
発生する配線導体と半導体装置との接触や短絡等の不具
合が発生することがなく、半導体装置の突起電極を安定
して確実に接合させることができ、半導体装置を信頼性
良くまた高い良品率で実装することができる。Also, when a wiring conductor electrically connected to the electrode pad is formed in the device mounting area, the surface of the wiring conductor is also flattened by pressing the flat surface of the pressing flattening means. Only the surface of the electrode pad and the wiring conductor in the device mounting area where a flat surface is required, and the wiring flat formed by the thick film printing method can be easily and easily provided with the electrode pad together with the electrode pad over the entire device mounting area. Since a stable mounting surface can be formed, problems such as contact or short-circuit between the wiring conductor and the semiconductor device caused by variations in the height and flatness of the surface of the wiring conductor in the device mounting area may occur. In addition, the bumps of the semiconductor device can be stably and reliably joined, and the semiconductor device can be mounted with high reliability and a high yield rate.
【0044】また、本発明の半導体モジュールによれ
ば、このような本発明の実装用基板に半導体装置を実装
していることから、半導体装置の突起電極と実装用基板
の電極パッドとを安定かつ確実に接合して良好な接続状
態で半導体装置を実装することができ、信頼性が高い半
導体モジュールとなり、また高い良品率で作製すること
ができる。Further, according to the semiconductor module of the present invention, since the semiconductor device is mounted on the mounting substrate of the present invention, the projecting electrodes of the semiconductor device and the electrode pads of the mounting substrate can be stably and reliably mounted. The semiconductor device can be mounted in a good connection state by reliable bonding, a highly reliable semiconductor module can be manufactured, and a high yield rate can be achieved.
【0045】以上により、本発明によれば、半導体装置
を実装用基板にフリップチップ実装する際に、信頼性良
くかつ高い良品率で半導体装置の突起電極と実装用基板
の電極パッドとを接合でき、しかも短時間かつ低コスト
で作製可能な実装用基板を提供することができた。As described above, according to the present invention, when a semiconductor device is flip-chip mounted on a mounting substrate, the projection electrodes of the semiconductor device and the electrode pads of the mounting substrate can be bonded with high reliability and a high yield. In addition, a mounting substrate that can be manufactured in a short time and at low cost can be provided.
【0046】また、本発明によれば、信頼性良くかつ高
い良品率で半導体装置の突起電極と実装用基板の電極パ
ッドとを接合してフリップチップ実装することができ、
短時間かつ低コストで作製可能な実装用基板を用いた半
導体モジュールを提供することができた。Further, according to the present invention, the bump electrodes of the semiconductor device and the electrode pads of the mounting substrate can be bonded to each other with high reliability and a high yield rate, thereby enabling flip-chip mounting.
A semiconductor module using a mounting substrate that can be manufactured in a short time and at low cost can be provided.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の実装用基板およびそれを用いた半導体
モジュールの実施の形態の一例を示す側面図である。FIG. 1 is a side view showing an example of an embodiment of a mounting board and a semiconductor module using the same according to the present invention.
【図2】本発明の実装用基板における電極パッドの表面
を平坦にする方法の例を示す側面図である。FIG. 2 is a side view showing an example of a method for flattening the surface of an electrode pad on a mounting substrate according to the present invention.
【図3】本発明の実装用基板における電極パッドの表面
を平坦にする方法の他の例を示す側面図である。FIG. 3 is a side view showing another example of a method for flattening the surface of an electrode pad in a mounting substrate of the present invention.
【図4】(a)および(b)は、それぞれ半導体素子の
フリップチップ実装の工程を説明するための側面図であ
る。FIGS. 4A and 4B are side views for explaining a step of flip-chip mounting a semiconductor element.
1・・・・・半導体装置 2・・・・・突起電極 3・・・・・実装用基板 4・・・・・電極パッド 7、8・・・加圧平坦化手段 1 semiconductor device 2 projecting electrode 3 mounting substrate 4 electrode pad 7 8 pressure flattening means
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成12年6月29日(2000.6.2
9)[Submission date] June 29, 2000 (2006.2.
9)
【手続補正1】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0033[Correction target item name] 0033
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【0033】そして、この実装用基板をフリップチップ
実装機のステージに載せ、このセラミックツールを実装
機のチップ実装用ヘッドに搭載して、約200Nの加圧力
で装置実装領域の電極パッドおよび配線導体の表面を加
圧して平坦にし、それらの平坦度および高さばらつきを
向上させた。Then, the mounting substrate is mounted on a stage of a flip chip mounting machine, and the ceramic tool is mounted on a chip mounting head of the mounting machine. Were flattened by pressing, and their flatness and height variation were improved.
Claims (3)
する半導体装置が実装される装置実装領域を備え、該装
置実装領域に前記突起電極と対応する電極パッドが形成
された実装用基板であって、前記電極パッドの表面が加
圧平坦化手段の平坦面で加圧して平坦にされていること
を特徴とする実装用基板。1. A mounting substrate, comprising: a device mounting region on a top surface of an insulating substrate on which a semiconductor device having a protruding electrode on a lower surface is mounted; and an electrode pad corresponding to the protruding electrode is formed in the device mounting region. A mounting substrate, wherein a surface of the electrode pad is flattened by pressing with a flat surface of a pressing flattening means.
気的に接続された配線導体が形成され、該配線導体の表
面も前記加圧平坦化手段の平坦面で加圧して平坦にされ
ていることを特徴とする請求項1記載の実装用基板。2. A wiring conductor electrically connected to the electrode pad is formed in the device mounting area, and the surface of the wiring conductor is also flattened by pressing the flat surface of the pressing flattening means. The mounting substrate according to claim 1, wherein:
板の前記装置実装領域に、下面に突起電極を有する半導
体装置を、前記突起電極を前記電極パッドに接合させて
実装したことを特徴とする半導体モジュール。3. A semiconductor device having a projecting electrode on a lower surface is mounted on the device mounting region of the mounting substrate according to claim 1 or 2 by bonding the projecting electrode to the electrode pad. Semiconductor module.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000194401A JP2002016168A (en) | 2000-06-28 | 2000-06-28 | Substrate for mounting and semiconductor module using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000194401A JP2002016168A (en) | 2000-06-28 | 2000-06-28 | Substrate for mounting and semiconductor module using the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002016168A true JP2002016168A (en) | 2002-01-18 |
Family
ID=18693239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000194401A Pending JP2002016168A (en) | 2000-06-28 | 2000-06-28 | Substrate for mounting and semiconductor module using the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2002016168A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006135249A (en) * | 2004-11-09 | 2006-05-25 | Fujitsu Ltd | Ultrasonic packaging method and ultrasonic packaging apparatus used for the same |
DE102005020087A1 (en) * | 2005-04-29 | 2006-11-09 | Infineon Technologies Ag | Even surface area producing method for e.g. semiconductor chip, involves evenly pressing surface by action of die or roller on surface of carrier for semiconductor device, and using steel plate as base for carrier |
JP2007251065A (en) * | 2006-03-17 | 2007-09-27 | Mitsubishi Electric Corp | Ceramic wiring board, and its manufacturing method |
JP2014049629A (en) * | 2012-08-31 | 2014-03-17 | National Institute Of Advanced Industrial & Technology | Joint method |
-
2000
- 2000-06-28 JP JP2000194401A patent/JP2002016168A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006135249A (en) * | 2004-11-09 | 2006-05-25 | Fujitsu Ltd | Ultrasonic packaging method and ultrasonic packaging apparatus used for the same |
DE102005020087A1 (en) * | 2005-04-29 | 2006-11-09 | Infineon Technologies Ag | Even surface area producing method for e.g. semiconductor chip, involves evenly pressing surface by action of die or roller on surface of carrier for semiconductor device, and using steel plate as base for carrier |
US8167187B2 (en) | 2005-04-29 | 2012-05-01 | Infineon Technologies Ag | Method and device for producing a bondable area region on a carrier |
JP2007251065A (en) * | 2006-03-17 | 2007-09-27 | Mitsubishi Electric Corp | Ceramic wiring board, and its manufacturing method |
JP2014049629A (en) * | 2012-08-31 | 2014-03-17 | National Institute Of Advanced Industrial & Technology | Joint method |
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