JP2002299549A - Laminated semiconductor device and manufacturing method therefor - Google Patents

Laminated semiconductor device and manufacturing method therefor

Info

Publication number
JP2002299549A
JP2002299549A JP2001095763A JP2001095763A JP2002299549A JP 2002299549 A JP2002299549 A JP 2002299549A JP 2001095763 A JP2001095763 A JP 2001095763A JP 2001095763 A JP2001095763 A JP 2001095763A JP 2002299549 A JP2002299549 A JP 2002299549A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
wiring
metal wire
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001095763A
Other languages
Japanese (ja)
Inventor
Hiroaki Fujimoto
博昭 藤本
Toru Nomura
徹 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001095763A priority Critical patent/JP2002299549A/en
Publication of JP2002299549A publication Critical patent/JP2002299549A/en
Pending legal-status Critical Current

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    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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Abstract

PROBLEM TO BE SOLVED: To provide a laminated semiconductor device and a manufacturing method for preventing disconnection of a metal thin wire by the stress inside the sealing resin constituting a package and improving reliability. SOLUTION: In the laminated semiconductor device mounted with a plurality of semiconductor elements, the metal thin wire 14 connecting a second semiconductor element 15 and the wiring electrode 10b of a wiring board 10 are provided with a curved recessed part 14a on the side of the second semiconductor element 15, disconnection of the metal thin wire 14 itself by thermal expansion stress inside the sealing resin 16 constituting the package is prevented, and the reliability of the laminated semiconductor device is improved. The reliability is extremely high especially at the time of an operation under a heating environment after performing secondary mounting on a mounting board.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は複数の機能の半導体
素子を三次元方向に積層搭載した積層型半導体装置およ
びその製造方法に関するものであり、特にパッケージ内
部のストレス対策を施した信頼性の高い積層型半導体装
置およびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor device in which semiconductor elements having a plurality of functions are stacked in a three-dimensional direction, and a method of manufacturing the same. The present invention relates to a stacked semiconductor device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、回路構成された1つの配線基板
(キャリア基板)上に複数の機能の半導体素子を積層搭
載し、1パッケージを構成する積層型半導体装置が開発
されている。
2. Description of the Related Art In recent years, a stacked semiconductor device has been developed in which semiconductor elements having a plurality of functions are stacked and mounted on one circuit board (carrier board) having a circuit structure to constitute one package.

【0003】以下、開発されている従来の積層型半導体
装置について、その代表構造として2つの半導体素子が
基板上に積層搭載されたタイプの積層型半導体装置につ
いて説明する。
Hereinafter, a conventional stacked semiconductor device which has been developed will be described as a typical structure of a stacked semiconductor device in which two semiconductor elements are stacked and mounted on a substrate.

【0004】図5は従来の積層型半導体装置の構成を示
す断面図である。
FIG. 5 is a sectional view showing the structure of a conventional stacked semiconductor device.

【0005】図5に示すように、従来の積層型半導体装
置は、配線電極1a,1bおよび底面に端子電極2を有
した配線基板3と、配線基板3上に樹脂4を介してその
表面側が配線基板3と対向してフリップチップ接続され
た第1の半導体素子5と、第1の半導体素子5の裏面上
に接着剤6を介してその表面側を上にして搭載された第
2の半導体素子7を有し、第1の半導体素子5はその表
面の電極パッド5aに設けた突起電極5bが配線基板3
の配線電極1aと接続し、第2の半導体素子7はその表
面の電極パッド7aが配線基板3の配線電極1bと金属
細線8で接続され、配線基板3の上面領域が絶縁性の封
止樹脂9で封止された構造である。
As shown in FIG. 5, in a conventional stacked semiconductor device, a wiring board 3 having wiring electrodes 1a and 1b and terminal electrodes 2 on the bottom surface, and a surface side of the wiring board 3 with a resin 4 interposed therebetween. A first semiconductor element 5 flip-chip connected to the wiring substrate 3 and a second semiconductor mounted on the back surface of the first semiconductor element 5 via an adhesive 6 with its front side up; The first semiconductor element 5 has a protruding electrode 5b provided on an electrode pad 5a on the surface thereof.
Of the second semiconductor element 7, the electrode pad 7a on the surface thereof is connected to the wiring electrode 1b of the wiring board 3 by a thin metal wire 8, and the upper surface area of the wiring board 3 is an insulating sealing resin. 9 is a structure sealed.

【0006】また配線基板3上に搭載された半導体素子
は、メモリー素子、ロジック素子なとの複数の種類の半
導体素子であり、1パッケージで多機能素子による高機
能型の半導体装置である。
The semiconductor elements mounted on the wiring board 3 are a plurality of types of semiconductor elements such as a memory element and a logic element, and are high-function type semiconductor devices formed of multifunctional elements in one package.

【0007】次に従来の積層型半導体装置の製造方法に
ついて図面を参照しながら説明する。図6,図7は従来
の積層型半導体装置の製造方法を示す工程ごとの主要な
断面図である。
Next, a conventional method for manufacturing a stacked semiconductor device will be described with reference to the drawings. 6 and 7 are main cross-sectional views for each process showing a conventional method for manufacturing a stacked semiconductor device.

【0008】まず図6(a)に示すように、第1の半導
体素子5の表面の複数の電極パッド5a上に突起電極
(バンプ)5bを各々形成する。この突起電極の形成は
メッキバンプ、ワイヤーボンド法によるスタッドバンプ
などの工法で形成される。
First, as shown in FIG. 6A, projecting electrodes (bumps) 5b are respectively formed on a plurality of electrode pads 5a on the surface of the first semiconductor element 5. The bump electrodes are formed by a plating bump, a stud bump by a wire bonding method, or the like.

【0009】次に図6(b)に示すように、配線基板3
の上面に対してシート状の異方性導電性(ACF)の樹
脂4を供給するとともに、第1の半導体素子5をその突
起電極5bの面を配線基板3の上面に対向させる。ここ
で配線基板への樹脂4の供給は配線基板3の配線電極1
aを覆うように供給するものであり、シート状以外に液
状の樹脂をポッティングにより供給してもよい。
Next, as shown in FIG.
A sheet-like anisotropic conductive (ACF) resin 4 is supplied to the upper surface of the wiring substrate 3, and the surface of the projection electrode 5 b of the first semiconductor element 5 is opposed to the upper surface of the wiring substrate 3. Here, the supply of the resin 4 to the wiring board is performed by the wiring electrode 1 of the wiring board 3.
The liquid resin is supplied so as to cover the sheet a, and a liquid resin other than the sheet shape may be supplied by potting.

【0010】次に図6(c)に示すように、第1の半導
体素子5を配線基板3の上面に加圧して、第1の半導体
素子5の突起電極5bと配線基板3の配線電極1aとを
接続する。
Next, as shown in FIG. 6C, the first semiconductor element 5 is pressed onto the upper surface of the wiring substrate 3 to project the protruding electrode 5b of the first semiconductor element 5 and the wiring electrode 1a of the wiring substrate 3. And connect.

【0011】次に図6(d)に示すように、第2の半導
体素子7を配線基板3に搭載した第1の半導体素子5の
裏面(背面側)に対して接着剤6により、その裏面で接
着固定する。
Next, as shown in FIG. 6D, the back surface (back side) of the first semiconductor element 5 on which the second semiconductor element 7 is mounted on the wiring board 3 is applied by the adhesive 6 to the back surface. Adhesively fix with.

【0012】次に図7(a)に示すように、搭載した第
2の半導体素子7の電極パッド7aと配線基板3の上面
の配線電極1bとを金属細線8により電気的に接続す
る。
Next, as shown in FIG. 7A, the electrode pads 7a of the mounted second semiconductor element 7 and the wiring electrodes 1b on the upper surface of the wiring board 3 are electrically connected by thin metal wires 8.

【0013】そして図7(b)に示すように、配線基板
3の上面領域を絶縁性の封止樹脂9で封止することによ
り積層型半導体装置を形成するものである。
Then, as shown in FIG. 7B, the stacked semiconductor device is formed by sealing the upper surface area of the wiring board 3 with an insulating sealing resin 9.

【0014】以上のような各工程により、従来は配線基
板上に2つの半導体素子を搭載した1パッケージタイプ
の積層型半導体装置を実現していた。
Through the above steps, a one-package type stacked semiconductor device in which two semiconductor elements are mounted on a wiring board has been conventionally realized.

【0015】[0015]

【発明が解決しようとする課題】しかしながら前記従来
の積層型半導体装置では、2つの半導体素子を1枚の配
線基板上に搭載する構造であるため、配線基板の上面領
域へ付加される構成部材が多く、熱膨張によって配線基
板の反り、または熱膨張によるストレスで半導体素子と
配線基板とを電気的に接続している金属細線の断線が懸
念されていた。
However, the conventional stacked semiconductor device has a structure in which two semiconductor elements are mounted on a single wiring board, so that the components added to the upper surface area of the wiring board are not provided. In many cases, there is a concern that the wiring board may be warped due to thermal expansion or a thin metal wire electrically connecting the semiconductor element and the wiring board may be broken due to stress due to thermal expansion.

【0016】すなわち熱膨張によって、積層型半導体装
置を構成する配線基板、半導体素子などの各構成部材の
熱膨張係数の差から、半導体素子が膨張した場合、パッ
ケージを構成する封止樹脂内部で半導体素子が微動し、
半導体素子と配線基板とを接続している金属細線がスト
レスを受けて断線する恐れがあった。従来は積層型半導
体装置を構成する配線基板、半導体素子、突起電極など
の各構成部材の熱膨張係数を近似するようにしたり、ま
たは熱膨張や、それによる積層型半導体装置自体の反り
に対抗できる構造にするなどして対策していたが、今後
は2つの半導体素子の搭載にとどまらす、3つ以上の半
導体素子を1つの配線基板上に搭載して1パッケージを
構成する傾向にあるため、根本的な積層型半導体装置の
構造の開発が必要とされていた。
That is, when the semiconductor element expands due to the difference in thermal expansion coefficient between the constituent members such as the wiring board and the semiconductor element constituting the stacked semiconductor device due to the thermal expansion, the semiconductor inside the sealing resin constituting the package is formed. The element moves slightly,
There is a risk that the thin metal wire connecting the semiconductor element and the wiring board may be broken due to stress. Conventionally, it is possible to approximate the thermal expansion coefficient of each component such as a wiring board, a semiconductor element, and a protruding electrode constituting a stacked semiconductor device, or to counteract thermal expansion and warpage of the stacked semiconductor device itself due to the thermal expansion coefficient. Although there was a countermeasure such as a structure, in the future it will be limited to mounting two semiconductor elements, and since there is a tendency to mount three or more semiconductor elements on one wiring board to constitute one package, There was a need to develop a fundamental stacked semiconductor device structure.

【0017】本発明は前記した従来の課題を解決するも
のであり、2つの以上の半導体素子を配線基板上に3次
元で搭載して1パッケージを構成した積層型半導体装置
において、パッケージを構成する封止樹脂内部でのスト
レスによる金属細線の断線を防止し、信頼性を高めた積
層型半導体装置およびその製造方法を提供することを目
的とする。
The present invention solves the above-mentioned conventional problems, and forms a package in a stacked semiconductor device in which two or more semiconductor elements are mounted three-dimensionally on a wiring board to form one package. It is an object of the present invention to provide a stacked semiconductor device having improved reliability by preventing disconnection of a thin metal wire due to stress inside a sealing resin, and a method of manufacturing the same.

【0018】[0018]

【課題を解決するための手段】前記従来の課題を解決す
るために本発明の積層型半導体装置は、配線電極を有し
た配線基板と、前記配線基板上に第1の半導体素子と第
2の半導体素子との2つ以上の半導体素子が積層搭載さ
れ、少なくとも前記第1の半導体素子と前記第2の半導
体素子のうちの1つの半導体素子と前記配線基板の配線
電極とを電気的に接続した金属細線と、前記配線基板の
前記積層された2つ以上の半導体素子の外囲を含む上面
領域を封止した封止樹脂とよりなる積層型半導体装置で
あって、前記金属細線は半導体素子側に湾曲した凹部を
有している積層型半導体装置である。
In order to solve the above-mentioned conventional problems, a stacked semiconductor device according to the present invention comprises a wiring board having wiring electrodes, a first semiconductor element and a second semiconductor element on the wiring board. Two or more semiconductor elements including a semiconductor element are stacked and mounted, and at least one of the first semiconductor element and the second semiconductor element is electrically connected to a wiring electrode of the wiring board. A laminated semiconductor device comprising: a metal thin wire; and a sealing resin sealing an upper surface region including an outer periphery of the stacked two or more semiconductor elements of the wiring substrate, wherein the metal thin wire is provided on a semiconductor element side. This is a stacked semiconductor device having a concavely curved concave portion.

【0019】また本発明の積層型半導体装置は、配線電
極を有した配線基板と、前記配線基板上に樹脂を介して
その表面側が前記配線基板と対向してフリップチップ接
続された第1の半導体素子と、前記第1の半導体素子の
裏面上に接着剤を介してその裏面側で搭載され、前記配
線基板の配線電極と金属細線で電気的に接続された第2
の半導体素子との少なくとも2つの半導体素子を有し、
前記配線基板上の前記第1の半導体素子、前記第2の半
導体素子および前記金属細線の外囲を含む配線基板上面
が封止樹脂で封止された積層型半導体装置であって、前
記第2の半導体素子と前記配線基板の配線電極とを接続
した金属細線は、前記第2の半導体素子側に湾曲した凹
部を有している積層型半導体装置である。
The stacked semiconductor device according to the present invention also includes a wiring substrate having wiring electrodes, and a first semiconductor flip-chip connected on the wiring substrate with a front surface facing the wiring substrate via a resin via a resin. A second element mounted on the back surface of the first semiconductor element via an adhesive on the back surface of the first semiconductor element, and electrically connected to the wiring electrode of the wiring board by a thin metal wire;
Having at least two semiconductor elements with a semiconductor element of
A stacked semiconductor device in which an upper surface of the wiring board including an outer periphery of the first semiconductor element, the second semiconductor element, and the fine metal wire on the wiring board is sealed with a sealing resin; The thin metal wire connecting the semiconductor element and the wiring electrode of the wiring board is a stacked semiconductor device having a curved concave portion on the second semiconductor element side.

【0020】また本発明の積層型半導体装置は、配線電
極を有した配線基板と、前記配線基板上に接着剤を介し
てその裏面側が前記配線基板上に搭載され、前記配線基
板の配線電極と第1の金属細線で電気的に接続された第
1の半導体素子と、前記第1の半導体素子の表面上に接
着剤を介してその裏面側で搭載され、前記配線基板の配
線電極と第2の金属細線で電気的に接続された第2の半
導体素子との少なくとも2つの半導体素子を有し、前記
配線基板上の前記第1の半導体素子、前記第2の半導体
素子および前記第1の金属細線,第2の金属細線の外囲
を含む配線基板上面が封止樹脂で封止された積層型半導
体装置であって、前記第1の金属細線は前記第1の半導
体素子側に湾曲した凹部を有している積層型半導体装置
である。
Further, the stacked semiconductor device of the present invention has a wiring board having a wiring electrode, and a back side mounted on the wiring board via an adhesive on the wiring board, the wiring board being provided with a wiring electrode. A first semiconductor element electrically connected by a first thin metal wire, mounted on a back surface of the first semiconductor element via an adhesive on a front surface of the first semiconductor element, and connected to a wiring electrode of the wiring board with a second electrode; The first semiconductor element, the second semiconductor element, and the first metal element on the wiring board, the semiconductor element including at least two semiconductor elements electrically connected to each other by a thin metal wire. A stacked semiconductor device in which an upper surface of a wiring substrate including a thin wire and a second metal thin wire is sealed with a sealing resin, wherein the first thin metal wire is a concave portion curved toward the first semiconductor element. Is a stacked semiconductor device having:

【0021】そして具体的には、第2の金属細線は第2
の半導体素子側に湾曲した凹部を有している積層型半導
体装置である。
More specifically, the second fine metal wire is the second metal wire.
Is a stacked semiconductor device having a curved concave portion on the semiconductor element side.

【0022】また、凹部は金属細線の中間部分に位置し
ている積層型半導体装置である。
The recess is a stacked type semiconductor device located at an intermediate portion of the thin metal wire.

【0023】また、配線基板は、上面に配線電極と、下
面に前記上面の配線電極と接続した端子電極とを有した
配線基板である積層型半導体装置である。
The wiring substrate is a laminated semiconductor device which is a wiring substrate having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface.

【0024】また、第1の半導体素子または第2の半導
体素子の面積と配線基板の面積とは、前記配線基板の面
積が大きい条件で略同等の大きさで構成されてチップサ
イズパッケージを構成している積層型半導体装置であ
る。
Further, the area of the first semiconductor element or the second semiconductor element and the area of the wiring board are substantially the same under the condition that the area of the wiring board is large, so that a chip size package is formed. Is a stacked semiconductor device.

【0025】前記構成の通り、半導体素子と配線基板と
を電気的かつ物理的に接続している金属細線は内側、す
なわちそれが接続されている半導体素子側に湾曲した凹
部を有しているため、封止樹脂内部でのストレスによる
金属細線の断線を防止できるものである。
As described above, the thin metal wire that electrically and physically connects the semiconductor element and the wiring board has a curved concave portion inside, that is, the semiconductor element side to which it is connected. In addition, the thin metal wire can be prevented from being broken due to stress inside the sealing resin.

【0026】本発明の積層型半導体装置の製造方法は、
上面に配線電極と、下面に前記上面の配線電極と接続し
た端子電極とを有した配線基板に対して、樹脂を介して
その表面の電極パッドに突起電極が形成された第1の半
導体素子をフリップチップ接続し、前記突起電極と前記
配線基板の配線電極とを接続する第1の工程と、前記第
1の半導体素子の裏面に対して、接着剤を介して第2の
半導体素子をその裏面側で接着搭載する第2の工程と、
前記配線基板の配線電極と前記第2の半導体素子とを金
属細線で電気的に接続するともに、前記金属細線に前記
第2の半導体素子側に湾曲した凹部を形成する第3の工
程と、前記配線基板の上面領域を封止樹脂で封止する第
4の工程とよりなる積層型半導体装置の製造方法であ
る。
The method for manufacturing a stacked semiconductor device according to the present invention comprises:
For a wiring substrate having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface, a first semiconductor element having a protruding electrode formed on an electrode pad on the surface via a resin is provided. A first step of performing flip-chip connection and connecting the protruding electrode and the wiring electrode of the wiring substrate, and bonding the second semiconductor element to the back surface of the first semiconductor element via an adhesive with respect to the back surface of the first semiconductor element A second step of bonding and mounting on the side;
A third step of electrically connecting a wiring electrode of the wiring substrate and the second semiconductor element with a thin metal wire, and forming a curved concave portion on the side of the second semiconductor element in the thin metal wire; A fourth step of sealing the upper surface region of the wiring board with a sealing resin is a method for manufacturing a stacked semiconductor device.

【0027】そして具体的には、第1の工程、第2の工
程、第3の工程、第4の工程は、その上面に複数の半導
体素子が個々に搭載されるもので、また上面に個々の半
導体素子に対応した配線電極が設けられ、下面には上面
の配線電極と基板内部で接続した端子電極が設けられ、
個々の半導体素子単位ごとに分割され得る構造の1枚の
大型の配線基板に対して各々行い、最終工程として、個
々の積層型半導体装置に切断分離する工程を有する積層
型半導体装置の製造方法である。
More specifically, the first step, the second step, the third step, and the fourth step involve individually mounting a plurality of semiconductor elements on the upper surface, A wiring electrode corresponding to the semiconductor element is provided, and a lower surface is provided with a terminal electrode connected to the upper surface wiring electrode inside the substrate,
A method for manufacturing a stacked semiconductor device, which includes a step of performing each of one large wiring substrate having a structure that can be divided into individual semiconductor element units and cutting and separating the stacked semiconductor devices into individual stacked semiconductor devices as a final step. is there.

【0028】また、配線基板の配線電極と第2の半導体
素子とを金属細線で電気的に接続するともに、前記金属
細線に前記第2の半導体素子側に湾曲した凹部を形成す
る第3の工程では、前記金属細線の中間部分に凹部を形
成する積層型半導体装置の製造方法である。
A third step of electrically connecting the wiring electrode of the wiring board to the second semiconductor element with a thin metal wire and forming a curved concave portion on the side of the second semiconductor element in the thin metal wire; Then, a method of manufacturing a stacked semiconductor device in which a concave portion is formed in an intermediate portion of the thin metal wire.

【0029】前記構成の通り、配線基板の配線電極と第
2の半導体素子とを金属細線で電気的に接続するととも
に、金属細線の中間部分に第2の半導体素子側に湾曲し
た凹部を形成しているため、封止樹脂で外囲を封止した
後、封止樹脂内部でのストレスによる金属細線の断線を
防止できるものである。
As described above, the wiring electrode of the wiring board and the second semiconductor element are electrically connected to each other by a thin metal wire, and a concave portion curved toward the second semiconductor element is formed in an intermediate portion of the thin metal wire. Therefore, after the outer periphery is sealed with the sealing resin, breakage of the thin metal wire due to stress inside the sealing resin can be prevented.

【0030】さらに金属細線の中間部分に第2の半導体
素子側に湾曲した凹部を形成しているため、樹脂封止の
際の流動樹脂による圧力に対しても緩衝構造となり、金
属細線の断線を防止して封止できるものである。特に一
括成形時の大量の封止樹脂の圧力に対しては絶大な断線
防止の効果を奏することができるものである。
Further, since the concave portion curved toward the second semiconductor element is formed in the middle portion of the thin metal wire, the structure becomes a buffer structure against the pressure caused by the flowing resin at the time of resin sealing, and the break of the thin metal wire is prevented. It can be prevented and sealed. In particular, a great effect of preventing disconnection can be exerted against a large amount of sealing resin pressure at the time of batch molding.

【0031】[0031]

【発明の実施の形態】以下、本発明の積層型半導体装置
およびその製造方法の一実施形態について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a stacked semiconductor device and a method of manufacturing the same according to the present invention will be described below.

【0032】まず本実施形態の積層型半導体装置につい
て図面を参照しながら説明する。図1は本実施形態の積
層型半導体装置を示す主要な断面図である。
First, the stacked semiconductor device of the present embodiment will be described with reference to the drawings. FIG. 1 is a main cross-sectional view showing the stacked semiconductor device of the present embodiment.

【0033】本実施形態の積層型半導体装置は、配線電
極を有した配線基板と、その配線基板上に第1の半導体
素子と第2の半導体素子との2つ以上の半導体素子が積
層搭載され、少なくとも複数の半導体素子のうちの1つ
の半導体素子と配線基板の配線電極とを電気的に接続し
た金属細線と、配線基板上の各半導体素子の外囲を含む
上面領域を封止した封止樹脂とよりなる積層型半導体装
置であって、金属細線は半導体素子側に湾曲した凹部を
有しているものである。そのため、封止樹脂内部でのス
トレスによる金属細線の断線を防止できるものである。
また特に二次実装後の加熱環境下での信頼性を高めた積
層型半導体装置である。
In the stacked semiconductor device of the present embodiment, a wiring board having wiring electrodes, and two or more semiconductor elements of a first semiconductor element and a second semiconductor element are stacked and mounted on the wiring board. A thin metal wire electrically connecting at least one semiconductor element of the plurality of semiconductor elements and a wiring electrode of the wiring substrate, and a sealing in which an upper surface region including an outer periphery of each semiconductor element on the wiring substrate is sealed; A laminated semiconductor device made of resin, wherein the thin metal wire has a curved concave portion on the semiconductor element side. Therefore, disconnection of the thin metal wire due to stress inside the sealing resin can be prevented.
In addition, the present invention is a stacked semiconductor device with improved reliability particularly in a heating environment after secondary mounting.

【0034】具体的には図1に示すように、本実施形態
の積層型半導体装置は、上面(表面)に配線電極10
a,10bを有し、下面(裏面)に各配線電極10a,
10bと基板内部で電気的に接続した端子電極10cを
有した配線基板10と、配線基板10上に異方性導電性
(ACF)の樹脂11を介してその表面側の電極パッド
12a上の突起電極12bが、配線基板10と対向して
フリップチップ接続されたマイコン素子などの第1の半
導体素子12と、第1の半導体素子12の裏面上に接着
剤13を介してその裏面側で第1の半導体素子12の裏
面と接着して積層搭載され、配線基板10の配線電極1
0bと金属細線14でその電極パッド15aが電気的に
接続されたメモリー素子などの第2の半導体素子15と
の少なくとも2つの半導体素子を有し、配線基板10上
の第1の半導体素子12、第2の半導体素子15および
金属細線14の外囲を含む配線基板10の上面領域が封
止樹脂16で封止された積層型半導体装置であって、第
2の半導体素子15と配線基板10の配線電極10bと
を接続した金属細線14は、内側である第2の半導体素
子15側に湾曲した凹部14aを有しているものであ
る。そして凹部14aは、金属細線14が第2の半導体
素子15の電極パッド15aと接続した部分と、配線基
板10の配線電極10bと接続した部分の中間部分に設
けられているものであり、各接続部分(ボンド部)には
直接的に外力が印加されない構造となっている。また金
属細線14の中間部分としては、金属細線14の膨らみ
が大きく、外力が印加されやすい部分であり、本実施形
態では金属細線14の接続された間の中央部分に凹部1
4aを形成している。
Specifically, as shown in FIG. 1, the stacked semiconductor device of this embodiment has a wiring electrode 10
a, 10b, and each wiring electrode 10a,
A wiring board 10 having a terminal electrode 10c electrically connected to the inside of the board 10b, and a projection on an electrode pad 12a on the front side of the wiring board 10 via an anisotropic conductive (ACF) resin 11 on the wiring board 10 An electrode 12b is connected to a first semiconductor element 12, such as a microcomputer element, which is flip-chip connected to the wiring substrate 10 and a first semiconductor element 12 on the back surface of the first semiconductor element 12 with an adhesive 13 therebetween. Is laminated and mounted on the back surface of the semiconductor element 12 of the
0b and a second semiconductor element 15 such as a memory element such as a memory element whose electrode pad 15a is electrically connected by a thin metal wire 14, and the first semiconductor element 12 on the wiring board 10; This is a stacked semiconductor device in which the upper surface area of the wiring substrate 10 including the outer periphery of the second semiconductor element 15 and the fine metal wires 14 is sealed with the sealing resin 16. The thin metal wire 14 connected to the wiring electrode 10b has a concave portion 14a which is curved on the second semiconductor element 15 side which is inside. The concave portion 14a is provided at an intermediate portion between a portion where the thin metal wire 14 is connected to the electrode pad 15a of the second semiconductor element 15 and a portion where the thin metal wire 14 is connected to the wiring electrode 10b of the wiring board 10. The structure is such that no external force is directly applied to the portion (bond portion). The middle portion of the thin metal wire 14 is a portion where the swelling of the thin metal wire 14 is large and an external force is easily applied.
4a.

【0035】さらに本実施形態の積層型半導体装置は、
第1の半導体素子12または第2の半導体素子15の面
積と配線基板10の面積とは、配線基板10の面積が大
きい条件で略同等の大きさで構成されてCSP(チップ
サイズパッケージ)を構成しているものである。
Further, the stacked semiconductor device of the present embodiment
The area of the first semiconductor element 12 or the second semiconductor element 15 and the area of the wiring board 10 are substantially the same size under the condition that the area of the wiring board 10 is large, and constitute a CSP (chip size package). Is what you are doing.

【0036】以上、本実施形態の積層型半導体装置は、
少なくとも2つ以上の半導体素子を配線基板上に搭載し
て1パッケージCSPを構成したものであり、特に配線
基板10と第2の半導体素子15とを電気的に接続した
金属細線14は内側に湾曲した凹部14aを有している
ので、パッケージを構成する封止樹脂16の内部での熱
膨張ストレスによる金属細線自体の断線を防止し、信頼
性を高めた積層型半導体装置である。特に本実施形態の
積層型半導体装置を実装基板へ二次実装した後の加熱環
境下での動作時にその信頼性が極めて高いものである。
As described above, the stacked semiconductor device of this embodiment is
A one-package CSP is formed by mounting at least two or more semiconductor elements on a wiring board. In particular, the thin metal wires 14 electrically connecting the wiring board 10 and the second semiconductor element 15 are curved inward. Since the recessed portion 14a is provided, it is possible to prevent disconnection of the thin metal wire itself due to thermal expansion stress inside the sealing resin 16 constituting the package, thereby providing a stacked semiconductor device with improved reliability. In particular, the reliability is extremely high when the stacked semiconductor device of the present embodiment is operated in a heating environment after being secondarily mounted on a mounting board.

【0037】次に本実施形態の積層型半導体装置の製造
方法について図面を参照しながら説明する。図2,図3
は本実施形態の積層型半導体装置の製造方法を示す工程
ごとの主要な断面図である。
Next, a method of manufacturing the stacked semiconductor device of the present embodiment will be described with reference to the drawings. Figures 2 and 3
FIG. 4 is a main cross-sectional view for each step showing the method for manufacturing the stacked semiconductor device of the embodiment.

【0038】まず図2(a)に示すように、第1の半導
体素子12の表面の複数の電極パッド12a上に突起電
極(バンプ)12bを各々形成する。この突起電極の形
成はメッキバンプ、ワイヤーボンド法によるスタッドバ
ンプなどの工法で形成される。
First, as shown in FIG. 2A, projecting electrodes (bumps) 12b are formed on a plurality of electrode pads 12a on the surface of the first semiconductor element 12, respectively. The bump electrodes are formed by a plating bump, a stud bump by a wire bonding method, or the like.

【0039】次に図2(b)に示すように、配線基板1
0の上面に対してシート状の異方性導電性(ACF)の
樹脂11を供給するとともに、マイコン(ロジック)素
子などの第1の半導体素子12をその突起電極12bの
面を配線基板10の上面に対向させる。ここで配線基板
10への樹脂11の供給は配線基板10の配線電極10
aを覆うように供給するものであり、シート状以外に液
状の樹脂をポッティングにより供給してもよい。またこ
の樹脂11の配線基板10と第1の半導体素子12との
間隙への充填は、前述のようにシート状の樹脂11を予
め配線基板10上に供給する以外、第1の半導体素子1
2と配線基板10の配線電極10aとを接続した後、注
入によって充填形成してもよい。この後注入による充填
では、絶縁性の樹脂でよい。
Next, as shown in FIG.
In addition to supplying a sheet-like anisotropic conductive (ACF) resin 11 to the upper surface of the wiring board 10, the first semiconductor element 12 such as a microcomputer (logic) element is connected to the surface of the projecting electrode 12 b of the wiring board 10. Face the upper surface. Here, the supply of the resin 11 to the wiring board 10 is performed by using the wiring electrodes 10 of the wiring board 10.
The liquid resin is supplied so as to cover the sheet a, and a liquid resin other than the sheet shape may be supplied by potting. The filling of the resin 11 into the gap between the wiring board 10 and the first semiconductor element 12 is performed by first supplying the sheet-shaped resin 11 onto the wiring board 10 as described above.
After connecting the wiring electrode 2 and the wiring electrode 10a of the wiring board 10, the filling may be performed by injection. In the subsequent filling by injection, an insulating resin may be used.

【0040】次に図2(c)に示すように、第1の半導
体素子12を配線基板10の上面に加圧して、第1の半
導体素子12の突起電極12bと配線基板10の配線電
極10aとを接続する。なお、素子接続、固定後におい
て、第1の半導体素子12の厚みを薄厚にするため、グ
ラインダーによる研削、さらにポリッシングを行い、素
子厚を薄くする工程を付加してもよい。
Next, as shown in FIG. 2C, the first semiconductor element 12 is pressed onto the upper surface of the wiring board 10 to project the protruding electrode 12b of the first semiconductor element 12 and the wiring electrode 10a of the wiring board 10. And connect. After connecting and fixing the elements, a step of reducing the element thickness by performing grinding with a grinder and further polishing to reduce the thickness of the first semiconductor element 12 may be added.

【0041】次に図2(d)に示すように、第1の半導
体素子12の裏面に対して、接着剤13を介して、その
表面に電極パッド15aを有した第2の半導体素子15
を裏面側で搭載する。
Next, as shown in FIG. 2D, the second semiconductor element 15 having an electrode pad 15a on the surface thereof is applied to the back surface of the first semiconductor element 12 with an adhesive 13 therebetween.
Is mounted on the back side.

【0042】次に図3(a)に示すように、搭載した第
2の半導体素子15の電極パッド15aと配線基板10
の配線電極10bとを金属細線14で電気的に接続す
る。金属細線としては、金線、アルミニウム線、銅線を
用いてワイヤーボンドする。この工程では、金属細線1
4の接続時に、第2の半導体素子15の電極パッド15
aと接続した部分と、配線基板10の配線電極10bと
接続した部分の中間部分に対して、第2の半導体素子1
5側に湾曲するように凹部14aを形成する。そして凹
部14aの形成としては、ワイヤーボンダーのボンディ
ングツールを第2の半導体素子15にボンディングし、
1stボンド(素子側)から2ndボンド(基板側)へ
移動させる際、第2の半導体素子15側に一旦移動させ
た後、配線基板10の配線電極10bにボンディングす
ることにより形成できる。凹部14aのくぼみ量として
は、半導体素子に接触しない程度の量であって、また金
属細線14自体がダレることのない程度に抑える。
Next, as shown in FIG. 3A, the electrode pad 15a of the mounted second semiconductor element 15 is
Is electrically connected to the wiring electrode 10b by a thin metal wire 14. Wire bonding is performed using a gold wire, an aluminum wire, or a copper wire as the thin metal wire. In this step, the fine metal wire 1
4 is connected to the electrode pad 15 of the second semiconductor element 15.
a of the second semiconductor element 1 with respect to a portion connected to the wiring electrode 10b of the wiring board 10 and a portion connected to the wiring electrode 10b.
The concave portion 14a is formed so as to be curved to the fifth side. Then, as the formation of the concave portion 14a, a bonding tool of a wire bonder is bonded to the second semiconductor element 15,
When moving from the 1st bond (element side) to the 2nd bond (substrate side), it can be formed by first moving to the second semiconductor element 15 side and then bonding to the wiring electrode 10b of the wiring substrate 10. The amount of depression of the concave portion 14a is an amount that does not make contact with the semiconductor element, and is suppressed to such a degree that the thin metal wire 14 itself does not sag.

【0043】そして図3(b)に示すように、配線基板
10の上面領域の第1の半導体素子12、第2の半導体
素子15、金属細線14の外囲を含む領域を絶縁性のエ
ポキシ樹脂などの封止樹脂16で封止する。この樹脂封
止においては、金型を用いたトランスファーモールド法
やポッティング工法により封止できるものである。
As shown in FIG. 3B, the region including the outer periphery of the first semiconductor element 12, the second semiconductor element 15, and the thin metal wire 14 in the upper surface area of the wiring board 10 is made of an insulating epoxy resin. Sealing with a sealing resin 16. In this resin sealing, sealing can be performed by a transfer molding method using a mold or a potting method.

【0044】そして金属細線14には凹部14aを形成
しているので、封止樹脂16の封止圧が金属細線14に
印加されても断線なく封止できるものである。
Since the concave portion 14a is formed in the fine metal wire 14, even if the sealing pressure of the sealing resin 16 is applied to the fine metal wire 14, the sealing can be performed without disconnection.

【0045】以上、本実施形態の積層型半導体装置の製
造方法では、金属細線の中間部分に第2の半導体素子側
に湾曲した凹部を形成しているため、封止樹脂内部での
ストレスによる金属細線の断線を防止できるほか、金属
細線の中間部分に第2の半導体素子側に湾曲した凹部を
形成しているため、樹脂封止の際の流動樹脂による圧力
に対しても緩衝構造となり、金属細線の断線を防止して
封止できるものである。
As described above, in the manufacturing method of the stacked semiconductor device according to the present embodiment, since the concave portion curved toward the second semiconductor element is formed in the middle portion of the thin metal wire, the metal due to the stress inside the sealing resin is formed. In addition to being able to prevent the thin wire from being broken, a concave portion that is curved toward the second semiconductor element is formed in the middle portion of the thin metal wire. The wire can be sealed by preventing the thin wire from being broken.

【0046】なお、本実施形態の積層型半導体装置の製
造方法では、基板上への各半導体素子の搭載、金属細線
接続、封止の各工程は、その上面に複数の半導体素子が
個々に搭載されるもので、また上面に個々の半導体素子
に対応した配線電極が設けられ、下面には上面の配線電
極と基板内部で接続した端子電極が設けられ、個々の半
導体素子単位ごとに分割され得る構造の1枚の大型の配
線基板に対して各々行なうものである(一括成形工
法)。そして配線基板の上面に対して封止樹脂で封止し
た後、最終工程として、ダイシングブレードにより個々
の積層型半導体装置に切断分離する工程を有するもので
ある。したがって、図1に示したような実施形態の積層
型半導体装置の外形形状として、封止樹脂15の側面が
配線基板10の側面と同一面に位置しているものであ
り、これは一括切断によって分割された形状である。
In the method of manufacturing a stacked semiconductor device according to the present embodiment, the steps of mounting each semiconductor element on a substrate, connecting a thin metal wire, and sealing are performed by individually mounting a plurality of semiconductor elements on the upper surface. In addition, wiring electrodes corresponding to individual semiconductor elements are provided on the upper surface, and terminal electrodes connected to the wiring electrodes on the upper surface inside the substrate are provided on the lower surface, and can be divided into individual semiconductor element units. This is performed for one large-sized wiring substrate having a structure (batch molding method). Then, after sealing the upper surface of the wiring substrate with the sealing resin, a final step is a step of cutting and separating into individual stacked semiconductor devices using a dicing blade. Accordingly, the outer shape of the stacked semiconductor device of the embodiment as shown in FIG. 1 is such that the side surface of the sealing resin 15 is located on the same plane as the side surface of the wiring substrate 10, and this is achieved by batch cutting. It is a divided shape.

【0047】また一括成形において、各半導体素子を接
続する金属細線に凹部を形成しているので、一括成形時
の大量の封止樹脂の圧力に対しては絶大な断線防止の効
果を奏することができるものである。
Further, in the collective molding, since the concave portion is formed in the thin metal wire connecting each semiconductor element, it is possible to exert a great effect of preventing disconnection against a large amount of sealing resin pressure during the collective molding. You can do it.

【0048】次に別の実施形態の積層型半導体装置につ
いて説明する。
Next, a stacked semiconductor device of another embodiment will be described.

【0049】図4は別の実施形態の積層型半導体装置を
示す主要な断面図である。
FIG. 4 is a main sectional view showing a stacked semiconductor device according to another embodiment.

【0050】図4に示すように、本実施形態の積層型半
導体装置は、図1に示した形態と異なり、第1の半導体
素子12の配線基板10との電気的な接続を金属細線1
7で行っているものである。そして金属細線17には金
属細線14に配した凹部14aと同様に、その中間部分
に凹部17aを配したものである。
As shown in FIG. 4, the stacked semiconductor device of this embodiment differs from the embodiment shown in FIG. 1 in that the electrical connection between the first semiconductor element 12 and the wiring board 10 is made by the thin metal wire 1.
7 is what is going on. The concave portion 17a is provided in the middle of the fine metal wire 17 in the same manner as the concave portion 14a provided in the fine metal wire 14.

【0051】この構造により、第1の半導体素子12,
第2の半導体素子15と配線基板10とを電気的かつ物
理的に接続している金属細線14,17は内側、すなわ
ちそれらが接続されている各半導体素子側に湾曲した凹
部14a,17aを有しているため、封止樹脂16内部
でのストレスによる金属細線の断線を防止できるもので
ある。特に図4に示したような形態では、金属細線の数
が多数になるため、ストレスによる影響を受けやすい
が、金属細線が凹部を有しているので、効果的に断線を
防止できるものである。
With this structure, the first semiconductor element 12,
The thin metal wires 14 and 17 that electrically and physically connect the second semiconductor element 15 and the wiring board 10 have curved concave portions 14a and 17a on the inside, that is, on the side of each semiconductor element to which they are connected. Accordingly, breakage of the thin metal wire due to stress inside the sealing resin 16 can be prevented. In particular, in the embodiment as shown in FIG. 4, the number of fine metal wires is large, and thus the metal wires are easily affected by stress. However, since the fine metal wires have concave portions, disconnection can be effectively prevented. .

【0052】以上、本実施形態では、配線基板上に第1
の半導体素子と第2の半導体素子との2つ以上の半導体
素子が積層搭載され、配線基板上に積層された2つ以上
の半導体素子の外囲を含む上面領域を封止した封止樹脂
とよりなる積層型半導体装置であって、少なくとも1つ
の半導体素子が金属細線で配線基板と接続され、その金
属細線の中間部分に凹部を設けているので、封止樹脂内
部でのストレスによる金属細線の断線を防止できるもの
である。特に二次実装後の加熱環境下での信頼性を高め
た積層型半導体装置である。
As described above, in the present embodiment, the first
A sealing resin in which two or more semiconductor elements of the semiconductor element and the second semiconductor element are stacked and mounted, and an upper surface region including an outer periphery of the two or more semiconductor elements stacked on the wiring board is sealed; The semiconductor device according to claim 1, wherein at least one semiconductor element is connected to the wiring board with a thin metal wire, and a concave portion is provided in an intermediate portion of the thin metal wire. Disconnection can be prevented. In particular, the stacked semiconductor device has improved reliability in a heating environment after secondary mounting.

【0053】[0053]

【発明の効果】本発明の積層型半導体装置は、配線基板
上に第1の半導体素子と第2の半導体素子との2つ以上
の半導体素子が積層搭載され、配線基板上に積層された
2つ以上の半導体素子の外囲を含む上面領域を封止した
封止樹脂とよりなる積層型半導体装置において、電気的
に接続した金属細線が凹部を有しているので、封止樹脂
内部でのストレスによる金属細線の断線を防止し、信頼
性を高めた積層型半導体装置を実現できるものである。
According to the stacked semiconductor device of the present invention, two or more semiconductor elements of a first semiconductor element and a second semiconductor element are stacked and mounted on a wiring board and stacked on the wiring board. In a stacked semiconductor device including a sealing resin that seals an upper surface region including an outer periphery of one or more semiconductor elements, a thin metal wire electrically connected has a concave portion, so that the inside of the sealing resin has This prevents a thin metal wire from being broken due to stress, thereby realizing a stacked semiconductor device with improved reliability.

【0054】また本発明の積層型半導体装置の製造方法
は、半導体素子と配線基板とを電気的に接続する際、金
属細線の中間部分に半導体素子側に湾曲した凹部を形成
しているため、樹脂封止の際の流動樹脂による圧力に対
しても緩衝構造となり、金属細線の断線を防止して封止
できるものである。特に一括成形時の大量の封止樹脂の
圧力に対しては絶大な断線防止の効果を奏することがで
きるものである。
In the method of manufacturing a stacked semiconductor device according to the present invention, when the semiconductor element is electrically connected to the wiring board, a concave portion curved toward the semiconductor element is formed in an intermediate portion of the thin metal wire. The structure has a buffer structure against the pressure caused by the flowing resin at the time of resin sealing, and can be sealed while preventing the thin metal wires from being broken. In particular, a great effect of preventing disconnection can be exerted against a large amount of sealing resin pressure at the time of batch molding.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の積層型半導体装置を示す
断面図
FIG. 1 is a sectional view showing a stacked semiconductor device according to an embodiment of the present invention;

【図2】本発明の一実施形態の積層型半導体装置の製造
方法を示す断面図
FIG. 2 is a cross-sectional view illustrating a method of manufacturing a stacked semiconductor device according to one embodiment of the present invention.

【図3】本発明の一実施形態の積層型半導体装置の製造
方法を示す断面図
FIG. 3 is a sectional view showing the method of manufacturing the stacked semiconductor device according to one embodiment of the present invention;

【図4】本発明の他の一実施形態の積層型半導体装置を
示す断面図
FIG. 4 is a sectional view showing a stacked semiconductor device according to another embodiment of the present invention;

【図5】従来の積層型半導体装置を示す断面図FIG. 5 is a cross-sectional view showing a conventional stacked semiconductor device.

【図6】従来の積層型半導体装置の製造方法を示す断面
FIG. 6 is a sectional view showing a conventional method of manufacturing a stacked semiconductor device.

【図7】従来の積層型半導体装置の製造方法を示す断面
FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional stacked semiconductor device.

【符号の説明】[Explanation of symbols]

1a,1b 配線電極 2 端子電極 3 配線基板 4 樹脂 5 第1の半導体素子 5a 電極パッド 5b 突起電極 6 接着剤 7 第2の半導体素子 7a 電極パッド 8 金属細線 9 封止樹脂 10 配線基板 10a,10b 配線電極 11 樹脂 12 第1の半導体素子 12a 電極パッド 12b 突起電極 13 接着剤 14 金属細線 14a 凹部 15 第2の半導体素子 15a 電極パッド 16 封止樹脂 17 金属細線 17a 凹部 1a, 1b Wiring electrode 2 Terminal electrode 3 Wiring board 4 Resin 5 First semiconductor element 5a Electrode pad 5b Protruding electrode 6 Adhesive 7 Second semiconductor element 7a Electrode pad 8 Fine metal wire 9 Sealing resin 10 Wiring board 10a, 10b Wiring electrode 11 Resin 12 First semiconductor element 12a Electrode pad 12b Protruding electrode 13 Adhesive 14 Thin metal wire 14a Depression 15 Second semiconductor element 15a Electrode pad 16 Sealing resin 17 Thin metal wire 17a Depression

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F044 AA02 CC05 FF08 JJ03  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F044 AA02 CC05 FF08 JJ03

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 配線電極を有した配線基板と、 前記配線基板上に第1の半導体素子と第2の半導体素子
との2つ以上の半導体素子が積層搭載され、 少なくとも前記第1の半導体素子と前記第2の半導体素
子のうちの1つの半導体素子と前記配線基板の配線電極
とを電気的に接続した金属細線と、 前記配線基板の前記積層された2つ以上の半導体素子の
外囲を含む上面領域を封止した封止樹脂とよりなる積層
型半導体装置であって、 前記金属細線は半導体素子側に湾曲した凹部を有してい
ることを特徴とする積層型半導体装置。
1. A wiring board having a wiring electrode, and two or more semiconductor elements of a first semiconductor element and a second semiconductor element are stacked and mounted on the wiring board, and at least the first semiconductor element And a thin metal wire electrically connecting one semiconductor element of the second semiconductor element and a wiring electrode of the wiring board; and an outer periphery of the two or more stacked semiconductor elements of the wiring board. A stacked semiconductor device comprising a sealing resin sealing an upper surface region, wherein the thin metal wire has a curved concave portion on a semiconductor element side.
【請求項2】 配線電極を有した配線基板と、 前記配線基板上に樹脂を介してその表面側が前記配線基
板と対向してフリップチップ接続された第1の半導体素
子と、 前記第1の半導体素子の裏面上に接着剤を介してその裏
面側で搭載され、前記配線基板の配線電極と金属細線で
電気的に接続された第2の半導体素子との少なくとも2
つの半導体素子を有し、 前記配線基板上の前記第1の半導体素子、前記第2の半
導体素子および前記金属細線の外囲を含む配線基板上面
が封止樹脂で封止された積層型半導体装置であって、 前記第2の半導体素子と前記配線基板の配線電極とを接
続した金属細線は、前記第2の半導体素子側に湾曲した
凹部を有していることを特徴とする積層型半導体装置。
2. A wiring board having wiring electrodes, a first semiconductor element flip-chip connected on the wiring board with a front surface facing the wiring board via a resin, and the first semiconductor. At least two of a second semiconductor element mounted on the back side of the element via an adhesive and on the back side thereof and electrically connected to the wiring electrode of the wiring board by a thin metal wire
A stacked semiconductor device having two semiconductor elements, and the upper surface of the wiring substrate including the first semiconductor element, the second semiconductor element, and the outer periphery of the fine metal wire on the wiring substrate is sealed with a sealing resin. Wherein the thin metal wire connecting the second semiconductor element and the wiring electrode of the wiring substrate has a curved concave portion on the side of the second semiconductor element. .
【請求項3】 配線電極を有した配線基板と、 前記配線基板上に接着剤を介してその裏面側が前記配線
基板上に搭載され、前記配線基板の配線電極と第1の金
属細線で電気的に接続された第1の半導体素子と、 前記第1の半導体素子の表面上に接着剤を介してその裏
面側で搭載され、前記配線基板の配線電極と第2の金属
細線で電気的に接続された第2の半導体素子との少なく
とも2つの半導体素子を有し、 前記配線基板上の前記第1の半導体素子、前記第2の半
導体素子および前記第1の金属細線,第2の金属細線の
外囲を含む配線基板上面が封止樹脂で封止された積層型
半導体装置であって、 前記第1の金属細線は前記第1の半導体素子側に湾曲し
た凹部を有していることを特徴とする積層型半導体装
置。
3. A wiring board having a wiring electrode, and a back side thereof is mounted on the wiring board via an adhesive on the wiring board, and electrically connected to the wiring electrode of the wiring board and the first thin metal wire. A first semiconductor element connected to the first semiconductor element, mounted on the front surface of the first semiconductor element via an adhesive on the back side, and electrically connected to a wiring electrode of the wiring board by a second thin metal wire. And at least two semiconductor elements, the first semiconductor element, the second semiconductor element, the first metal thin wire, and the second metal thin wire on the wiring board. A stacked semiconductor device in which an upper surface of a wiring board including an outer periphery is sealed with a sealing resin, wherein the first thin metal wire has a curved concave portion on the first semiconductor element side. A stacked semiconductor device.
【請求項4】 第2の金属細線は第2の半導体素子側に
湾曲した凹部を有していることを特徴とする請求項3に
記載の積層型半導体装置。
4. The stacked semiconductor device according to claim 3, wherein the second thin metal wire has a curved concave portion on the side of the second semiconductor element.
【請求項5】 凹部は金属細線の中間部分に位置してい
ることを特徴とする請求項1〜請求項3のいずれかに記
載の積層型半導体装置。
5. The stacked semiconductor device according to claim 1, wherein the recess is located at an intermediate portion of the thin metal wire.
【請求項6】 配線基板は、上面に配線電極と、下面に
前記上面の配線電極と接続した端子電極とを有した配線
基板であることを特徴とする請求項1〜請求項3のいず
れかに記載の積層型半導体装置。
6. The wiring board according to claim 1, wherein the wiring board has a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface. 3. The stacked semiconductor device according to item 1.
【請求項7】 第1の半導体素子または第2の半導体素
子の面積と配線基板の面積とは、前記配線基板の面積が
大きい条件で略同等の大きさで構成されてチップサイズ
パッケージを構成していることを特徴とする請求項1〜
請求項3のいずれかに記載の積層型半導体装置。
7. An area of the first semiconductor element or the second semiconductor element and an area of the wiring board are substantially equal to each other under the condition that the area of the wiring board is large to constitute a chip size package. Claim 1 characterized by the fact that
The stacked semiconductor device according to claim 3.
【請求項8】 上面に配線電極と、下面に前記上面の配
線電極と接続した端子電極とを有した配線基板に対し
て、樹脂を介してその表面の電極パッドに突起電極が形
成された第1の半導体素子をフリップチップ接続し、前
記突起電極と前記配線基板の配線電極とを接続する第1
の工程と、 前記第1の半導体素子の裏面に対して、接着剤を介して
第2の半導体素子をその裏面側で接着搭載する第2の工
程と、 前記配線基板の配線電極と前記第2の半導体素子とを金
属細線で電気的に接続するともに、前記金属細線に前記
第2の半導体素子側に湾曲した凹部を形成する第3の工
程と、 前記配線基板の上面領域を封止樹脂で封止する第4の工
程とよりなることを特徴とする積層型半導体装置の製造
方法。
8. A wiring board having a wiring electrode on an upper surface and a terminal electrode connected to the wiring electrode on the upper surface on a lower surface, wherein a protruding electrode is formed on an electrode pad on the surface via a resin. A first semiconductor element that is flip-chip connected to connect the protruding electrode to a wiring electrode of the wiring board;
A second step of bonding and mounting a second semiconductor element on the back side of the first semiconductor element via an adhesive to the back side of the first semiconductor element; and a wiring electrode of the wiring board and the second step. A third step of electrically connecting the semiconductor element with a thin metal wire and forming a curved concave portion on the second semiconductor element side in the thin metal wire; and sealing the upper surface region of the wiring board with a sealing resin. A method of manufacturing a stacked semiconductor device, comprising a fourth step of sealing.
【請求項9】 第1の工程、第2の工程、第3の工程、
第4の工程は、その上面に複数の半導体素子が個々に搭
載されるもので、また上面に個々の半導体素子に対応し
た配線電極が設けられ、下面には上面の配線電極と基板
内部で接続した端子電極が設けられ、個々の半導体素子
単位ごとに分割され得る構造の1枚の大型の配線基板に
対して各々行い、最終工程として、個々の積層型半導体
装置に切断分離する工程を有することを特徴とする請求
項8に記載の積層型半導体装置の製造方法。
9. A first step, a second step, a third step,
In the fourth step, a plurality of semiconductor elements are individually mounted on the upper surface, wiring electrodes corresponding to the individual semiconductor elements are provided on the upper surface, and the wiring electrodes on the upper surface are connected to the wiring electrodes on the lower surface inside the substrate. A large-sized wiring board having a structure in which terminal electrodes are provided and which can be divided into individual semiconductor element units, and having a step of cutting and separating into individual stacked semiconductor devices as a final step. The method for manufacturing a stacked semiconductor device according to claim 8, wherein:
【請求項10】 配線基板の配線電極と第2の半導体素
子とを金属細線で電気的に接続するとともに、前記金属
細線に前記第2の半導体素子側に湾曲した凹部を形成す
る第3の工程では、前記金属細線の中間部分に凹部を形
成することを特徴とする請求項8に記載の積層型半導体
装置の製造方法。
10. A third step of electrically connecting a wiring electrode of a wiring board and a second semiconductor element with a thin metal wire and forming a curved concave portion on the side of the second semiconductor element in the thin metal wire. 9. The method according to claim 8, wherein a recess is formed in an intermediate portion of the thin metal wire.
JP2001095763A 2001-03-29 2001-03-29 Laminated semiconductor device and manufacturing method therefor Pending JP2002299549A (en)

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Publication Number Publication Date
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Family

ID=18949774

Family Applications (1)

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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100884662B1 (en) * 2004-07-15 2009-02-18 다이니폰 인사츠 가부시키가이샤 Semiconductor device and semiconductor device producing substrate and production methods therefor
US7943427B2 (en) 2004-07-15 2011-05-17 Dai Nippon Printing Co., Ltd. Semiconductor device, substrate for producing semiconductor device and method of producing them
JP2015043465A (en) * 2014-12-01 2015-03-05 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. Semiconductor device
CN108682303A (en) * 2018-05-14 2018-10-19 云谷(固安)科技有限公司 Flexible display substrates, flexible display screen and electric terminal equipment

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100884662B1 (en) * 2004-07-15 2009-02-18 다이니폰 인사츠 가부시키가이샤 Semiconductor device and semiconductor device producing substrate and production methods therefor
US7943427B2 (en) 2004-07-15 2011-05-17 Dai Nippon Printing Co., Ltd. Semiconductor device, substrate for producing semiconductor device and method of producing them
JP2015043465A (en) * 2014-12-01 2015-03-05 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. Semiconductor device
CN108682303A (en) * 2018-05-14 2018-10-19 云谷(固安)科技有限公司 Flexible display substrates, flexible display screen and electric terminal equipment
CN108682303B (en) * 2018-05-14 2020-05-19 云谷(固安)科技有限公司 Flexible display substrate, flexible display screen and electronic terminal equipment

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